Abstract: Systems and methods described herein provide for determining priority levels within one or more data streams established between a host computing device and a storage device. Data streams that have been assigned a sufficiently high priority may be provided additional processing resources available within the storage device. These additional processing resources may include an increased number of write buffers, superblocks, and access to other ancillary resources that facilitate an increased level of performance compared to data streams not provided additional processing resources. The assignment of priority to the data streams can occur through the use of one or more priority identifiers. Many types and scales of priority identifiers may be used. The establishing of this system of priority identifiers can occur by the storage device notifying the hose of the accepted priority identifier usage. In other embodiments, the storage device may come preconfigured with a priority indication system and scale.

Abstract: Apparatuses and methods for writing data to a memory array are disclosed. When data is duplicative across multiple data lines, data may be transferred across a single line of a bus rather than driving the duplicative data across all of the data lines. The data from the single data line may be provided to the write amplifiers of the additional data lines to provide the data from all of the data lines to be written to the memory. In some examples, error correction may be performed on data from the single data line rather than all of the data lines.

Abstract: Technologies for improving enumeration of universal serial bus (USB) devices over a media agnostic USB (MAUSB) connection are disclosed. In the illustrative embodiment, an MAUSB device may send USB configuration data to a host compute device. The host compute device may then perform a virtual enumeration of the USB devices based on the USB configuration data without necessarily communicating with the USB devices. The MAUSB device may perform an enumeration of the USB devices on behalf of the host compute devices without necessarily communicating with the host compute device. The USB devices may not be aware or have any indication that the USB device is not communicating with the host compute device during the enumeration process. Such an approach may improve the latency of USB enumeration over an MAUSB connection.

Abstract: A method may be provided for a system having a logic device interfaced between a management controller and a plurality of subsystems, wherein the logic device includes a plurality of purpose-built engines, each purpose-built engine configured to perform single-wire communication with one or more subsystems in accordance with a particular protocol associated with such purpose-built engine and a purpose-built engine group switch interfaced between the plurality of purpose-built engines and a plurality of connectors for communicatively coupling the plurality of subsystems to the logic device. The method may include establishing, with a purpose-built engine group switch, a plurality of communication routes based on one or more switch control signals, wherein each route of the plurality of communication routes is established between a respective purpose-built engine and a respective connector.

Abstract: Methods and apparatus are provided for processing communications. In one aspect, a method comprises receiving first data from a first device and receiving second data from a second device, wherein the first data has a longer latency constraint than the second data. The method also comprises sending the first data over a network link to a processing node for processing the first data.

Abstract: A USB integrated circuit includes three TX connecting component pairs and three RX connecting component pairs. The first TX connecting component pair and the first RX connecting component pair are respectively coupled to the first TX pin pair and the first RX pin pair of the first USB connector. The second TX connecting component pair and the second RX connecting component pair are respectively coupled to the first TX pin pair and the first RX pin pair of a second USB connector. The third TX connecting component pair is coupled to the second TX pin pair of the first USB connector or to the second TX pin pair of the second USB connector. The third RX connecting component pair is coupled to the second RX pin pair of the first USB connector or to the second RX pin pair of the second USB connector.

Abstract: A chip and an interface conversion device are provided. The chip includes first, second, third, fourth, fifth and sixth pads. The first and second pads are coupled to first and second SBU pins of a USB connector respectively. The fourth and the sixth pads are coupled to first and second pins of an AUX channel of a DP connector respectively. When the chip operates in a first mode, first and second AUX channel signals generated by the chip are transmitted to the third and fifth pads respectively, a voltage of the fourth pad is weakly pulled down, and a voltage of the sixth pad is weakly pulled up. When the chip operates in a second mode, one of the first and second pads is connected to the fourth pad, and the other one of the first and second pads is connected to the sixth pad.

Abstract: Communication devices and methods of data communication are herein disclosed. In some aspects, a communication device may include a host and a modem interconnected by an interface. The host includes a host processor configured to control components of the communication device and to communicate with the modem via the interface. The modem includes a modem processor configured to control components of the modem and to communicate with the host via the interface. The modem processor is further configured to communicate information on a reduced activity state and a time remaining until a next event of the modem to the host processor. The host processor is further configured to reduce an operation of at least one component of the communication device based on receipt of the information on the reduced activity state of the modem and the time remaining until the next event of the modem.

Abstract: A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.

Abstract: Technologies for improving enumeration of universal serial bus (USB) devices over a media agnostic USB (MAUSB) connection are disclosed. In the illustrative embodiment, an MAUSB device may send USB configuration data to a host compute device. The host compute device may then perform a virtual enumeration of the USB devices based on the USB configuration data without necessarily communicating with the USB devices. The MAUSB device may perform an enumeration of the USB devices on behalf of the host compute devices without necessarily communicating with the host compute device. The USB devices may not be aware or have any indication that the USB device is not communicating with the host compute device during the enumeration process. Such an approach may improve the latency of USB enumeration over an MAUSB connection.

Abstract: According to one embodiment, a data transmission device, includes: a wireless transmitting circuitry transmitting a wireless signal; measurement circuitry measuring a state of a measurement target at a first sampling rate and acquiring a first measurement value of the state of the measurement target; and controlling circuitry determining whether the first measurement value satisfies a first condition based on a first threshold value. The wireless transmitting circuitry transmits the plurality of first measurement values acquired before the first condition is satisfied when the first condition is satisfied. The measurement circuitry switches the first sampling rate to a second sampling rate higher than the first sampling rate when the first condition is satisfied, measures a state of the measurement target at the second sampling rate, and acquires a second measurement value of the state of the measurement target. The wireless transmitting circuitry transmits the second measurement value.

Abstract: Technologies for improving enumeration of universal serial bus (USB) devices over a media agnostic USB (MAUSB) connection are disclosed. In the illustrative embodiment, an MAUSB device may send USB configuration data to a host compute device. The host compute device may then perform a virtual enumeration of the USB devices based on the USB configuration data without necessarily communicating with the USB devices. The MAUSB device may perform an enumeration of the USB devices on behalf of the host compute devices without necessarily communicating with the host compute device. The USB devices may not be aware or have any indication that the USB device is not communicating with the host compute device during the enumeration process. Such an approach may improve the latency of USB enumeration over an MAUSB connection.

Abstract: Enhanced communications over a Universal Serial Bus (USB) Type-C cable are disclosed. In one aspect, a link control circuit is provided in a USB host to enable one or more communication circuits in the USB host to transmit and receive protocol-specific data over a sideband use (SBU) interface according to communication protocols that may or may not be USB compliant. In another aspect, the link control circuit is provided in a USB client to enable one or more communication circuits in the USB client to transmit and receive protocol-specific data over the SBU interface according to communication protocols that may or may not be USB compliant. By configuring the USB host and the USB client to support multi-protocol communications via the SBU interface, it is possible to enable more flexible architectural design in mobile communication devices for enhanced performance and reduced costs.

Abstract: The invention relates to managing operation of a spanning tree protocol process in a network bridge having a central controller and one or more port controllers, each for controlling one or more ports of said network bridge. The spanning tree protocol process comprises a plurality of state machines including a Port Information state machine. The Port Information state machine comprises an UPDATE state and a plurality of other states. The invention involves running a Protocol Manager on a central controller, wherein the Protocol Manager owns the UPDATE state such that updates are carried out by the Protocol Manager. The Neighbor Managers on each of the port controllers owns the plurality of other states of the Port Information state machine, such that updates are carried out by the respective Neighbor Manager on said port controller. This allows the Protocol Manager and the Neighbor Managers to operate without having to force one to pause whilst work is done on the other.

Abstract: A hot swappable device includes a port, a firmware module, and an interrupt masking module. The port includes a Peripheral Component Interface express Physical Layer, and the Peripheral Component Interface express Physical Layer includes multiple lanes lanes. The Peripheral Component Interface express Physical Layer detects an analog signal in each of the multiple lanes, when it is detected that an amplitude of an analog signal in one of the multiple lanes is less than a preset threshold, generates an ALOS signal corresponding to the lane, and transmits the ALOS signal to the interrupt masking module. The interrupt masking module generates an ALOS interrupt signal corresponding to the lane and sends the ALOS interrupt signal to the firmware module. If the firmware module receives, in a preset time period, an ALOS interrupt signal corresponding to each lane, the firmware module resets the port.

Abstract: A management system (or controller) is configured to send commands to robotic components of different types (e.g., different command types, byte order types, etc.). Once configured, a translation component may be deployed to translate some commands to some robotic components that use a different command type than a native command type used by the management system. The management system uses a native byte order type to create commands, which may be big endian or little endian. While some of the robotic components (e.g., first robotic components) may also use the native byte order type, other robotic components (e.g., second robotic components) may use a non-native byte order type (in relation to the management system). For example, the native byte order type may be big endian while the non-native byte order type may be little endian, or vice versa.

Abstract: Disclosed is a method for changing a role over control authorization performed in a communication apparatus. The method may comprise receiving, from a second controller, a role-request message requesting a role change of the second controller to a master controller; transmitting a role status request message for confirmation of the role change of the second controller to a first controller which is a previous master controller; and determining whether to accept the role change of the second controller according to a role status response message received from the first controller. Therefore, reliability may be guaranteed when a role of master controller is changed.

Abstract: A method for data transmission within a server that includes a processor, a main memory, a southbridge, a chipset, and a buffer, the chipset including a baseboard management controller (BMC), the method including: obtaining memory information about a segment of the peripheral memory allocated for a peripheral controller included in the chipset; transmitting a notifying command to the BMC indicating a data size of to-be-transmitted data associated with a booting operation of the server; transmitting at least a part of the to-be-transmitted data to the segment, according to the memory information; and transmitting a standby command to the BMC indicating that the part of the to-be-transmitted data has been stored in the segment.

Abstract: A system-on-a-chip (SoC) includes a master module and a first adapter module. The master module includes an upstream interface and a downstream interface. The upstream interface is coupled to a host unit for receiving a write burst or a read burst therefrom. The master module is configured to convert the write burst or the read burst into a series of access requests to the downstream interface. The first adapter module includes an input interface, an output interface, and an endpoint interface, and an address Base Address Register (BAR). The input interface is coupled to the downstream interface of the master module. The output interface is coupled to a second adapter module or to a termination module. The endpoint interface is coupled to a first functional unit or to a third adapter module. The first adapter module is configured to detect a respective access request corresponding to the address BAR.

Abstract: A system that includes a PCIe hierarchy may utilize a ring controller for message handling. Nodes acting as the root complex or as endpoint devices may include such ring controllers, portions of which may be implemented by dedicated circuitry on each node. The ring controllers may receive posted transactions representing messages, may return flow control credits for those transactions, may classify each message as to its type, and may write information about each message to a respective ring buffer storing information about messages of that type. A processor (or processing logic/circuitry) on the node may subsequently retrieve messages from the ring buffers and process them. The sizes and locations of the ring buffers in memory may be configurable by software (e.g., by writing to registers within the ring controllers). The message types may include correctable and non-correctable error messages, and non-error messages (including, but not limited to, vendor-defined messages).

Abstract: A method, data storage device and computer program product for efficiently configuring different types of hardware components. A Universal Serial Bus (USB) key is preloaded with multiple profiles, where each profile contains a configuration file(s) associated with a particular type of hardware component. Upon plugging the USB key into a hardware component, the USB key recognizes the type of hardware component based on the properties of the hardware component available on the USB interface. The USB key identifies a profile containing the configuration file(s) associated with the recognized type of hardware component. The USB key then presents the configuration file(s) contained in the identified profile to the connected hardware component. Such a process may be repeated for configuring another type of hardware component. In this manner, the user is able to efficiently configure different types of hardware by having the USB key function as multiple USB keys.

Abstract: A method, data storage device and computer program product for efficiently configuring different types of hardware components. A Universal Serial Bus (USB) key is preloaded with multiple profiles, where each profile contains a configuration file(s) associated with a particular type of hardware component. Upon plugging the USB key into a hardware component, the USB key recognizes the type of hardware component based on the properties of the hardware component available on the USB interface. The USB key identifies a profile containing the configuration file(s) associated with the recognized type of hardware component. The USB key then presents the configuration file(s) contained in the identified profile to the connected hardware component. Such a process may be repeated for configuring another type of hardware component. In this manner, the user is able to efficiently configure different types of hardware by having the USB key function as multiple USB keys.

Abstract: A method and apparatus for reliable I/O performance anomaly detection. In one embodiment of the method, input/output (I/O) performance data values are stored in memory. A first performance data value is calculated as a function of a first plurality of the I/O performance data values stored in the memory. A first value based on the first performance data value is calculated. An I/O performance data value is compared to the first value. A message is generated in response to comparing the I/O performance value to the first value.

Abstract: A processing device includes a plurality of input units configured to input a process request; a plurality of processing units configured to execute a process corresponding to the process request input by the plurality of input units; a power control unit configured to transfer the processing device into a power saving state and to transfer the processing device back to a regular state from the power saving state; and an operation suppression control unit configured to send an operation suppression request to the plurality of input units and the plurality of processing units before the power control unit transfers the processing device into the power saving state, and to send an operation suppression release request to the plurality of input units and the plurality of processing units when the power control unit transfers the processing device back to the regular state from the power saving state.

Abstract: A method for controlling media devices by an electronic device is described. The method includes receiving a first control signal from a first media device in a first media device control network. The method also includes generating a second control signal based on the first control signal and a second media device in a second media device control network. The method further includes sending the second control signal to the second media device.

Abstract: In an image forming apparatus in which a first board including a first central processing unit (CPU) and a second board including a second CPU communicate with each other to control image processing, a monitoring unit monitors whether processing executed by the second CPU is normal. If the monitoring unit determines that the processing executed by the second CPU is not normal, a notification unit notifies the first CPU. The first CPU resets the second board according to the notification.

Abstract: The present disclosure is directed to a NoC interconnect that consolidates one or more Network on Chip functions into one Network on Chip. The present disclosure is further directed to a Network on Chip (NoC) interconnect comprising a plurality of first agents, wherein each agent can be configured to communicate with other ones of the plurality of first agents. NoC of the present disclosure can further include a second agent configured to perform a NoC function, and a bridge associated with the second agent, wherein the bridge can be configured to packetize messages from the second agent to the plurality of first agents, and to translate messages from the plurality of first agents to the second agent.

Abstract: An apparatus includes a memory and a processor. The processor is configured to send to a storage device a request from an application to retrieve data from the storage device, so as to cause the data to be transferred from the storage device to the memory, to send to the application an acknowledgement that the requested data is available in the memory before the data has been fully transferred from the storage device to the memory, and, when the fetched data is ready in the memory, to provide the data to the application.

Abstract: A structure and method of allocating read buffers among multiple bus agents requesting read access in a multi-processor computer system. The number of outstanding reads a requestor may have based on the current function it is executing is dynamically limited, instead of based on local buffer space available or a fixed allocation, which improves the overall bandwidth of the requestors sharing the buffers. A requesting bus agent may control when read data may be returned from shared buffers to minimize the amount of local buffer space allocated for each requesting agent, while maintaining high bandwidth output for local buffers. Requests can be made for virtual buffers by oversubscribing the physical buffers and controlling the return of read data to the buffers.

Abstract: Embodiments of the invention include a communication interface and protocol for allowing communication between devices, circuits, integrated circuits and similar electronic components having different communication capacities or clock domains. The interface supports communication between any components having any difference in capacity and over any distance. The interface utilizes request and acknowledge phases and signals and an initiator-target relationship between components that allow each side to throttle the communication rate to an accepted level for each component or achieve a desired bit error rate.

Abstract: One example embodiment provides a method and system where a node in a utility network registers with one or more access point devices associated with one or more local area utility networks. The utility node generates a unique network address using a network address prefix of a network address associated with the access point device. The utility node registers with a DNS server. Messages sent to the utility node are routed through the access point corresponding to the received prefix used to generate the unique network address for the utility node. The network address for the utility node and access point may be IPv6 addresses and the network address prefix may be an IPv6 prefix, or may be an IPv4 address.

Abstract: An apparatus and method of emulating a hardware accelerator engine over an interconnect link such as PCI Express (PCIe) link. In one embodiment, the accelerator emulation mechanism is implemented inside a PCIe Host Bridge which is integrated into a host IC or chipset. The accelerator emulation mechanism provides an interface compatible with other integrated accelerators thereby eliminating the overhead of maintaining different programming models for local and remote accelerators. Co-processor requests issued by threads requesting a service (client threads) targeting remote accelerator are queued and sent to a PCIe adapter and remote accelerator engine over a PCIe link. The remote accelerator engine performs the requested processing task, delivers results back to host memory and the PCIe Host Bridge performs co-processor request completion sequence (status update, write to flag, interrupt) include in the co-processor command.

Abstract: Methods and apparatus relating to techniques for Electromagnetic Interference (EMI) mitigation on high-speed lanes using false stall are described. In one embodiment, protocol logic determines whether to perform a false stall operation on a lane in response to a determination that no data is to be sent over the lane and that data is being transmitted over the lane. The false stall operation includes sending one or more training symbols (e.g., immediately) after an End Of Burst (EOB) signal over the lane, instead of allowing the lane to stall. Other embodiments are also disclosed.

Abstract: According to one aspect of the teachings herein, a system includes first and second modules that respectively anchor host-side and device-side ends of an intermediate transport link that interconnects a USB host to a USB device. The system detects when the host activates an isochronous endpoint in the device for an isochronous IN data transaction, and the second module autonomously generates data requests for the device and forwards the isochronous data output from the device towards the first module. In turn, the first module buffers the data and provides it to the host in response to host's data requests. However, the first module blocks host requests from propagating to the device and it NACKs host requests until forwarded data is available from the second module. Such operation remains transparent to the host and device, while avoiding USB timing violations, even for extended intermediate transport links.

Abstract: A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals from a USB host and independently provides responses required by USB specification within the required time frame. The upstream processor also contains storage for descriptors for a device associated with this upstream processor. The main controller obtains the descriptors by commanding the downstream processor, and passes them to the upstream processor. The downstream processor connectable to USB-compliant devices accepts the USB signals from the USB-compliant devices and provides responses required by USB specification within the required time frame. The main controller interconnects the upstream and downstream processors, and provides timing independence between upstream and downstream timing. The main controller also commands the downstream processor to obtain device descriptors independent of the USB host.

Abstract: A configurable 2-wire/3-wire serial communications interface (C23SCI), which includes start-of-sequence (SOS) detection circuitry and sequence processing circuitry, is disclosed. When the SOS detection circuitry is coupled to a 2-wire serial communications bus, the SOS detection circuitry detects an SOS of a received sequence based on a serial data signal and a serial clock signal. When the SOS detection circuitry is coupled to a 3-wire serial communications bus, the SOS detection circuitry detects the SOS of the received sequence based on a chip select (CS) signal. In response to detecting the SOS, the SOS detection circuitry provides an SOS detection signal to the sequence processing circuitry, which initiates processing of the received sequence using the serial data signal and the serial clock signal. The received sequence is associated with one of multiple serial communications protocols.

Abstract: An automatically configurable 2-wire/3-wire serial communications interface (AC23SCI), which includes start-of-sequence (SOS) detection circuitry and sequence processing circuitry, is disclosed. When the SOS detection circuitry is coupled to a 2-wire serial communications bus, the SOS detection circuitry detects an SOS of a received sequence based on a serial data signal and a serial clock signal. When the SOS detection circuitry is coupled to a 3-wire serial communications bus, the SOS detection circuitry detects the SOS of the received sequence based on a chip select (CS) signal. The SOS detection circuitry provides an indication of detection of the SOS to the sequence processing circuitry, which initiates processing of the received sequence using the serial data signal and the serial clock signal upon the detection of the SOS. As such, the AC23SCI automatically configures itself for operation with some 2-wire and some 3-wire serial communications buses without external intervention.

Abstract: An apparatus for forwarding an Fiber Channel over Ethernet (FCoE) data frame into an Ethernet network comprising a processor configured to receive a data frame on a input port, obtain a first destination address and a virtual local area network identifier (VID), determine whether the first destination address and the VID matches an entry within a forwarding table, construct a key when the first destination address and VID matches the entry and the data frame is a FCoE frame, and forward the data frame as an outgoing data frame via an output port when the key matches a rule that permits forwarding the data frame.

Abstract: Described embodiments provide a system having a bridge for connecting two different processor buses. The bridge receives a request from a first bus, the request having an identification field having a value. The request is then entered into one of a plurality of buffers having requests therein with the same identification field values. Which buffer receives the request may be based on a variety of techniques, such as random, least recently used, most full, prioritized, or sequential. Next, the buffered request is transmitted over a second bus. A response to the request is eventually received from the second bus, the response is transmitted over the first bus, and the request is then removed from the buffer. By entering the received request to the buffer with request with the same identification value, there is a reduced possibility of head-of-line request blocking when compared to a single buffer implementation.

Abstract: An integrated circuit (IC) device can include a serial communication first interface (I/F) circuit electrically coupled to first physical connections of the IC device, and configured to respond to communication signals received at the first physical connections; at least one serial communication second interface (I/F) circuit electrically coupled to second physical connections of the IC device, and configured to enable data transactions over the second physical connections; and a repeater circuit configured to bypass the first I/F circuit and enable serial communication signals to be transmitted from the first physical connections to the second physical connections. Systems including such an IC device and related methods are also disclosed.

Abstract: Techniques for isochronous data transfer between different memory-mapped domains in a distributed system. A method includes configuring an isochronous engine with an isochronous period. The method further includes transferring data over a memory-mapped fabric from a first memory to a second memory during a specified portion of a cycle of the isochronous period. The first memory is comprised in a first device in a first memory-mapped domain of the memory-mapped fabric and the second memory is comprised in a second device in a second memory-mapped domain of the memory-mapped fabric. The method may further comprise translating one or more addresses related to the transferring. The memory-mapped fabric may be a PCI-Express fabric. The transferring may be performed by a DMA controller. A non-transparent bridge may separate the first and the second memory-mapped domains and may perform the translating.

Abstract: A telecommunications chassis includes an array of mezzanine card interfaces and a carrier module coupled to the mezzanine card interfaces to control and manage mezzanine cards connected to the mezzanine card interfaces.

Abstract: This disclosure provides a network security architecture that permits installation of different software security products as virtual machines (VMs). By relying on a standardized data format and communication structure, a general architecture can be created and used to dynamically build and reconfigure interaction between both similar and dissimilar security products. Use of an integration scheme having defined message types and specified query response framework provides for real-time response and easy adaptation for cross-vendor communication. Examples are provided where an intrusion detection system (IDS) can be used to detect network threats based on distributed threat analytics, passing detected threats to other security products (e.g., products with different capabilities from different vendors) to trigger automatic, dynamically configured communication and reaction.

Abstract: An apparatus providing for a secure execution environment is presented. The apparatus includes a microprocessor and a secure non-volatile memory. The microprocessor is configured to execute non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus, and where the secure application program is executed in a secure execution mode. The microprocessor has secure execution mode logic that is configured to monitor instructions within the secure application program, and that is configured to preclude execution of certain instructions. The secure non-volatile memory is coupled to the microprocessor via a private bus, and is configured to store the secure application program, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor.

Abstract: Techniques for management of target devices are provided. User input for management of a target device may be received. The user input may be converted into a first format. The first format may be encapsulated into a second format and sent over a communications channel. The second format may be un-encapsulated to recover the first format. The first format may be provided to the target devices.

Abstract: A method of operation of a storage controller system includes: accessing a first controller having a synchronization bus; accessing a second controller, by the first controller, through the synchronization bus; and receiving a first transaction layer packet by the first controller including performing a multi-cast transmission between the first controller and the second controller through the synchronization bus.

Abstract: The invention relates to a receiving station (10) comprising a first physical connection port (20) intended for a first host equipment item and at least one second physical connection port (22) intended for at least one second host equipment item, detection means (24, 34) of host equipment connected to the ports, and the means (30) of automatic selection of combined use modes of the resources of the receiving station and/or connected host equipment, controlled by the detection means (24, 34). Application to handheld portable equipment.

Abstract: An IEEE 802.3 compliant physical layer device provides efficient loading of configuration information of the physical layer device. The configuration information is written into a volatile memory in the physical layer device, and then uploaded to at least one EEPROM. The configuration information is downloaded to the volatile memory during startup of the physical layer device. The system controller can also directly access the EEPROMs, bypassing the volatile memory. By providing a bridge between the system controller and the EEPROMs and providing additional bits in the volatile memory of the physical layer device, the system controller can read and write the EEPROMs one byte at a time. During reset time, the content of the EEPROMs is written to registers in the physical layer device to configure the physical layer device.

Abstract: A method is included for loading a main loadable file and at least one optional loadable file during initialization of a computer system. The method includes loading a main loadable file which includes a resident portion and an input/output network interface software component. The resident portion is a utilization software component configured to use transmission protocols. The method also includes determining which optional loadable files are required to be loaded. The optional loadable files each include an optional portion. The method also includes loading the optional loadable files which contain optional portions corresponding to required protocols.

Abstract: Systems and methods to perform a register access are described. A particular method includes receiving a data frame at a bridge element of a plurality of bridge elements in communication with a plurality of server computers. The data frame may include a register access request and may be forwarded from a controlling bridge in communication with the plurality of bridge elements. A register may be accessed and execution of the register access request may be initiated in response to receiving the data frame.