Abstract: A virtualization of the internal interconnection bus, which results in a virtualized switch or virtualized multi-ported bridge. In the case of a PCI Express switch, one embodiment includes virtualization of the undefined interconnection bus. In the case of a Multi-ported bridge, one embodiment includes virtualization of the internal PCI/PCI-X bus. Through virtualization of the internal interconnection bus, the integrated circuit topology (the physical bridges and ports) may advantageously be spatially separated and remotely distributed far a field from the host computer, yet appear to the host system and host system software as single physical device (i.e. a normal PCIe switch or a normal multi-ported bridge).

Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Abstract: An analog/digital switching circuit for connecting a primary electronic device to a peripheral electronic device, including D+ and D? signal lines connected to a primary electronic device, a first analog/digital switch connected to the D+ signal line, for multiplexing an input D+ signal to an output USB data signal or audio left or right signal, the multiplexed signal feeding into a peripheral device connector for connecting the primary device to a peripheral electronic device, a second analog/digital switch connected to the D? signal line, for multiplexing an input D? signal to an output USB data signal or audio right or left signal, the multiplexed signal feeding into the peripheral device connector, a headset left signal line connected to the primary device and to the output audio left signal of the first analog/digital switch, a headset right signal line connected to the primary device and to the output audio right signal of the second analog/digital switch, a first USB signal line connected to a USB conn

Abstract: Various techniques are disclosed for providing data retrieved from a memory device and furnished to a memory bus in response to a read operation to a local bus interface. For instance, a set of conductive traces may be provided that forms a communication path between the memory bus and the local bus interface, such that the communication path formed by the conductive traces bypasses a memory bus interface coupled to the memory bus. In this manner, the data furnished to the memory bus may be communicated directly to the local bus without first being communicated to the memory bus interface.

Abstract: The present invention helps to develop a smaller sized portable terminal without reducing the functions available for the user. A USB device which is detachable from the portable terminal is provided with a USB connector which is inserted into a USB part of the portable terminal, a power source terminal which comes into contact with a power supply terminal of the portable terminal, when the USB connector is inserted into the USB port of the portable terminal, and a screw which is engaged with a screw hole of the portable terminal. When the screw is engaged with the screw hole of the portable terminal, a switch inside the screw hole is pushed down due to a contact with the screw. The portable terminal detects mounting of the USB device by an output from the switch, and initiates power supplying from the power supply terminal of the portable terminal to the power source terminal of the USB device.

Abstract: Apparatus and method for bus matching. The method includes: receiving data transfer characteristics at a first endian mode and at a second endian mode; determining a connectivity of multiple devices to an interfacing bus in response to the data transfer characteristics and in response to a relationship between a width of the interfacing bus and a width of each device interface; wherein at least one device interface is connected in parallel to multiple interfacing bus portions; and configuring a control logic such as to provide control signals representative of a transfer of data over the interfacing bus; whereas the control logic is configured in response to the connectivity.

Abstract: A vehicle includes a high assurance processing system including a plurality of data processors coupled in parallel, a bridge coupled to the input/output processor, and an input/output processor coupled to the bridge for coupling to a sensor and an effector. Sensor data passes to the bridge through the input/output processor for processing by the parallel data processors, which generate redundant effector data for comparison by the bridge to detect errors. If data matches are found, data is transmitted to the effector.

Abstract: Methods and apparatuses that utilize a serial bus, such as a universal serial bus (USB), for communications between a communications network, a computing device, and an auxiliary device are disclosed. Some embodiments comprise methods handling sideband communications using serial buses. One or more of the embodiments comprise differentiating in-band data from out-of-band data, transferring information of the in-band data between a communications network and a computing device, and transferring information of the out-of-band data between the communications network and an auxiliary device. Some embodiments comprise an apparatus having a communications network interface, an auxiliary device interface, and a computing device interface. Of the interfaces, one or more may be a serial bus interface. The apparatus may differentiate between in-band and out-of-band data and communicate information of the out-of-band data to an auxiliary device. In some embodiments, the apparatus may also transfer control information.

Abstract: A system for implementing handshaking configuration to enable coordinated data execution in a computer system. The system includes a core logic component coupled to a system memory and a graphics processor coupled to the core logic component via a graphics bus. The graphics processor and the core logic component implement a configuration communication to selectively configure coordinated data execution between the graphics processor and the core logic component via communication across the graphics bus.

Abstract: Embodiments include methods, apparatus, and systems for converting resets in a shared I/O system. One embodiment includes a method that propagates a first type of reset from a host computer to a multi-function device that shares I/O operations with other hosts. The first type of reset is converted to a second type of reset to prevent the host from resetting functions bound to the other hosts at the multi-function device.

Abstract: Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a peer-to-peer request. If it is, the posted request is sent as a non-posted request. A limit on the number of pending non-posted requests is maintained and not exceed, such that deadlock is avoided. Another exemplary embodiment provides an arbiter that tracks a number of pending posted requests. When the number pending posted requests reaches a predetermined or programmable level, a Block Peer-to-Peer signal is sent to the arbiter's clients, again avoiding deadlock.

Abstract: A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals from a USB host and independently provides responses required by USB specification within the required time frame. The downstream processor connectable to USB-compliant devices accepts the USB signals from the USB-compliant devices and provides responses required by USB specification within the required time frame. The main controller interconnects the upstream and downstream processors, and provides timing independence between upstream and downstream timing.

Abstract: An interrupt controller for a disk controller includes an interrupt scanner module that receives a plurality of interrupt requests (IRQs) from a plurality of corresponding interrupt sources, performs a scan of respective vector values of the plurality of IRQs, and selectively outputs a priority based on the scan. An interrupt generation module receives the priority and generates at least one of a fast interrupt and a regular interrupt based on the priority.

Abstract: A computer system includes compute nodes coupled through a switch to shared or non-shared I/O devices. The switch includes a pool of bridge headers and virtual bridges coupling a root port of a compute node to each of one or more shared or non-shared I/O devices. The switch is configured to associate each of the virtual bridges with a respective one of the fixed pool of bridge headers, receive a packet including data identifying the root port and a shared or non-shared I/O device, and route the packet in response to comparing data in the packet to data in the bridge headers associated with the virtual bridges. The virtual bridges comprise a hierarchy of virtual bridges in which one virtual bridge connects the root port to the remaining virtual bridges of the hierarchy. The switch may change the associations between virtual bridges and bridge headers.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: A method and apparatus are provided that include creating an image of a page descriptor at a universal serial bus (USB) device, transferring the image of the page descriptor to a main memory, modifying a schedule list in a main memory based on the transferred image, identifying an active transaction in the modified schedule list, and providing code data to the USB device from the main memory based on the identified active transaction.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for addressing deficiencies of the art in respect to hypertransport-based switching for multi-CPU systems and for flexibly configurable multi-CPU supported hypertransport switching is provided. The design structure can include a hypertransport switching data processing system. The system can include a CPU and at least two I/O bridges. Each I/O bridge can provide a communications path for data driven to a corresponding peripheral device from the CPU. Notably, the system can include a flexibly configurable hypertransport switch. The switch can include a first configuration adapting the CPU to both of the I/O bridges, and a second configuration adapting the CPU to a first one of the I/O bridges and a second CPU to a second one of the I/O bridges.

Abstract: In one embodiment, the present invention includes a method including receiving a read request at a first buffer from a first one of multiple interfaces and forwarding the read request from the first buffer to a first memory controller of multiple memory controllers, where the first buffer is dedicated to the first memory controller. Other embodiments are described and claimed.

Abstract: Methods and apparatuses that utilize a serial bus, such as a universal serial bus (USB), for communications between a communications network, a computing device, and an auxiliary device are disclosed. Some embodiments comprise methods handling sideband communications using serial buses. One or more of the embodiments comprise differentiating in-band data from out-of-band data, transferring information of the in-band data between a communications network and a computing device, and transferring information of the out-of-band data between the communications network and an auxiliary device. Some embodiments comprise an apparatus having a communications network interface, an auxiliary device interface, and a computing device interface. Of the interfaces, one or more may be a serial bus interface. The apparatus may differentiate between in-band and out-of-band data and communicate information of the out-of-band data to an auxiliary device. In some embodiments, the apparatus may also transfer control information.

Abstract: An embodiment of the present invention includes a communication system configured to conform to SAS standard and causing communication between one or more hosts and a SATA/SAS device. The communication system includes a multi-port bridge device including two or more SAS ports through which the bridge device communicates to hosts. The multi-port bridge device further includes a SATA port through which the bridge device communicates to a SATA device, each said SAS ports having associated therewith addresses for identifying the ports, the bridge device operative to generate addresses unique to each SAS port and operative to communicate the port addresses, through a SAS frame, wherein identification of SAS ports is achievable even when the SATA device is inoperational.

Abstract: An IO processor includes an embedded central processing unit (CPU), a switch connected to the embedded CPU, an external CPU bus controller connected to the switch for optionally connecting to an external CPU, a first memory controller connected to the switch for connecting to a first memory, and a second memory controller connected to the switch for optionally connecting to a second memory. The IO processor may be connected to the external CPU, to the second memory, or be capable of connecting to external CPUs of different ranks, depending on the situation, so as to meet the cost considerations and the actual application requirements.

Abstract: A multi-core bus termination apparatus includes a location array and a plurality of drivers. The location array generates a plurality of location signals that indicate locations on the bus of a corresponding plurality of nodes that are coupled to the bus, where the locations comprise either an internal location or a bus end location. Each of the plurality of drivers has one of the corresponding plurality of nodes, and controls how the one of the corresponding plurality of nodes is driven responsive to a state of a corresponding one of the plurality of location signals. Each of the plurality of drivers has configurable multi-core logic. The configurable multi-core logic enables pull-up logic and first pull-down logic if the state indicates the bus end location. The configurable multi-core logic disables the pull-up logic and to enable the first pull-down logic and second pull-down logic if the state indicates the internal location.

Abstract: Embodiments of the invention address deficiencies of the art in respect to hypertransport-based switching for multi-CPU systems and provide a method, system and computer program product for flexibly configurable multi-CPU supported hypertransport switching. In one embodiment of the invention, a hypertransport switching data processing system can be provided. The system can include a CPU and at least two I/O bridges. Each I/O bridge can provide a communications path for data driven to a corresponding peripheral device from the CPU. Notably, the system can include a flexibly configurable hypertransport switch. The switch can include a first configuration adapting the CPU to both of the I/O bridges, and a second configuration adapting the CPU to a first one of the I/O bridges and a second CPU to a second one of the I/O bridges.

Abstract: There is described a method for coupling at least two independent bus systems and to a suitable device for carrying out said method, a cycle time TA, TB being assigned to each bus system and each data item from a sequence of data being transmitted to the bus of the respective bus system in its own cycle. A predetermined or predeterminable number of data items is buffered from a data sequence that is to be transmitted from the original bus system to the target bus system, and a respective data item is determined on the basis of the cycle time TB of the target bus system from the data buffered on the basis of cycle time TA of the original bus system.

Abstract: A weakly-ordered processing system implements an execution synchronization bus transaction, or “memory barrier” bus transaction, to enforce strongly-ordered data transfer bus transactions. A slave device that ensures global observability may “opt out” of the memory barrier protocol. In various embodiments, the opt-out decision may be made dynamically by each slave device asserting a signal, may be set system-wide during a Power-On Self Test (POST) by polling the slave devices and setting corresponding bits in a global observability register, or it may be hardwired by system designers so that only slave devices capable of performing out-of-order data transfer operations participate in the memory barrier protocol.

Abstract: A network interface is described in which a single computer bus is split over a long distance into two or more intercommunicating buses. On one bus, processing and applications are provided and on the other remote bus, peripheral and local controllers are provided. The buses communicate through a series of: bridge, a first communications controller, a second communications controller, and bridge. Between the communications controllers, a communication path provides long distance communication via a packet-switched network.

Abstract: A method for centralized link power management control (CLMC), performed by a north-bridge of a processing unit, comprises the following steps. A data transmission status of a bus is monitored. CLMC is activated to configure devices corresponding to the bus in order to speed up data transmission of the bus when detecting that the data transmission status of the bus is continually busy. CLMC is activated to configure devices corresponding to the bus in order to slow down data transmission of the bus when detecting that the data transmission status of the bus is continually idle.

Abstract: In the conventional bus control system, the interconnect section and the bridge section have the arbitration function. Meanwhile, the interconnect section and the bridge section were designed by different designers. Accordingly, a large number of man-hours are needed not only for designing the bridge section but also for inspecting the bridge section.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: A method and apparatus for creating USB peripheral device report descriptors: A short, compressed, report descriptor is stored in a peripheral device. This short report descriptor is transmitted to a USB wireless bridge and combined with templates stored in the bridge to create a USP report descriptor. Power is saved because less time is required to transmit the short report descriptor than would be required to transmit a full USB report descriptor. Hardware is also saved in the peripheral device since less memory is required to store the short report descriptors as compared to storing a full USB report descriptor.

Abstract: A telecommunications system and constituent two-wire interface module. The two wire interface module includes a logic component configured to communicate over the same pair of wires using different two-wire interface protocols depending on an input signal presented on a configuration input. This configurability allows the two-wire interface module to use the same two wires to communicate with a variety of other two-wire interface modules, even if those two-wire interface modules communicate using different two-wire interface protocols.

Abstract: A bridge device access system permits access to a locked bridge device coupled between a host and a storage device. The bridge device is unlocked by sending an unlock sequence of storage device verify commands from the host to the bridge device. Each verify command includes a start address and a length parameter, wherein the sequence of start addresses in the sequence of storage device verify commands is a pseudorandom sequence of hexadecimal values. The bridge device detects the unlock sequence and is unlocked. The host can send a bridge-access command as the first command after the unlock sequence. Bridge-access commands can include storage device commands that are interpreted by the bridge device as queries and/or instructions for performing various tasks. The bridge device processes the bridge-access command, performing a prescribed operation in response to the bridge-access command, and then immediately re-enters its locked state.

Abstract: A configuration space operation packet is received from a link. The configuration space operation packet is detected using a hardware mechanism. The configuration space operation packet is forwarded to a software-controlled entity for processing. A received packet can be detected as a configuration space operation packet from an address range of an address in a header of the received packet. The software-controlled entity can provide configuration space virtualisation.

Abstract: An electronic apparatus with a USB connection has a functional circuit with a processor, a parallel address data bus couple to the processor and a USB device controller circuit with a USB interface in parallel with said address/data bus. The apparatus contains an interface integrated circuit electronically between the USB connection on one hand and the parallel address/data interface and the USB interface on the other hand. The interface integrated circuit has external terminals for connecting to a USB bus, a transceiver capable of transceiving for both a USB host and a USB device, the transceiver having a USB interface, a host interface and a device interface. The USB interface is coupled to the USB connection. The device interface is connected to the external USB device controller circuit. A host controller is coupled to the host interface, the host controller being coupled to the functional circuits via the parallel data/address bus.

Abstract: A data transfer control device includes a PATA I/F connected to a PATA bus, an SATA I/F connected to an SATA bus, and a sequence controller that controls a transfer sequence. The PATA I/F includes a task file register (TFR). The sequence controller suspends transmission of a register FIS corresponding to an ATA packet command issued by a host to a device, and performs a dummy setting that causes the host to issue an ATAPI packet command using the TFR. The sequence controller transmits the register FIS corresponding to the ATA packet command to the device after the host has issued the ATAPI packet command.

Abstract: In one embodiment, the present invention includes a switch device to be coupled between a first semiconductor component and a processor node by interconnects of a communication protocol that provides for cache coherent transactions and non-cache coherent transactions. The switch device includes logic to handle cache coherent transactions from the first semiconductor component to the processor node, while the first semiconductor component does not include such logic. Other embodiments are described and claimed.

Abstract: A hard disk drive bracket including a bezel, a lever arm attached to the bezel rotatably between a closed position against the bezel and an open position apart from the bezel, and a unitarily formed body attached to the bezel. The lever arm includes an extension on the rotating end. The unitarily formed body includes a locking member adapted to secure the lever arm in the closed position and a release button arranged to release the locking member when the release button is depressed. The unitarily formed body may be adapted to serve as a horn attached to the bezel rotatably between a natural position in which the locking member impedes the path of the lever arm, and a forced position in which the locking member is clear of the path of the lever arm.

Abstract: A generic device controller unit system (10) includes a generic “true real time” peripheral device controller and a data and protocol communications interface that uses a common set of instructions from a meta-message set. The system (10) is generic, in that the system (10) is capable of connecting a processor (40) to any number of various peripheral devices (50), instead of being designed to interconnect a processor (40) only to a specific peripheral device (50). The system (10) interfaces between a standard non-true real time operating system and peripheral devices (50) in such a manner as to employ true real time peripheral device control using the meta-message set. The device controller of the system (10) allows a standard non-true real time operating system to send instructions from the meta-message set to implement true real time control of peripheral devices (50).

Abstract: To minimize the restriction on the number of available PCI devices although the assignable size of I/O space is limited, an arithmetic unit is provided with a configuration information acquisition device for acquiring the configuration information about PCI devices, an available space determination device for determining available space for each PCI device, and a configuration information notification device for notifying an operating system of the configuration information.

Abstract: An apparatus is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data processor core, and a functionally coupled data processor slave. Both the data processing master and the data processing slave are coupled to a common bus or common crossbar switch. The data processing device processes the data associated with transfers to or from the data processor slave. System masters will direct transactions that require data processing to the data processing slave, which will indirectly interact with the target memory slave. System masters will direct transactions that do not require data processing, directly to the target memory slave.

Abstract: Provided are a guaranteed services method and apparatus in bridged LAN. streams are transmitted through bridges to a plurality of listener stations in a distributed network, and each bridge performs filtering, stream group registration and authentication for the streams. Accordingly, quality of service (QoS) in a distributed network can be improved. Furthermore, streams to the plurality of listener stations can be guaranteed.

Abstract: A hard disk drive bracket includes a bezel, a lever arm attached to the bezel rotatably between a closed position against the bezel and an open position apart from the bezel, a release mechanism attached to the bezel including a locking member that latches the lever arm in the closed position and a release button arranged to unlatch the lever arm from the locking member when the release button is depressed, and a horn attached to the bezel translatably between a natural position apart from the release mechanism and a forced position that allows the horn and release mechanism to interact to unlatch the lever arm from the locking member. The horn and lever arm of the hard disk drive bracket may be adapted to serve as a cam that automatically depress the release button as the lever arm is being closed.

Abstract: An apparatus, system and method to facilitate I2C communication between a host device and a slave device where the slave device shares a common physical address with another slave device on the I2C bus. The apparatus includes a detection module to detect an incoming address on the I2C bus, a translation module to translate the incoming address to an outgoing address, and a communication module to communicate data between the host device and the slave device where the outgoing address matches the physical address of the slave device. In this manner, the present invention avoids address conflicts between commonly addressed slave devices while reducing costs, components, and complexities traditionally associated with dynamic addressing techniques and other prior art solutions to address conflicts.

Abstract: A method and apparatus for sharing peripheral devices between multiple execution domains of a hardware platform are described. In one embodiment, the method includes the configuration end-point devices, bridges and interconnects of a hardware platform including at least two execution domains. When a configuration requests is issued from an execution domain, the configuration requests may be intercepted. Hence, the received configuration request is not used to configure the peripheral end-points, bridges or interconnects of the hardware platform. Configuration information decoded from intercepted configuration request may be stored as virtual configuration information. In one embodiment, configuration information is read from a target of the configuration request to identify actual configuration information.

Abstract: An enhanced fibre channel adapter with multiple queues for use by different server processors or partitions. For a non-partitioned server, the OS owns the adapter, controls the adapter queues, and updates the queue table(s). An OS operator can obtain information from the fibre channel network about the fibre channel storage data zones available to the physical fibre channel adapter port and can specify that one or more zones can be accessed by a specific processor or group of processors. The processor or group of processors is given an adapter queue to access the zone or zones of storage data. This queue is given a new World Wide Port Name or new N-Port ID Virtualization identifier, to differentiate this queue from another queue that might have access to a different storage data zone or zones. For a partitioned server, one partition owns the adapter, controls the adapter queues, and updates the queue table(s).

Abstract: Embodiments of the present invention provide a media drive that is intended for reduction in power consumption required for serial communications to/from a host, and a power saving method thereof. In one embodiment, a HDD includes: a cache; a host interface for transferring, to a host, transfer data read out from the cache; a host interface manager that controls the execution of commands so as to generate a transfer unnecessary period during which a command and transfer data need not be exchanged with the host; and a MPU that brings a serial communication part of the host interface into a power save mode during the transfer unnecessary period. The host interface manager determines the optimum data transfer timing of transferring data from the cache to the host on the basis of a transfer rate at which data is transferred to the host, and a read rate at which data is read out from a disk into the cache.

Abstract: A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.

Abstract: In at least some embodiments, a method comprises emulating a Universal Serial Bus (USB) host controller at a computer system. The method further comprises using the emulated USB host controller to interface a remote management console with the computer system.

Abstract: Embodiments of the invention include a bus bridge that is capable of communicating with more than one MSC device coupled to it. In some embodiments, the bridge includes a LUN processor that translates different LUN numbers received from the bus into different addresses and LUNs for devices connected to the bridge. The bridge masks the fact that multiple MSC devices are coupled to it by reporting to the host that only a single device having multiple LUNs are coupled to the bridge.

Abstract: ASCII gateway to in-vehicle system provides bi-directional translation between multiplexed motor vehicle networks and industrial control and monitoring devices. Integrated hardware and software components provide data communications between motor vehicle electronic control module networks and RS-232 serial ASCII-text capable device, for industrial control and/or industrial automation application in manufacturing or assembly operations. Communications networks (CAN, SAE or ISO protocols) implemented inside motor vehicles pass data between electronic control modules that control operation of important vehicle components like engine, transmission and brake systems, have their messages converted to RS-232 serial ASCII-text; and from RS-232 serial ASCII-text converted to motor vehicle communications network by the system. Messages to monitor and/or control vehicle networks are generated by a serial ASCII-test capable device. Multiple vehicle protocols are supported by the system.