Abstract: A method and system to adapt communication links statically and/or dynamically to their individual link conditions on a platform. The communicatively coupled devices have logic to adapt one or more settings of a respective one or more communication links with another device based at least in part on a respective metric of received data patterns from the respective one or more communication links. The communicatively coupled devices in the platform have a back channel to allow feedback or information to be sent from one receiving device to a transmitting device in one embodiment of the invention.

Abstract: A system and method for verifying the receive path of an input/output device such as a network interface circuit. The device's operation with various different input sources (e.g., networks) and output sources (e.g., hosts, host buses) is modeled in a verification layer that employs multiple queues to simulate receipt of packets, calculation of destination addresses and storage of the packet data by the device. Call backs are employed to signal completion of events related to storage of packet data by the device and modeling of data processing within the verification layer. Processing of tokens within the verification layer to mimic the device's processing of corresponding packets is performed according to a dynamic DMA policy modeled on the device's policy. The policy is dynamic and can be updated or replaced during verification without interrupting the verification process.

Abstract: An I/O bridge device includes: a command receiver that receives a command signal indicating a command to a memory controller from a peripheral component; a converter that converts the command signal into a command packet including the command and identification information for identifying the command signal; a command transmitter that transmits the command packet to the memory controller; a response receiver that receives, from the memory controller, a response packet to the command packet, the response packet including the identification information; and a write command transmitter that transmits a write command signal to the peripheral component that is a transmission source of the command signal, the write command signal indicating a command for the writing a content of the response packet to an internal memory of the peripheral component.

Abstract: A switch apparatus capable of being coupled to a computer and a plurality of devices, the switch apparatus includes: a first bridge coupled to the computer; a second-bridge group coupled to the devices; and a controller for controlling the connection relationship between the first bridge and the second-bridge group, wherein the controller assigns physical identifiers having different bus identifiers to the plurality of devices, assigns logical identifiers to the devices in accordance with an identifier assigned to the first bridge in response to an instruction for reading connection states of the devices received from the computer when the computer is coupled to the first bridge, and converts a physical identifier and a logical identifier of a packet transmitted between the first bridge and the second-bridge group in accordance with the correspondence relationships between the physical identifiers and the logical identifiers.

Abstract: There is provided a storage system including a file server connecting to a computer over a network and a storage apparatus connecting to the file server connecting over the network, wherein the file server includes a first controller, the storage apparatus includes multiple storage devices having multiple storage areas and a second controller that controls accesses to the multiple storage areas, each of the multiple storage areas has at least one power saving mode among multiple power saving modes with different shift times from the power saving modes to a ready mode, the first controller, in response to the reception of data from the computer, sets an indicator relating to the performance of response to an access from the computer to the data and refers to the indicator of the data and selects a first storage area having the power saving mode satisfying the indicator, and the second controller stores the data to the first storage area.

Abstract: A method for adjusting a link speed and a computer system using the same are provided. The method is used after executing a boot block code and before executing a bus enumeration procedure. A testing step is executed using a maximum link speed supported by both a bridge and a peripheral device. If the test fails, the link speed is adjusted down until the test succeeds, thus automatically adjusting the link speed of the bridge.

Abstract: A method for clearing data stored in a complementary metal-oxide semiconductor (CMOS) chip of a computing device. The computing device further includes a CMOS jumper connected to the CMOS chip, and a general purpose input/output (GPIO) interface connected to the CMOS jumper. The method configures a GPIO pin of the GPIO interface as an output port, controls the GPIO pin to generate a GPIO signal with a high level, and outputs the GPIO signal with the high level to the CMOS jumper. After receiving a command of clearing data stored in the CMOS chip, the method pulls down the GPIO signal from the high level to a low level, to clear the data stored in the CMOS chip.

Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Abstract: A data processing system includes a processor core, a system memory coupled to the processor core, an input/output adapter (IOA), and an input/output (I/O) host bridge coupled to the processor core and to the IOA. The I/O host bridge includes a register coupled to receive I/O messages from the processor core, a buffer coupled to receive I/O messages from the IOA, and logic coupled to the register and to the buffer that services I/O messages received from the register and from the buffer.

Abstract: A device may include a first data path coupled between a first port and a data transfer section that enables data paths between the first data path and at least a second port and a third port. A second data path may be coupled between the first port and the second port that bypasses the data transfer section and is not coupled to the second or third ports.

Abstract: A data transfer system comprising a first bus interface, a second bus interface, a first-in-first-out memory, a controller and a message unit. The message unit is operable to queue a plurality of data transfer request messages from the first bus interface and the second bus interface. The controller is operable to process each data transfer request message and transfer data between the first bus interface, the first-in-first-out memory and the second bus interface. The controller is configured to calculate error detection codes (EDCs) and chain EDC values.

Abstract: A method and data processing system enables scheduling of atomic operations within a Peripheral Component Interconnect Express (PCIe) architecture during page migration. In at least one embodiment, firmware detects the activation of a page migration operation. The firmware notifies the I/O host bridge, which responds by setting an atomic operation stall (AOS) bit to a pre-established value that indicates that there is an ongoing migration within the memory subsystem of a memory page that is mapped to that I/O host bridge. When the AOS bit is set to the pre-established value, the I/O host bridge prevents/stalls any received atomic operations from completing. The I/O host bridge responds to receipt of receipt of an atomic operation by preventing the atomic operation from being initiated within the memory subsystem, when the AOS bit is set to the pre-established value. The AOS bit is reset when the migration operation has completed.

Abstract: Systems and methods to perform a register access are described. A particular method includes receiving a data frame at a bridge element of a plurality of bridge elements in communication with a plurality of server computers. The data frame may include a register access request and may be forwarded from a controlling bridge in communication with the plurality of bridge elements. A register may be accessed and execution of the register access request may be initiated in response to receiving the data frame.

Abstract: The present invention may be related to a bridge for communications between a first computing device and a second computing device in a data communication system. The bridge may include a first interface, a second interface and a control module. The first interface may be adapted to couple with the first computing device. The second interface may be adapted to couple with the second computing device. The control module may be configured to process a file input/output (I/O) command from the first computing device so as to allow the first computing device to have access to at least one of data or resource of the second computing device via the first and second interfaces. Moreover, the control module may further include a parser, a decoder and a micro processor. The parser may be configured to identify whether the file I/O command includes an encoded controller command and retrieve the encoded controller command from the file I/O command if the file I/O command includes an encoded controller command.

Abstract: A system includes a data holding module that at least one of stores and receives data based on a first clock signal of a first clock domain. A data output module receives the data from the data holding module and selectively outputs the data based on a load signal and a second clock signal of a second clock domain which is asynchronous to the first clock domain. A synchronization process module generates the load signal based on a state of the data output module.

Abstract: A remote control support system provides a simple way to allow remote users to access a computer in a variety of circumstances, even when no software installed on the computer. In some cases, the system includes a hardware device to simulate most USB mice, keyboards, storage devices, camera sensors (to capture a screen display), etc. The hardware device can communicate with a remote computer (via a network connection) to allow a user, such as a remote technician, to work on the remote computer as through the user were sitting at the remote computer. Information technology professionals and other users can use the described systems to communicate with a user at a remote computer in a natural way to communicate via voice, video or chat with online messaging.

Abstract: A method and system to improve the operations of an integrated non-transparent bridge device (NTB) that is coupled to another NTB device or Root Port device. The integrated NTB device has logic to maintain ordering of interrupts to be sent to the remote Root Port or NTB device. The integrated NTB device allocates a contiguous portion of the memory for both the primary Base Address Register 0 associated with the integrated NTB device and the secondary BAR0 associated with the remote NTB device. The integrated NTB device has logic to report the size of the primary BAR0 as the combined size of the primary BAR0 and the size of the secondary BAR0. The integrated NTB device facilitates the dynamic modification of a mapping of each bit of a doorbell register with a respective one of a plurality of interrupt vectors based on a mapping register.

Abstract: An apparatus (such as a printer) including a combination engine controller circuit board having a integrated circuit (IC) chip configured to process (format) incoming data as well as to control the operations of the apparatus is disclosed. The IC chip is adapted to receive and process data as well as to control the operations of the apparatus. For this reason, the IC chip is referred to as a combined controller IC.

Abstract: In one embodiment, the present invention includes a switch device to be coupled between a first semiconductor component and a processor node by interconnects of a communication protocol that provides for cache coherent transactions and non-cache coherent transactions. The switch device includes logic to handle cache coherent transactions from the first semiconductor component to the processor node, while the first semiconductor component does not include such logic. Other embodiments are described and claimed.

Abstract: Embodiments of the invention include a bus bridge that is capable of communicating with more than one MSC device coupled to it. In some embodiments, the bridge includes a processor that translates different routing numbers received from the bus into different addresses and routing numbers for devices connected to the bridge. The bridge masks the fact that multiple MSC devices are coupled to it by reporting to the host that only a single device having multiple LUNs are coupled to the bridge.

Abstract: An integrated circuit bridge device can include a first interface circuit coupled to a buffer circuit and a configurable in response to configuration information to receive command information, address information, and data values on a same multi-bit input/output (I/O) bus. A second interface circuit can be coupled to the buffer circuit and configured to communicate according to a first communication protocol different from that executable by the first interface circuit. In addition, a controller circuit formed in the same substrate as the first and second interface circuits can be configured to enable data transfers between the first interface circuit and the second interface circuits via the buffer circuit.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: A computer system includes compute nodes coupled through a switch to shared or non-shared I/O devices. The switch includes a pool of bridge headers and virtual bridges coupling a root port of a compute node to each of one or more shared or non-shared I/O devices. The switch is configured to associate each of the virtual bridges with a respective one of the fixed pool of bridge headers, receive a packet including data identifying the root port and a shared or non-shared I/O device, and route the packet in response to comparing data in the packet to data in the bridge headers associated with the virtual bridges. The virtual bridges comprise a hierarchy of virtual bridges in which one virtual bridge connects the root port to the remaining virtual bridges of the hierarchy. The switch may change the associations between virtual bridges and bridge headers.

Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Abstract: A storage subsystem and a storage controller adapted to take advantage of high data transfer rates of fiber channels while offering enhanced reliability and availability and capable of connecting with a plurality of host computers having multiple different interfaces. A loop is provided to serve as a common loop channel having fiber channel interfaces. Host interface controllers (HIFC) connected to host computers having different interfaces permit conversion between the fiber channel interface and a different interface as needed. Control processors, shared by the host interface controllers, each reference FCAL (fiber channel arbitrated loop) management information to capture a frame having an address of the processor in question from among the frames passing through the loop. I/O processing is then carried out by the controller in accordance with a range of logical unit numbers (LUN) set in the captured frame.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: The invention relates to a data transmission device for transmitting data between a first bus system and a second bus system with a copy table (103) for providing an output sequence of data of the first bus system and a transmission device (101) for transmitting data between the first bus system and the second bus system according to the output sequence.

Abstract: Methods and apparatus are provided for simultaneously supporting multiple hosts with a single communication port; each host may host multiple functions. The input/output device comprises multiple buffers; each buffer stores packets for one host, but can be dynamically reallocated to a different host. Multiple buffers may simultaneously support the same host and all of its functions. After a packet is received and classified, it is distributed to buffer ingress managers. Within a set of ingress managers serving one buffer, each manager corresponds to one function of the buffer's corresponding host, and is programmed with criteria for identifying packets desired by that function. One copy of the packet is stored in a buffer if at least one of the buffer's ingress managers accepts it, along with control information for processing the packet upon egress from the buffer. Egress managers for each buffer extract packets and transfer them to destination host/functions.

Abstract: Circuits, methods, and apparatus that provide transactions to wake an external device from a low-power state before a data transfer. This prevents an interruption that would be caused if the external device exited the low-power state during the data transfer. One example monitors a need for data by a first device. At a predetermined time before data is needed, the first device sends a transaction to a second device. The transaction is intended to wake the second device from a low-power state. If the first device has information to indicate that the second device is not in a low-power state, this transaction can be skipped. The first device then requests data. Later transactions to the second device do not result in the second device exiting the low-power state and therefore do not interrupt or cause delays in the data transfer.

Abstract: A signal processing board including a resource board substrate, an external interface on the board substrate, adapted to receive signals for processing, at least one slot adapted to receive a plug-in module with at least one processor thereon and an interface unit adapted to at least participate in converting signals exchanged between the external interface and a processor on a module received by the slot, between a format of signals received by the external interface and a signal format of the processor. The interface unit is suitable to at least participate in the conversion for a plurality of types of processors that differ in the format in which they transmit or receive signals.

Abstract: A method for dynamically determining bit configuration for a host bridge. The method first obtains information of peripheral components coupled to the host bridge. Next, the method dynamically determines a bit configuration of a processor system bus connecting to the host bridge according to the obtained information.

Abstract: Device connection routing for controllers is provided. A computing device is configured with multiple controllers that provide connections for peripheral devices. The controllers enable the peripheral devices to interact with the computing device through a bus. Each device connection is routed to one of the multiple controllers based on one or more pre-determined factors. These factors may include load-balancing, power saving, quality of service, data flow requirements, and the like. Device connection routing may be dynamically managed to respond to changing states of the peripheral devices and the controllers. The device connection routing may be performed for controllers associated with any type of wired or wireless buses, such as Universal Serial Bus (USB), IEEE 1394, Secure Digital Input/Output (SDIO), and the like.

Abstract: ASCII gateway to in-vehicle system provides bi-directional translation between multiplexed motor vehicle networks and industrial control and monitoring devices. Integrated hardware and software components provide data communications between motor vehicle electronic control module networks and RS-232 serial ASCII-text capable device, for industrial control and/or industrial automation application in manufacturing or assembly operations. Communications networks (CAN, SAE or ISO protocols) implemented inside motor vehicles pass data between electronic control modules that control operation of important vehicle components like engine, transmission and brake systems, have their messages converted to RS-232 serial ASCII-text; and from RS-232 serial ASCII-text converted to motor vehicle communications network by the system. Messages to monitor and/or control vehicle networks are generated by a serial ASCII-test capable device. Multiple vehicle protocols are supported by the system.

Abstract: A method of bridging a plurality of buses within a bus bridge can include determining whether a queue of the bus bridge includes a transaction request directed to a restricted address range and, for each received transaction request, determining whether an address to which the transaction request is directed is within the restricted address range. Each transaction request received by the bus bridge can be selectively rejected according to whether the address to which the transaction request is directed is within the restricted address range and whether the queue includes a transaction request directed to the restricted address range.

Abstract: A server having remote peripheral device access functions for accessing different types of peripheral devices located on a remote host, such as USB, SATA and IDE devices. The remote device access function is implemented in the IPMI section of the server. The IPMI section is connected to a bridge of the server, and communicates with the bridge using a single predetermined communication protocol, such as the PCI protocol, regardless of the type of the peripheral devices being remotely accessed. An application on the remote host communicates with the IPMI section of the server to transmit the data generate by or to be consumed by the peripheral device using a predetermined network protocol.

Abstract: A communications module apparatus for an automotive network comprises an input for receiving data to be transmitted. The apparatus also comprises a first output for coupling to a first bus line and a second output for coupling to a second bus line. An alternating voltage signal transmission circuit for transmitting at least part of the received data is also provided. The alternating voltage signal transmission circuit is coupled to the first output and the second output.

Abstract: A register access request for control and/or status operations from a link is detected using a hardware mechanism and is forwarded to a software-controlled entity for access to a virtual register for control and/or status operations. The software-controlled entity can provide virtual registers in memory associated with the software-controlled entity. The hardware mechanism can form part of an interconnect device and the software-controlled entity is external to the interconnect device.

Abstract: A data processing apparatus and method are provided for performing hazard detection in a series of access requests issued by processing circuitry for handling by one or more slaves. The requests include one or more write access requests to be performec by an addressed slave device. Hazard detection circuitry comprises a pending write access history storage having at least one buffer and at least one counter for keeping a record of each pending write access request. Update circuitry responds receipt of a write access request to perform an update process to identify that write access request as a pending write access request in one of the buffers, and if the identity of another pending write access request is overwritten by that update process, to increment a count value a counter.

Abstract: Methods and apparatus are provided for improving communication between processors in separate computer systems. Components and peripherals in individual computer systems communicate using input/output (I/O) buses such as PCI Express buses. The I/O buses are extended to allow interconnection between computer systems without having to introduce network infrastructure. A transfer controller supporting Direct Memory Access (DMA) is provided to allow even more efficient communication between computer systems.

Abstract: A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus.

Abstract: Described are electronics systems and methods for distributing a limited number of lanes of a PCI Express-based processor (CPU) module among a plurality of PCI Express-based I/O modules with which the CPU module is in communication. The CPU module receives a code from each I/O module over a sideband interface between that I/O module and the CPU module. The coded signal represents a link-width capability of the I/O module. The CPU module is configured to allocate a link width to each I/O module based on the fixed number of lanes and the link-width capability as represented by the coded signal received from that I/O module. The link between CPU module and each I/O module is trained in accordance with the link width allocated to that I/O module.

Abstract: Embodiments are described for executing embedded functions in endpoint devices by proxy in a shared PCI Express subsystem. The shared subsystem comprises a plurality of proxy devices coupled to a PCIe fabric, wherein each one of the proxy devices is associated with an endpoint device and coupled to a controlling server through a PCIe link. An associated proxy device comprises a copy of the configuration space of the target endpoint device. Embedded functions of an endpoint device can be accessed by controlling servers through the associated proxy devices. Devices in the shared subsystem use PCI protocol to communicate. The duplication of the endpoint configuration space in the proxy device is administrated by a proxy configuration manager. The proxy device translates destination addresses in upstream and downstream transactions. A proxy interrupt conveyance mechanism relays interrupt messages from an endpoint device to the controlling server via the associated proxy device.

Abstract: In one embodiment, the present invention includes a switch device to be coupled between a first semiconductor component and a processor node by interconnects of a communication protocol that provides for cache coherent transactions and non-cache coherent transactions. The switch device includes logic to handle cache coherent transactions from the first semiconductor component to the processor node, while the first semiconductor component does not include such logic. Other embodiments are described and claimed.

Abstract: A communications arrangement is implemented for packet data communications control. According to an example embodiment of the present invention, a communications arrangement (100), such as a PCI Express type arrangement, carries out separate arbitration functions (112, 116, 117, 118) for ordering packet data. One of the arbitration functions (112) orders the packet data in accordance with protocol standards (e.g., to meet PCI Express standards when implemented with a PCI Express system). The other arbitration function (116, 117, 118) orders the packet data in accordance with performance standards while maintaining compliance with the protocol standards.

Abstract: A PCI Express switch which connects a plurality of peripheral devices to an arbitrary one of a plurality of CPUs through an Ethernet is constituted by a plurality of upstream and downstream PCI Express-network bridges, an Ethernet switch, and a system manager. Each of the upstream and downstream PCI Express-network bridges includes a PCI Express adapter which terminates a link of a PCI Express bus, a network adapter which terminates a link to the Ethernet switch, and a control unit which encapsulates a TLP in a frame, the destination of which is a MAC address of a bridge to which the destination is connected to transmit and receive the frame. Because the switch according to the present invention comprising a plurality of upstream PCI Express-network bridges and a plurality of downstream PCI Express-network bridges connected to the plurality of upstream PCI Express network bridges through a network is equivalent to a conventional PCI Express switch, it is needless to change a conventional PCI software.

Abstract: Provided is a data transfer apparatus having a system bus interface 20 connected to an MC 51, a high-speed I/O bus interface connected to a high-speed I/O bus switch 54, a history selection controller 10 that selects part of transmission/reception data transferred between the MC 51 and high-speed I/O bus switch 54, a buffer section 11 that is connected to the history selection controller 10 and retains the part of the transmission/reception data selected by the history selection controller 10, and a low-speed bus interface that outputs the part of the transmission/reception data retained by the buffer section 11 to an observation apparatus 200.

Abstract: Routing between multiple hosts and adapters in a PCI environment is provided by a method and system. A Destination Identification (DID) field is inserted in a field of the PCI bus address (PBA) of transaction packets dispatched through PCI switches. A particular DID is associated with a particular host or system image, and thus identifies the physical or virtual end point of the packets. The method and system may track connections such that when particular host of a root node becomes connected to a specified switch, a PCI Configuration Master (PCM), residing in one of the root nodes, is operated to enter a destination identifier or DID into a table. The DID is then inserted in the PBA of packets directed through the specified switch from the particular host to one of the adapters.

Abstract: Embodiments of the present invention include a switch component, incorporated within a computer system, that receives switch commands from users and that controls internal switches to direct output to, and receive input from, either components of the computer system or one or more external-access ports. The switch component allows one or more external computers to access internal components of, or external peripherals attached to, a computer system that includes the switch component.

Abstract: A connection device for selecting an optimum receiver includes a single first port, in which a transmitter is connected via a bidirectional type cable, and a plurality of second ports, in which a plurality of receivers are connected via respective bidirectional type cables. The connection device further includes a transmission control unit which acquires transmitter function information from the transmitter via the first port as well as acquiring receiver function information from each of the plurality of receivers via their respective second ports. A transmission control unit links together the first port and the respective second port from among the plurality of second ports, which is connected to the receiver which is endowed with receiver function information closest to the transmitter function information.