Abstract: Disclosed are various embodiments of a Consumer Electronics Control (CEC) bridge. In one embodiment, a CEC bridge includes an HDMI interface, a network interface, a processor, and code executable by the processor. The code includes logic that emulates a CEC command directed to any of a cluster of remote HDMI devices, wherein none of the remote HDMI devices are coupled to the device through the HDMI interface.

Abstract: A USB key device and method for realizing the intelligent card communication using the USB interface are provided.

Abstract: A method and system for providing multi-process protection using direct memory mapped control registers is disclosed. According to one embodiment, a computer-implemented method provides a set of control registers for each execution unit of a plurality of execution units in a controller switch. The controller switch facilitates communication between a host system and one or more devices connected to a plurality of device ports of the controller switch. A device driver is provided to allow users' processes to access the controller switch and to grant exclusive access to each execution unit of the plurality of execution units. A first access request to access an execution unit of the plurality of execution units is received from a first process. A set of direct accessible addresses to the set of control registers of the execution unit is allocated, and the first process is granted to exclusive access the execution unit until the first process release the exclusive access to the execution unit.

Abstract: Methods, apparatuses, and computer program products for accessing a logic device through a serial interface are provided. Embodiments include receiving, by the serial interface of the logic device, a first data access request indicating a non-linear address mode, wherein the first data access request includes: a non-linear address corresponding to a non-linear index specifying a plurality of non-linear addresses, the non-linear index associating each non-linear address with one of the plurality of registers; a data count indicating an amount of data to be accessed in the first data access request; and a page offset value indicating within a register, a starting page to perform the first data access request. Embodiments also include identifying in the non-linear address mode a location within the logic device based on the non-linear address and the starting page; and performing at the identified location, by the logic device, a serial transaction in accordance with the first data access request.

Abstract: Memory apparatuses that may be used for receiving commands and ordering memory responses are provided. One such memory apparatus includes response logic that is coupled to a plurality of memory units by a plurality of channels and may be configured to receiving a plurality of memory responses from the plurality of memory units. Ordering logic may be coupled to the response logic and be configured to cause the plurality of memory responses in the response logic to be provided in an order based, at least in part, on a system protocol. For example, the ordering logic may enforce bus protocol rules on the plurality of memory responses stored in the response logic to ensure that responses are provided from the memory apparatus in a correct order.

Abstract: CPUs that generate PCIe auxiliary signals and changing clock signals nevertheless communicate with each other using PCIe owing to PCIe switch assemblies that are disposed in the communication paths to isolate and terminate the auxiliary signals from reaching other CPUs and to isolate changing clock signals, communicating with each other using a fixed clock derived from one of the changing clock signals. Also, the CPUs directly access the memories of CPUs to which they wish to write data so that data is directly written from one CPU memory to another without store-and-forward operations being needed in the network.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: Systems and methods to perform a register access are described. A particular method includes receiving a data frame at a bridge element of a plurality of bridge elements in communication with a plurality of server computers. The data frame may include a register access request and may be forwarded from a controlling bridge in communication with the plurality of bridge elements. A register may be accessed and execution of the register access request may be initiated in response to receiving the data frame.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: Embodiments include methods, apparatus, and systems for converting resets in a shared I/O system. One embodiment includes a method that propagates a first type of reset from a host computer to a multi-function device that shares I/O operations with other hosts. The first type of reset is converted to a second type of reset to prevent the host from resetting functions bound to the other hosts at the multi-function device.

Abstract: A network system that is part of a main system includes: a first PCI express-network bridge with a first control unit and a first PCI express adapter terminating a first PCI express bus; and a second PCI express-network bridge connected to the first PCI express-network bridge through a network. The second PCI express-network bridge includes a second control unit and a second PCI express adapter terminating a second PCI express bus, wherein the first control unit detects a destination of a packet sent from the first PCI express adapter, searches a physical address of the destination from a packet encapsulating table, and encapsulates the packet in a frame so that the frame includes the physical address, and wherein the second control unit removes the encapsulation tagged to the packet, and transfers the packet to the destination through the second PCI express bus by referring to a PCI express configuration register.

Abstract: A storage assembly includes a physical expander for connection in use to two or more SCSI initiators, and two or more storage devices, wherein the expander is controlled such that it presents plural virtual expanders. A method for connecting two or more storage devices to two or more SCSI initiators within a storage assembly, includes providing a physical expander for connection in use to the two or more SCSI initiators, and two or more storage devices, and controlling the single expander such that it presents plural virtual expanders.

Abstract: A storage system including: a storage apparatus including a plurality of storage devices on which a plurality of logical units is configured and a first controller that controls accesses to the plurality of logical units; and a file server coupled to said storage apparatus and including a second controller and a memory storing management information which indicates relationships between each of the plurality of logical units and each of a plurality of indicators; wherein the first controller, in response to a request to create a first folder with a first indicator, creates the folder on one or more first logical units included in the plurality of logical units, the one or more first logical units related to the first indicator.

Abstract: Systems and methods of routing data units such as data packets or data frames that provide improved system performance and more efficient use of system resources. The disclosed systems and methods employ memory mapping approaches in conjunction with transaction ID tag fields from the respective data units to assign each tag value, or at least one range of tag values, to a specified address, or at least one range of specified addresses, for locations in internal memory that store corresponding transaction parameters. The disclosed systems and methods can also apply selected bits from the transaction ID tag fields to selector inputs of one or more multiplexor components for selecting corresponding transaction parameters at data inputs to the multiplexor components. The disclosed systems and methods may be employed in memory-read data transfer transactions to recover the transaction parameters necessary to determine destination addresses for memory locations where the memory-read data are to be transmitted.

Abstract: Systems and methods to remotely configure adapters are described. A particular method may include generating a management frame at a controlling bridge. The management frame may include instructions to configure an operating parameter of the adapter. The management frame may be communicated to a bridge element of a plurality of interconnected bridge elements in communication with the controlling bridge. The bridge element may be coupled to the adapter, and the operating parameter of the adapter may be configured.

Abstract: A data storage apparatus having improved data transfer performance. The storage apparatus has: plural controllers connected to each other by first data transfer paths; plural processors controlling the controllers; and second data transfer paths through which the controllers send data to various devices. Each of the controllers has a data-processing portion for transferring data to the first and second data transfer paths. The data-processing portion has a header detection portion for detecting first header information constituting data, a selection portion for selecting data sets having continuous addresses of transfer destination and using the same data transfer path from plural data sets such that a coupled data set is created from the selected data sets, a header creation portion for creating second header information about the coupled data set, and coupled data creation means for creating the coupled data set from the selected data sets and from the second header information.

Abstract: A packet communication device autonomously selects an appropriate operation mode according to a connection environment to an external device before a service of the device is started. When the device is connected to the external buses, connection interface units notify an external device discrimination unit of connection of the device. The external device discrimination unit issues a polling packet to the connected device, discriminates the connected external device on the basis of the response packet, and notifies an operation mode switching unit. The operation mode switching unit selects an operation mode conforming to a connection environment of the packet communication device to the external device and switches the operation mode of the device to the mode.

Abstract: Embodiments are generally directed to a method and apparatus to couple a module to a management controller on an interconnect. In one embodiment, a method includes detecting that a module has coupled to an interconnect, the interconnect coupled to a modular platform backplane. The method further includes logically coupling the module to one of a plurality of management controllers resident on the interconnect, each management controller logically appears as a management controller for different interconnects coupled to the modular platform backplane.

Abstract: In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value.

Abstract: Methods and apparatuses that utilize a serial bus, such as a universal serial bus (USB), for communications between a communications network, a computing device, and an auxiliary device are disclosed. Some embodiments comprise methods handling sideband communications using serial buses. One or more of the embodiments comprise differentiating in-band data from out-of-band data, transferring information of the in-band data between a communications network and a computing device, and transferring information of the out-of-band data between the communications network and an auxiliary device. Some embodiments comprise an apparatus having a communications network interface, an auxiliary device interface, and a computing device interface. Of the interfaces, one or more may be a serial bus interface. The apparatus may differentiate between in-band and out-of-band data and communicate information of the out-of-band data to an auxiliary device. In some embodiments, the apparatus may also transfer control information.

Abstract: A USB device includes: a communication section that is capable of wirelessly communicating with a communication device that supports a predetermined communication standard; a USB communication section that is capable of communicating with a USB host device; and a connection section that, when a connection to the communication device is requested under the condition that a connection to the USB host device is requested, determines whether or not a protocol supported by the communication device is any of multiple protocols, and establishes the connection to the USB host device through the USB communication section using a device class corresponding to the determined protocol.

Abstract: A method for identifying noise sources for automation devices (1, 2) which have a multiplicity of input/output modules (2a, 2b, . . .

Abstract: In an embodiment a translation of RID (requester identifier) ranges to identifiers of north chips is stored into a south chip. A command that comprises a command RID is received at the south chip from a device. In response, a RID range is determined that encompasses the command RID, and a north chip identifier is found that is assigned a virtual function identified by the command RID. The command is sent from the south chip to the north chip identified by the north chip identifier. The translation comprises a RID compare value and a RID mask. A determination is made that the RID range encompasses the command RID by performing a logical-and operation on the command RID and the RID mask and comparing a result of the logical-and operation to the RID compare value.

Abstract: In one embodiment, a technique for routing traffic in networks represented by logical topologies, such as Multi Chassis Port Channel (MCPC) or Multi Chassis Ether Channel (MCEC) topologies, is provided. By modifying a port priority vector (PPV) to include an additional “Switch ID” field that identifies a designated bridge ID or a local switch ID, depending on whether the corresponding port is used as an MCT, a routing protocol designed to avoid loops in routing paths, such as STP, may avoid blocking MCT ports.

Abstract: Programming of modules which can be reprogrammed during operation is described. Partitioning of code sequences is also described.

Abstract: A bridge includes a host interface via which data/commands are received from and transferred to a host, and a storage device interface via which data/commands are received from and transferred to a storage device. The bridge also includes one SDPC, a controller and a switching system that is configurable by the controller to connect the protocol converter to the host interface and the storage device interface if the storage device protocol used by the host device differs from the storage device protocol used by the storage device, and to connect the host device interface to the storage device interface, not via the bi-directional protocol converter, if the two storage device protocols are the same. The bridge may include two SDPCs, each for converting a different protocol to the host protocol and vice versa, with the switching system being configurable to switch between the two SDPCs.

Abstract: A computer motherboard includes first and second peripheral interfaces, a switching interface, a switching card inserted into the switching card, and first and second central processing unit (CPU) sockets. The switching interface is placed between the first and second peripheral interfaces. The switching card includes first and second interface. Pins of the first interface of the switching card are interconnected, and pins of the second interface of the switching card are interconnected. Connection between the first and second peripheral sockets and the first and second CPU sockets is adjustable by selectively connecting one of the first and second interfaces of the switching card to the switching interface.

Abstract: An apparatus and a method for setting a primary port on a PCI multi-port bridge. More specifically, there is provided a method that comprises detecting a configuration signal at the PCI multi-port bridge and automatically setting the primary port on the PCI multi-port bridge based on the configuration signal. A system for implementing the method is also provided.

Abstract: Degradation of data transfer performance is restrained during data transfer for mirroring between first and second controllers. The first and second controllers are connected with a first path for connecting a second port of a first switch unit on the first controller to a second port of a first switch unit on the second controller, and with a second path independent of the first path, for connecting a second port of a second switch unit on the first controller to a second port of a second switch unit on the second controller.

Abstract: In an embodiment, a command is received that requests movement of ownership of a target device from an origin compute element to a destination compute element. From the origin compute element, a translation of a virtual bridge identifier to a first secondary bus identifier, a first subordinate bus identifier, and a first MMIO bus address range is removed. To the destination compute element, a translation of the target virtual bridge identifier to a second secondary bus identifier, a second subordinate bus identifier, and a second MMIO bus address range is added. From a south chip that comprises the target virtual bridge, a translation of the target virtual bridge identifier to an identifier of the origin compute element is removed. To the south chip, a translation of the target virtual bridge identifier to an identifier of the destination compute element is added.

Abstract: Methods and apparatus are provided for simultaneously supporting multiple hosts with a single communication port; each host may host multiple functions. The input/output device comprises multiple buffers; each buffer stores packets for one host, but can be dynamically reallocated to a different host. Multiple buffers may simultaneously support the same host and all of its functions. After a packet is received and classified, it is distributed to buffer ingress managers. Within a set of ingress managers serving one buffer, each manager corresponds to one function of the buffer's corresponding host, and is programmed with criteria for identifying packets desired by that function. One copy of the packet is stored in a buffer if at least one of the buffer's ingress managers accepts it, along with control information for processing the packet upon egress from the buffer. Egress managers for each buffer extract packets and transfer them to destination host/functions.

Abstract: An integrated circuit device may include a mask register that stores mask values writable from a processor interface; and mask logic that selectively masks status indications from each of a plurality of buffers according to stored mask values; wherein the buffers alter the status indications in response to accesses from at least one different interface other than the processor interface.

Abstract: Device connection routing for controllers is provided. A computing device is configured with multiple controllers that provide connections for peripheral devices. The controllers enable the peripheral devices to interact with the computing device through a bus. Each device connection is routed to one of the multiple controllers based on one or more pre-determined factors. These factors may include load-balancing, power saving, quality of service, data flow requirements, and the like. Device connection routing may be dynamically managed to respond to changing states of the peripheral devices and the controllers. The device connection routing may be performed for controllers associated with any type of wired or wireless buses, such as Universal Serial Bus (USB), IEEE 1394, Secure Digital Input/Output (SDIO), and the like.

Abstract: Embodiments of the present invention provide a unique capability of implementing a pair of pseudo-PHY interfaces using a bridge. From the host and device perspectives, the host and device communicate through a PHY interface. The bridge, however, avoids actually using a USB PHY interface. This PHY-less bridge allows communication between a host and a device at high speeds without high-power transceivers associated with a USB PHY interface. In accordance with the present invention, a host and a device may be coupled together using a PHY-less bridge using the same interface or translating between different interfaces by using a wrapper. Such PHY-less bridges include a UTMI-to-UTMI bridge, a UTMI-to-ULPI bridge, a ULPI-to-UTMI bridge and a ULPI-to-ULPI bridge, each avoiding the need for a USB PHY interface.

Abstract: An apparatus includes a PHY assembly in electrical communication with a first interface assembly and with a second interface assembly, the PHY assembly configured to receive a power signal from a PSE, the PHY assembly having a first PHY and a second PHY. The first PHY is configured to receive a first data signal from the PSE through the first interface assembly via the frame-based computer networking connection and provide the first data signal to the second PHY for transmission to a network device through the second interface assembly via the frame-based computer networking connection. The second PHY is configured to receive a second data signal from the network device through the second interface assembly via the frame-based computer networking connection and provide the second data signal to the first PHY for transmission to the PSE through the first interface assembly via the frame-based computer networking connection.

Abstract: A system to operationally connect logic nodes may include an inter-nodal circuit to provide communications between any connected logic nodes. The system may also include a fabric bus that may be physically separate from the inter-nodal circuit, the fabric bus may provide logical connections restricted to any two connected logic nodes. The system may further include a clock circuit carried by the inter-nodal circuit that controls both the inter-nodal circuit and the fabric bus.

Abstract: A system to mate logic nodes may include a connector to secure at least one of an inter-nodal circuit and a fabric bus, where the inter-nodal circuit provides communications between any connected logic nodes, and the fabric bus provides logical connections to a first logic node and any other logic node. The system may also include an element carried by the connector configured to provide an appropriate actuation force to mate the connector and at least one of the inter-nodal circuit and the fabric bus.

Abstract: A shared system to operationally connect logic nodes may include an inter-nodal circuit to provide communications between any connected logic nodes. The system may also include a fabric bus carried by the inter-nodal circuit, the fabric bus to provide logical connections to a first logic node and any other logic node. The system may further include a clock circuit carried by the inter-nodal circuit that controls both the inter-nodal circuit and the fabric bus.

Abstract: A system-on-a-chip (SOC) bridge is described that applies an adapted delay, or latency, to data transfers across the bridge to avoid data corruption without reducing data transfer performance. The adapted delay assures that a source SOC service device transferring data to a destination SOC service device via the bridge and an SOC crossbar bus does not prematurely assume that the data transfer is complete upon transferring the data to the bridge. The bridge causes wait states to be inserted into the transfer between the source SOC service device and the SOC bridge until the SOC bridge receives confirmation that the data has arrived at the destination SOC service device. The adapted delay assures that subsequent operations are not prematurely initiated by the source SOC service device and/or the SOC CPU that may interfere with the data transfer from the SOC bridge to the destination SOC service device, resulting in corrupted data.

Abstract: A first SAS expander including at least phys is operably coupled to a first and a second SAS wide port. A second SAS expander including at least two phys is operably coupled to the first and the second SAS wide port. The first and the second SAS wide port each include at least two lanes, one of each at least two lanes designateable as a connection request lane. The connection request lane of each SAS wide port is operably coupled to a different SAS expander.

Abstract: A relay device includes: an input buffer for receiving data units, each of which includes a header, to which multiple pieces of destination information have been added, and data associated with the header; multiple virtual channels for storing data units, each of the multiple virtual channels storing a data unit in accordance with the destination information; a destination comparing section for determining the order of allocation of virtual channels at a relay device on the receiving end with respect to the data units that are stored on the multiple virtual channels by seeing if their destinations are the same; and an output section for outputting the stored data units preferentially through one of the virtual channels that has already allocated at the relay device on the receiving end.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: Communications adapters and methods are provided for interfacing communications for an EtherNet/Ip or other general purpose industrial network, a Fieldbus or other open protocol device network, and a PointBus or other proprietary network. The adapter may be integrated in a module of a backplane system with connections to the general purpose, proprietary, and open protocol device networks, and provides a bridging for communications across the networks to make devices on the proprietary and open protocol networks accessible as if they were on a single device network and with sequential addressing capabilities.

Abstract: An apparatus that controls access by multiple IP cores to a bus is provided. The apparatus includes a main controller and multiple sub controllers, each of the sub controllers being associated with each IP cores. The main controller switches connection between each of the IP cores and the bus according to a schedule predetermined based on predetermined time slices. Each of the sub controllers controls access by the IP core to the bus according to a schedule under the control of the main controller. Embodiments of the present invention provide method and apparatus to ensure real-time accessibility to a bus shared by multiple IP cores and improve bus use efficiency.

Abstract: A method for performing write transactions in an interconnect fabric is described. A burst write transaction is received by a bridge coupled to a master. The burst transaction is initiated by a command phase that includes a wait state attribute. The bridge is also coupled to a second bus that is coupled to a slave destination device or to another bridge. The bridge may initiate a cut-through transaction to the second bus when the wait state attribute indicates a master inserted wait state will not be incurred during the burst transaction.

Abstract: In one embodiment, link logic of a multi-chip processor (MCP) formed using multiple processors may interface with a first point-to-point (PtP) link coupled between the MCP and an off-package agent and another PtP link coupled between first and second processors of the MCP, where the on-package PtP link operates at a greater bandwidth than the first PtP link. Other embodiments are described and claimed.

Abstract: A cellular telephone using a memory array that is directly addressed and non-volatile is disclosed. The memory array can be used to replace and emulate multiple memory types such as DRAM, SRAM, non-volatile RAM, FLASH memory, and a non-volatile memory card, for example. The memory array may be randomly accessed. Data stored in the memory array is retained in the absence of electrical power. One or more memory arrays may be used in the cellular telephone. At least one of the memory arrays may be in the form of a removable memory card.

Abstract: A computer system has a central processing unit, a north bridge electrically connected to the central processing unit, memory electrically connected to the north bridge, a south bridge electrically connected to the north bridge, and a peripheral device electrically connected to the south bridge. The south bridge includes a register for storings a plurality of pre-fetched read data to provide the pre-fetched read data to the peripheral device. The north bridge has an address queue module for storing an address of the pre-fetched read data, and a snooping module for checking whether a data value corresponding to the address is updated by the CPU. The north bridge assists the south bridge in obtaining and maintaining the pre-fetched read data for high efficiency and accuracy of read caching of the south bridge.

Abstract: A data transmission system forming a network including transmission line sections comprising traditional infrastructure such as AC power line (mains), twisted-pair (e.g. CAT-5) and coaxial cable wiring interconnected with a novel adapter to form a data system also providing data transfer over an extended length and diversity of connected equipment. Further combined with a data bridge connected to conventional format data (e.g. Ethernet) and to the traditional data infrastructure wiring, the novel adapter permits connection to any 2 of twisted pair/multi-pair, coaxial and power mains for data flow therebetween.