Abstract: A bridging module, a data transmission system, and a data transmission method are provided. The bridging module obtains a first read request, and allocates a first location storage space for first return data corresponding to the first read request. The bridging module combines a first master transaction identifier and an address of the first location storage space as a first slave transaction identifier of the first read request, and sends the first read request to a slave device. The bridging module obtains a second read request, and allocates a second location storage space for second return data corresponding to the second read request. The bridging module combines a second master transaction identifier and an address of the second location storage space as a second slave transaction identifier of the second read request, and sends the second read request to the slave device.

Abstract: Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

Abstract: Disclosed is an Avalon-to-Axi4 bus conversion method, including: in case that an Avalon bus is an Avalon_st bus, receiving Avalon_st bus data, performing a logical process on the received Avalon_st bus data, and then outputting corresponding Axi4_st bus data; and in case that the Avalon bus is an Avalon_mm bus, receiving a signal transmitted by each channel of the Avalon_mm bus, framing and storing the signal in asynchronous First Input First Output (FIFO), and in case that a device corresponding to an Axi4 bus is ready, reading the signal from the asynchronous FIFO, and outputting the signal to a corresponding channel of the Axi4 bus according to a timing relationship of the Axi4 bus.

Abstract: An address decoder for a source node in a multi-chip system is disclosed, which can perform parallel decoding steps to determine whether a transaction from the source node is addressed to a target node in a local integrated circuit (IC) or a remote IC, and whether the source node is allowed to access that target node. Based on the outcome of both the decoding steps, the transaction can be either blocked by the address decoder, or routed to the target node. If the transaction is addressed to the remote IC, but the source node is not allowed to access the target node on the remote IC, the transaction can be terminated by the address decoder in the local IC.

Abstract: A memory card access module and a memory card access method are provided. The memory card access method is applied to an electronic device. A processing unit of the electronic device accesses a memory card through a memory card slot. The method includes steps of: detecting whether the memory card supports a Peripheral Component Interconnect Express (PCIe) interface; when the memory card does not support the PCIe interface, controlling the processing unit to access the memory card through a data transmission path and performing data format conversion between a transmission interface and the PCIe interface using a memory card access unit disposed on the data transmission path; and when the memory card supports the PCIe interface, controlling the processing unit to access the memory card through a PCIe data transmission path that allows the processing unit and the memory card to transmit data through the PCIe interface.

Abstract: A configurable multi-function Peripheral Component Interchange Express (PCIe) endpoint controller, integrated in a system-on-chip (SoC), that exposes multiple functions of multiple processing subsystems (e.g., peripherals) to a host. The SoC may include a centralized transaction tunneling unit and a multi-function interrupt manager. The processing subsystems output data to the host via the centralized transaction tunneling unit, which translates addresses provided by the host to a local address of the SoC. Therefore, the centralized transaction tunneling unit enables those processing subsystems to consume addresses provided by the host without the need for software intervention and software-based translation. The SoC may also provide isolation between each function provided by the processing systems. The multi-function interrupt manager enables the endpoint controller to propagate interrupt messages received from the processing subsystems to the host.

Abstract: Systems and methods for interfacing an application circuit to an industrial network include first and second interfaces, one or more controllers, and one or more memory devices. The one or more memory devices store instructions, which when executed, cause the controllers perform operations to convert messages between a specified message format according to a protocol of the industrial network and a protocol agnostic format.

Abstract: Techniques are described for providing consistent memory operations and security across electronic circuitry components having disparate memory and/or security architectures when integrating such disparately architected components within a single system, such as a system on chip. A programmable logical hierarchy of isolated memory region (IMR) enforcement circuits is provided to protect such IMRs, allowing or preventing memory access requests from one of multiple distinct circuitry components based on configuration registers for the IMR enforcement circuits. Integration of multiple trust domain architectures associated with the multiple distinct circuitry components is facilitated via trust domain conversion bridge circuitry that includes translation logic for generating information in accordance with a first trust domain architecture based on information provided in accordance with a distinct second trust domain architecture.

Abstract: Systems and methods are disclosed for processing and executing queries against one or more dataset sources, where the queries identify a set of data to be processed and a manner of processing the set of data. To query the dataset sources, a query coordinator generates a query processing scheme that includes a dynamic allocation of multiple layers of partitions. The query is then executed based on the query processing scheme.

Abstract: A U-I/O card improves on traditional I/O cards by enabling configuration of each I/O channel on each U-I/O card to operate according to a desired signal type (e.g., AI, AO, DI, or DO). Thus, each I/O channel of a given U-I/O card may be coupled to any type of field device. The U-I/O card thus simplifies I/O network design, wiring, configuration, commissioning, redesign, and rewiring. The U-I/O card also improves space efficiency in marshalling cabinets and eliminates inefficient use of I/O cards relative to traditional I/O cards.

Abstract: A dongle for connecting a computerized device to a certified unit under test (UUT) includes a computerized device communication port and a UUT communication port. The dongle also includes a communication module operatively connecting the computerized device communication port and the UUT communication port. The communication module includes an internet protocol (IP) module that supplies an IP address to a computerized device connected to the computerized device communication port, wherein the IP address enables the computerized device to receive signals from and/or send signals to the UUT.

Abstract: Disclosed embodiments relate to securely inspecting and validating remote access protocol communications. Operations may include accessing remote access protocol communications between a first computing resource and a second computing resource; and validating at least a portion of the remote access protocol communications by at least one of: analyzing a sequence among the at least the portion, analyzing data contents of the at least the portion, analyzing a size field in the at least the portion, or analyzing a data-size correlation of the at least the portion; wherein at least one of the following is conditioned on a result of the validation: an ability of the at least the portion of the remote access protocol communications to pass between the first computing resource and the second computing resource, or an establishment of a remote access session between the first computing resource and the second computing resource.

Abstract: The present disclosure relates to a method of monitoring Controller Area Network (CAN) nodes and a monitoring device performing the method. In an aspect a method of a monitoring device of monitoring a plurality of CAN buses is provided, wherein at least one CAN node is connected to each CAN bus, said plurality of CAN buses being interconnected via the monitoring device. The method comprises detecting, for each CAN bus, any dominant data being sent over said each CAN bus by a CAN node connected to said each CAN bus and routing said any dominant data received by the monitoring device over said each CAN bus to all remaining CAN buses without overwriting any dominant data sent over the remaining CAN buses.

Abstract: A single communication interface between a master device and at least one slave device and a method with internal/external addressing mode using the single communication interface. In the single communication interface between a master device and at least one slave device, the master device includes a master interface and the slave device comprises a slave interface and a slave bus-system, whereas the slave interface is directly connected to the slave bus-system, wherein the master interface and the slave interface communicate on a packet based protocol by an internal and external addressing mode inside the slave interface, whereas the addressing mode, data transfer direction and data address location are coded by the packet based protocol inside a first 32-bit word of each transmission between the master device and slave device over the single communication interface.

Abstract: In one embodiment, an electronic device controls an external conversion device connected to an external device. The electronic device includes a connection terminal formed on a portion of an outer surface thereof, a first converter connected to the connection terminal and configured to convert signals, and a processor operatively connected to the first converter. The processor is configured, when the external conversion device is connected to the connection terminal, and the external device is connected to the external conversion device, to identify a type of the external device connected to the external conversion device by receiving an operation signal of the external device through the external conversion device, the connection terminal, and the first converter, and to input or output a signal corresponding to the external device through the external conversion device.

Abstract: A memory card includes a card substrate on which a controller and a memory device are mounted, and a card enclosure that accommodates the card substrate and exposes terminals for electrical connection to an external device. The controller is operable in a universal flash storage (UFS) mode and in a first sub-mode other than the UFS mode. The terminals that are exposed include a UFS terminal group according to a UFS standard, and a first sub-mode terminal group. The UFS terminal group includes first row terminals arranged adjacent to an insertion side edge of the memory card and second row terminals arranged apart from the insertion side edge such that the first row terminals are provided between the second row terminals and the insertion side edge. The first sub-mode terminal group is adjacent to the first row terminals.

Abstract: Various embodiments include systems and methods of operating the systems that include operation of a plurality of first nodes and second nodes in response to a request, where each first node is a first type of processing unit and each second node is a second type of processing unit, where the second type of processing node is different from the first type of processing node. Each of the first and second nodes can be operable in parallel with the other nodes of their respective plurality. Each second node may be operable to respond to the request using data and/or metadata it holds and/or operable in response to data and/or metadata from one or more of the first nodes. Additional apparatus, systems, and methods are disclosed.

Abstract: A cable assembly for providing a data acquisition system with data messages passing on a fieldbus of rolling stock, said cable assembly comprising a data listener adapted to listen in on said data messages passing on said fieldbus; a data transmitter adapted to transmit said data messages to said data acquisition system; and an isolation module adapted to electrically isolate said data transmitter from said data listener and from said fieldbus, thereby electrically isolating said data acquisition system from said fieldbus such that said data acquisition system is limited by said isolation module to only listening in on said data messages passing on said fieldbus.

Abstract: An industrial control system, such as a process control for use in a process plant, uses a hardware/software architecture that makes the system more reactive by making the system more resilient, responsive, and elastic. The industrial control system includes one or more distributed input/output (I/O) controller devices (BFN I/O controllers) which are coupled to field devices within a plant and provide direct or indirect access to the field devices for control and messaging purposes, one or more advanced function and computation nodes, and one or more user nodes coupled to the BFN I/O controllers via a network connection. The advanced function nodes store and execute virtual machines, devices, or entities, which decouples the hardware used in the control system from the software that functions on that hardware, making the system easier to scale, reconfigure, and change.

Abstract: A streaming engine employed in a digital data processor specifies fixed first and second read only data streams. Corresponding stream address generator produces address of data elements of the two streams. Corresponding steam head registers stores data elements next to be supplied to functional units for use as operands. The two streams share two memory ports. A toggling preference of stream to port ensures fair allocation. The arbiters permit one stream to borrow the other's interface when the other interface is idle. Thus one stream may issue two memory requests, one from each memory port, if the other stream is idle. This spreads the bandwidth demand for each stream across both interfaces, ensuring neither interface becomes a bottleneck.

Abstract: A system for enabling secure bidirectional communications on a network is provided, wherein a first server having a first security rating is connected to a second server having a second security rating by a first data channel configured to establish one-way communication from the first server to the second server. A second data channel incorporating a third server is configured to establish one-way communication from the second server back to the first server. The third server has a power switch that controls third server on and off states. The second data channel is enabled when the power switch is turned on. The third server arbitrates the flow of message traffic from the second server back to the first server by applying an on-board security module's encoded set of rules to determine whether the message is permitted to proceed to the first server.

Abstract: Disclosed herein are techniques for preventing or minimizing completion timeout errors on a computer device. An apparatus include a processing logic circuit and a timeout logic. The timeout logic is configured to: generate a timeout event based on a transaction not completed by the processing logic circuit within a timeout period; determine a number of the timeout events generated during a monitoring period; and responsive to determining that the number equals to or exceeds a threshold, reduce the timeout period.

Abstract: A method for controlling a storage device is provided. The method may include: transmitting an initial command conforming to a first communications protocol and a data payload including a command parameter conforming to a second communications protocol to the storage device; transmitting a setting command conforming to the first communications protocol to the storage device; transmitting a confirmation command conforming to the first communications protocol to the storage device; and according to a data payload corresponding to the confirmation command, confirming whether the initial command, the setting command, and the confirmation command are successfully executed.

Abstract: An interconnect circuit, and method of operation of such an interconnect circuit, are provided. The interconnect circuitry has a first interface for coupling to a master device and a second interface for coupling to a slave device. Transactions are performed between the master device and the slave device, where each transaction comprises or more transfers, and each transfer comprises a request and a response. A first connection path between the first interface and the second interface is provided that comprises a first plurality of pipeline stages. The first connection path forms a default path for propagation of the requests and responses of the transfers. A second connection path is also provided between the first interface and the second interface that comprises a second plurality of pipeline stages, where the second plurality is less than the first plurality. Path selection circuitry is then used to determine presence of a fast path condition.

Abstract: A device includes a first input/output (I/O) port for communication with an external processor, a second I/O port for communication with a second device, and an interface adaptor supporting communication through the first and second I/O ports via a protocol having a plurality of layers, including an application layer, a physical layer, and a physical adaptor layer. The application layer processes information according to an application layer format and the physical adaptor layer processes information according to a physical adaptor layer format. The device receives from the external processor through the first I/O port a request in the application layer format that one or more communication conditions be set for a physical layer of the second device, converts the request from the application layer format to the physical adaptor layer format, and sends the converted request in the physical adaptor layer format to the second device through the second I/O port.

Abstract: A method of providing high-availability services across a one-way data diode is provided, wherein first network and second networks are connected by first and second data channels each including a one-way data diode. Identical signals are carried by both data channels, but only the signal carried by the first data channel reaches the second network under normal operating conditions. System heartbeats, or periodic shared signals, are used to monitor health status of the parallel data channels, and a loss of heartbeat on the high side of the data diode on the first data channel triggers a timing channel to begin measuring the failure interval relative to a preset failover value. If the failover interval is exceeded, a failover to the second data channel is executed, provided the second data channel is still receiving data from the first network.

Abstract: The present disclosure includes apparatuses and methods for in-memory operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. The memory device includes first sensing circuitry coupled to the first subset, the first sensing circuitry including a sense amplifier and a compute component configured to perform an in-memory operation. The memory device includes second sensing circuitry coupled to the second subset, the second sensing circuitry including a sense amplifier. The memory device also includes a controller configured to direct a first movement of a data value to a selected subarray in the first subset based on the first sensing circuitry including the compute component.

Abstract: An integrated circuit including an FPGA having an input to receive an input data stream which includes a first portion and a second portion, processing circuitry to generate processed data by processing only the first portion of the input data stream via a data processing operation, and an output to output the processed data. The integrated circuit further includes logic circuitry, separate from the FPGA, including an input to receive the input data stream, data alignment circuitry to temporally synchronize the second portion of the input data stream with the processing of the first portion of the input data stream via the processing circuitry, and data combining circuitry to generate an output data stream using the processed data from the FPGA and the second portion of the input data stream received from the data alignment circuitry.

Abstract: Embodiments provide methods and systems for detecting rogue endpoints on a device management bus. A communications controller configured as a bus owner initiates discovery of managed devices coupled to the bus and generate a unique identifier for each managed device. The communications controller transmits a bus configuration message to the managed devices, including the respective unique identifiers. The managed devices are configured as bus endpoints based on the bus configuration message. The managed devices also capture the bus address of the communications controller from the received bus configuration message. Messages received by a managed device are authenticated as originating from the communications controller if the messages include the unique identifier provided to that managed device. The messages may be further authenticated by comparing the bus address of the message sender against the captured bus address of the communications controller.

Abstract: Apparatuses, systems, and methods are provided for electronic data logging. More particularly, apparatuses, systems, and methods are provide for electronic data logging which may incorporate a vehicle electronic device that may store data when the vehicle electronic device is not in communication with an external device and that may transmit data when the vehicle electronic device is in communication with an external device.

Abstract: Methods for transfer of bulk data from a leader device to a follower device over a bus are described. The methods employ address frames and write frames. The bus, the address frames, and the write frames are compatible with Clause 45 of IEEE Std 802.3-2015. The methods achieve a reduction in the number of frames employed to transfer data as contrasted with conventional indirect write transactions. After transmitting on a Management Data Input/Output (MDIO) data signal an address frame that specifies the follower device and that contains the address of an initial register, the leader device proceeds to transmit on the MDIO data signal multiple write frames that specify the target follower device, the multiple write frames transmitted one at a time, each write frame containing a different block of the bulk data. A follower device implements a post-write-increment-address action, despite the absence of any definition in Clause 45 of IEEE Std 802.3-2015 of a post-write-increment-address frame.

Abstract: A bus allocation system includes at least one connector coupled to a plurality of devices, and a processing subsystem that includes at least one root port that is coupled to the at least one connector. The processing system executes instructions that are stored on a memory subsystem in order to provide a Basic Input Output System (BIOS) that is configured, during a boot process, to assign temporary bus values to each of the plurality of devices that are coupled to the connector. Based on the assigned temporary bus values, the BIOS detects each link that couples each of the plurality of devices to the connector, and determines a bus allocation count based on the detected links. The BIOS then allocates a number of buses for the at least one root port based on the bus allocation count.

Abstract: A system, method and computer readable medium for operating a First In, First Out (FIFO) buffer that transfers data between a host and a plurality of endpoints using chip select is disclosed. The method includes receiving a current value of a read pointer and a status for an active endpoint and reading data at a location to which the read pointer points and setting a tag associated with the location to which the read pointer points to indicate availability.

Abstract: Various embodiments are directed to a USB hub configured for supporting multiple data transfer speed protocols. The USB hub comprises a plurality of protocol/LINK layer components; and a physical layer component shared among the plurality of protocol/LINK layer components and supporting at least two USB connection ports. The physical layer component is in communication with each of the plurality of protocol/LINK layer components. A buffer system (including RX/TX buffers) is shared among the plurality of protocol/LINK layer components and a USB host controller component is in communication with the buffer system. The physical layer component is configured for operating in a first mode to support one of the at least two USB ports in a first operating mode; and operating in a second mode to support the at least two USB ports in a second operating mode.

Abstract: An external device including at least a first connector, a signal transmission module and a power module is provided. The signal transmission module is electrically connected to the first connector. The power module is electrically connected to the first connector and outputs power via the first connector. The signal transmission module of the external device is a pluggable external graphics card. A graphics card or a graphics chip in the electronic device connected to the external device can be replaced via the external graphics card. Consequently, the graphics card or the graphics chip in the electronic device can be eliminated and thus the electronic device can be made light and thin.

Abstract: A method and system for conducting meetings, e.g. making it easy for the user to connect his device to the meeting or come to a common shared view of the meeting content, where all devices participating in the meeting are located within one physical meeting room. In another embodiment, at least some devices are located outside the meeting room. In principle there is no meeting room necessary, but all devices can be distributed anywhere in a region or in the world, and after connection, the meeting content is shared to all physical meeting rooms and remote devices of the system.

Abstract: A data storage device includes a main storage memory and a non-volatile cache memory system. The non-volatile cache memory system comprises a master device, a first slave device communicatively coupled to the master device, the first slave device comprising a first non-volatile memory, and a second slave device communicatively coupled to the master device, the second slave device comprising a second non-volatile memory of a different type than the first non-volatile memory. The data storage device also includes a controller communicatively coupled to the main storage memory and to the non-volatile cache memory system, the controller is configured to, upon a power loss to the data storage device, store volatile data into the non-volatile cache memory system.

Abstract: A baseboard management controller (BMC) includes a plurality of device I2C interfaces. Each device I2C interfaces provides a device I2C bus that is ported externally to the BMC. The BMC further includes a plurality of device buffer/switch circuits. Each device buffer/switch circuit is connected to a respective device I2C bus, and is configured to selectably connect to the respective I2C bus in a high-impedance mode, an open-drain mode, and a FET switch mode. The BMC further includes a multiplexor/driver circuit that has a multiplexor I2C interface that provides a multiplexor I2C bus that is ported externally to the BMC. The multiplexor/driver circuit is coupled to each device I2C bus via the respective buffer/switch circuit, and is configured to selectively couple one of the device I2C busses to the multiplexor I2C bus, and to select one of the high-impedance mode, the open-drain mode, or the FET switch mode for the selected buffer/switch circuit.

Abstract: One embodiment provides an apparatus comprising a first processor to execute a function driver for a peripheral having a first bus interface and virtualized host controller interface logic to provide a protocol interface associated with the first bus interface to the function driver to enable the function driver to control a set of peripherals connected via at least a second bus interface, the second bus interface different from the first bus interface.

Abstract: An operation state recording system is provided in a target device including: an input unit; a device group; and a control system controlling the device group based on an input of the input unit. The operation state recording system records an operation state from a start to a stop of an operation of the target device, and the control system includes: a plurality of control devices controlling a plurality of devices; nonvolatile storage units where the operation state of the target device is recorded as operation history information; and a time measuring unit measuring a time.

Abstract: A power-up signal generation circuit including a pre-power-up signal generation block operates by using a first power supply voltage, and generates a pre-power-up signal when the first power supply voltage becomes higher than a first level, and a second power supply voltage becomes higher than a second level; a level shifting block suitable for pull-down driving a first node when the pre-power-up signal is not in an activated state, and pull-up driving the first node with the second power supply voltage when the pre-power-up signal is in the activated state; a driving block suitable for pull-down driving the first node when the second power supply voltage is lower than the second level; and a power-up signal driving block operates by using the second power supply voltage, and generates a power-up signal through a second node by driving the second node based on a voltage level of the first node.

Abstract: An information processing apparatus including: a communication processor; a controller that makes the communication processor be in a port opened state when the information processing apparatus is powered on; and a setting processor that sets connection information in the communication processor made into the port opened state by the controller through executing a program file to set the connection information. This configuration makes it possible to easily set communication setting information.

Abstract: A server device includes a plurality of interface circuits configured to connect with a network, and perform format conversion between network packets and data chunks, the network packets being packets communicated with the network, the data chunks complying with an internal format; a plurality of memory modules operating independently of each other; and a switch circuit connected between the plurality of interface circuits and the plurality of memory modules, the switch circuit being configured to select at least one memory module from among the plurality of memory modules based on an attribute of a first data chunk transmitted from the plurality of interface circuits and, send the first data chunk to the selected memory module, wherein the selected at least one memory module is configured to, decode the first data chunk, and perform a read or write operation associated with the first data chunk based on the decoding result.

Abstract: An I/O-abstracted configuration is defined for a field device that has not yet been assigned or allocated to communicate via a particular I/O device, and the field device (and optionally portions of the process control loop of which the field device is a part) is commissioned based on contents of its I/O-abstracted configuration. The field device's I/O-abstracted configuration is stored in an instance of a device placeholder object, which may be common to multiple types of devices and multiple types of I/O. A property of the device placeholder object may be exposed based on the value entered for another property, and the device placeholder object may store abstracted values as well as explicit or discrete values that are descriptive of the field device and its behavior. Upon I/O-assignment or allocation, values held in the device's I/O-abstracted configuration may be transferred to or otherwise synchronized with the device's as-built configuration.

Abstract: A first portion of a distributed catalog service is implemented for a given one of a plurality of distributed processing node clusters associated with respective data zones, each of the clusters being configured to perform processing operations utilizing local data resources locally accessible within its corresponding data zone. The first portion of the distributed catalog service receives a request to identify for each of a plurality of data resources to be utilized by an application initiated in the given cluster whether the data resource is a local or remote data resource relative to the given cluster, and provides a response to the request. The first portion of the distributed catalog service in combination with additional portions implemented for respective additional ones of the distributed processing node clusters collectively provide the distributed catalog service with capability to resolve local or remote status of data resources in each of the data zones.

Abstract: A system, method and computer readable medium for operating a First In, First Out (FIFO) buffer that transfers data between a host and a plurality of endpoints using chip select is disclosed. The method includes receiving a current value of a read pointer and a status for an active endpoint and reading data at a location to which the read pointer points and setting a tag associated with the location to which the read pointer points to indicate availability.

Abstract: Apparatuses, systems, methods, and program products are disclosed for indicating a connection to a printer. A signal reception module receives a signal at a printer of a plurality of printers from an information handling device. The signal requests an indication that the information handling device is connected to the printer. An indication type module determines a type of indication to provide based on the received signal. An indicator provider module provides an indication of the determined type from the printer that indicates the information handling device is connected to the printer.

Abstract: A system and a method are disclosed for simulating a target system. The target system may include a plurality of components coupled via a communication bus. Each component of the target system may include a model algorithm representing the internal behavior of the component, and a model interface configured to transfer and/or receive communication payloads to/from a peer component in the target system. During simulation initialization, a simulation model of a component of the target system is accessed and a protocol engine, associated with a bus communication protocol is selected to be attached to the simulation model of the accessed component. Then, during the simulation of the target system, the model interface receives an incoming payload and informs the protocol engine of the received payload. The protocol engine may instruct the model algorithm of the component to perform a protocol specific action based on the received payload.

Abstract: An electronic card and a detecting method are provided. The electronic card includes a connector. The detecting method detects whether an output signal from a host is received by Pin 41, Pin 43, Pin 47 and Pin 49 of the connector, or Pin 29, Pin 31, Pin 35 and Pin 37 of the connector, or Pin 17, Pin 19, Pin 23 and Pin 25 of the connector, or Pin 5, Pin 7, 11 and Pin 13 of the connector. According to the detecting result and the output signal, the electronic card judges the communication protocol of the host is a SATA communication protocol, a PCIe communication protocol or a USB3.0 communication protocol.

Abstract: Protection circuits, USB interface integrated circuits, and methods for protecting host circuitry from USB port pin overvoltages, in which a switch is connected between a USB port pin and a middle node, and a detection circuit compares the middle node voltage with a reference voltage. A control circuit turns off the switch and turns on a clamp circuit to conduct pull down current from the middle node in response to the middle node voltage exceeding the reference voltage to mitigate overvoltage conditions on a host pin coupled to the middle node. When the middle node voltage falls below the reference voltage, the control circuit delays for a predetermined time and then turns off the clamp circuit and turns on the switch.