Abstract: An apparatus comprising an interface, a first port, and a second port. The interface may be configured to connect to a host computer. The first port may be configured to connect to a first set of storage devices using a first protocol. The second port may be configured to connect to a second set of storage devices using a second protocol. The apparatus may provide support for the first protocol and the second protocol to allow communication using both the first protocol and the second protocol through the interface.

Abstract: A method of conversion by at least one interface circuit connected between a first bus including at least one data wire and one clock wire, and at least one second single-wire bus, of a transmission between a master circuit connected to the first bus and at least one slave circuit connected to the second bus, wherein a speculative read command is sent to the slave circuit before interpreting the state of a bit for controlling a reading or a writing, originating from the master circuit.

Abstract: System and methods for improving connections to an information handling system are disclosed. An enhanced serial attached small computer system interface for an information handling system includes a receptacle which is connectable to an information handling system and a connector which is connectable to the receptacle. The connector comprises a first set of signal pins positioned on a first planar surface of the connector and a second set of signal pins positioned on a second planar surface of the connector. The second planar surface is not co-planar with the first planar surface. The connector further includes a third set of signal pins positioned on a third planar surface of the connector and the third planar surface is not co-planar with the first planar surface and the second planar surface.

Abstract: A system-on-a-chip (SOC) bridge is described that applies an adapted delay, or latency, to data transfers across the bridge to avoid data corruption without reducing data transfer performance. The adapted delay assures that a source SOC service device transferring data to a destination SOC service device via the bridge and an SOC crossbar bus does not prematurely assume that the data transfer is complete upon transferring the data to the bridge. The bridge causes wait states to be inserted into the transfer between the source SOC service device and the SOC bridge until the SOC bridge receives confirmation that the data has arrived at the destination SOC service device. The adapted delay assures that subsequent operations are not prematurely initiated by the source SOC service device and/or the SOC CPU that may interfere with the data transfer from the SOC bridge to the destination SOC service device, causing corrupted data.

Abstract: A management hub is disclosed. The management hub comprises an interface; a master hub controller coupled to the interface; a plurality of ports coupled to the master hub controller; a microcontroller coupled to the master hub controller; and hub setting switch and a slave hub controller coupled to the microcontroller and the plurality of ports. The management hub also includes a memory device coupled to the microcontroller, the memory device including a hidden drive information partition and a hidden drive organizer partition for managing and identifying information in various drives coupled to the plurality of ports, wherein when the management hub is first connected to a host system the drives are displayed in an inactive state.

Abstract: Embodiments of the invention relate to upbound input/output expansion requests and response processing in a PCIE architecture. A first request to perform an operation on a host system is intitiated. The first request is formatted for the first protocol and includes data that is required in order to process the first request. A second request is created in response to the first request, the second request includes a header and is formatted according to the second protocol. The data required to process the first request in the header of the second request is stored, and the second request is sent to the host system.

Abstract: Accessing data stored in a memory device through an interface, with addressing data on the memory device through at least one address bus, controlling at least data flow to and from the memory device through at least one command bus, and transferring data to and from the memory through at least one data bus wherein commands on the command bus are adjusted depending on the type of memory connected to the interface.

Abstract: Transactions of the request/response type between a first circuit module and a second circuit module operating with incompatible protocols or interfaces envisage organizing a queue of memory locations for storing transaction information items and transaction identifiers associated to said transactions and implementing the transactions via operations of reading/writing of the locations in the queue, mapping on the transaction identifiers information for management of the queue.

Abstract: Communication interfaces having reduced signal lines. In one aspect, a physical layer circuit, set forth by way of example and not limitation, interfaces a link controller and a device communication bus, and includes a wrapper coupled to a first interface bus having only six or less communication lines and coupled to a second interface bus having a larger number of communication lines than the first interface bus. The wrapper can communicate first signals with the link controller over the first interface bus and perform conversion between the first signals and second signals communicated on the second interface bus. A core, coupled to the wrapper by the second interface bus, can communicate device signals with the device communication bus by performing conversion between the second signals and the device signals.

Abstract: A signal transmission system includes a controller interface, a protocol engine to convert data based on at least one protocol, and a common protocol interface coupled between the controller interface and the protocol engine. The controller interface includes or is coupled to a common dispatcher, and the data is to be transmitted between the controller interface and protocol engine through the common protocol interface and common dispatcher. The same protocol engine may convert data into different protocols, with all of the converted data be transmitted to or received from the controller interface through the common dispatcher and common protocol interface.

Abstract: A method of providing high density expansion of a USB network, the method comprising: attaching a plurality of USB hubs to adjacent slots in a PXI instrumentation chassis; configuring one of the USB hubs as a primary USB Hub; connecting an upstream port of the primary USB Hub to a USB network; configuring a first downstream port of the primary USB Hub to communicate across a first PXI Local Bus to a first adjacent USB Hub of the USB Hubs other than the primary USB Hub, the first adjacent USB Hub being adjacent to the primary USB Hub; configuring a plurality of other downstream ports of the primary USB Hub to provide expansion of the primary USB Hub; connecting an upstream port of the first adjacent USB Hub to the first PXI Local Bus, wherein the first PXI Local Bus is in the direction of the primary USB Hub; configuring a first downstream port of the first adjacent USB Hub to communicate across a second PXI Local Bus to a second adjacent USB Hub of the USB Hubs other than the primary USB Hub, the second adjac

Abstract: A solution for setup and optimization of a data transfer path in extended computer systems, where the I/O system is virtualized. The solution achieves advantageous results via a mechanism that automates the configuration of multiple data path components. The solution achieves initial optimization and then automates continual optimization of the data path through monitoring of changes and through dynamic adjustment of system resources and data transfer characteristics.

Abstract: The present invention intends to provide a high-performance multi-processor device in which independent buses and external bus interfaces are provided for each group of processors of different architectures, if a single chip includes a plurality of multi-processor groups. A multi-processor device of the present invention comprises a plurality of processors including first and second groups of processors of different architectures such as CPUs, SIMD type super-parallel processors, and DSPs, a first bus which is a CPU bus to which the first processor group is coupled, a second bus which is an internal peripheral bus to which the second processor group is coupled, independent of the first bus, a first external bus interface to which the first bus is coupled, and a second external bus interface to which the second bus is coupled, over a single semiconductor chip.

Abstract: A system for implementing non-standard I/O adapters in a standardized I/O architecture, the system comprising an I/O hub communicatively coupled to an I/O bus and at least one I/O adapter, the I/O hub including logic for implementing a method, the method comprising receiving a request to perform an operation on the I/O adapter from a requester at a requester address, the I/O adapter at a destination address, determining that the request is in a format other than a format supported by the I/O bus, the I/O bus expecting a requester identifier at a first location in a header of the request, reformatting the request into the format supported by the I/O bus, the reformatting comprising storing the requester address, the destination address and an operation code at the first location in the header of the reformatted request, and sending the reformatted request to the I/O adapter.

Abstract: The controlled device includes: an external terminal; a memory; a processor for controlling the memory according to a control signal received via the external terminal; a plurality of buses forming a first transmission path connecting the external terminal and the memory via the processor, and a second transmission path connecting the external terminal and the memory directly by bypassing the processor; and a switching unit for switching a transmission state to either a first transmission state in which one or more of the buses forming the first transmission path are caused to transmit the control signal from the external terminal to the processor according to a first protocol, or a second transmission state in which one or more of the buses forming the second transmission path are caused to transmit data directly between the external terminal and the memory according to a second protocol capable of transmitting data at a higher rate than the first protocol.

Abstract: An apparatus for transmitting data across a high-speed serial bus includes an IEEE 802.3-compliant PHY having a GMII interface; an IEEE 1394-compliant PHY in communication with the IEEE 802.3-compliant PHY via a switch; the switch determining whether data transmission is be routed to the IEEE 802.3-compliant PHY or the IEEE 1394-compliant PHY; a first connection, the first connection for transmitting data between a device and the IEEE 802.3-compliant PHY; and a second connection, the second connection for transmitting data between a device and the IEEE 1394-compliant PHY.

Abstract: A data and voice communication system includes communication between a line card and an accelerator card. Voice, data, and control traffic is received from the line card and is transmitted to the accelerator card via a physical link having separate voice, data, and control logical channels. The separate voice, data, and control logical channels are represented by labeled data packets.

Abstract: The present invention provides a information transmission device including: a transmission section that transmits information to a first transmission path that transmit information serially; a reception section that receives information from a second transmission path; a waveform shaping section that, according to setting information, shapes at least one of a signal waveform of the information for transmission, and/or a signal waveform of the information for reception; and a controller that, when establishing communication, controls the transmission section to transmit predetermined first information that requests communication establishment, and effects control to change the first setting information and controls the transmission section to re-transmit the first setting information when the reception section has not received the first information within an interval that from the beginning of transmission of the first information until a predetermined duration required for communication establishment has elap

Abstract: A method for offloading remote terminal services processing tasks to a peripheral device that would otherwise be performed in a computer system's processor and memory. In one embodiment, the disclosed method is utilized in a layered network model, wherein computing tasks that are typically performed in network applications are instead offloaded to a peripheral such as a network interface card (NIC).

Abstract: A circuit for simultaneously analyzing performance and bugs includes a mapping unit and a USB 3.0 data flow analyzer. The mapping unit is used for mapping commands transmitted to a USB 3.0 host through a peripheral component interconnect express and internal events of the USB 3.0 host to a packet of a USB 3.0 bus. The USB 3.0 data flow analyzer is used for analyzing performance and bugs of the USB 3.0 host through the packet of the USB 3.0 bus.

Abstract: A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals from a USB host and independently provides responses required by USB specification within the required time frame. The upstream processor also contains storage for descriptors for a device associated with this upstream processor. The main controller obtains the descriptors by commanding the downstream processor, and passes them to the upstream processor. The downstream processor connectable to USB-compliant devices accepts the USB signals from the USB-compliant devices and provides responses required by USB specification within the required time frame. The main controller interconnects the upstream and downstream processors, and provides timing independence between upstream and downstream timing. The main controller also commands the downstream processor to obtain device descriptors independent of the USB host.

Abstract: A method and system for providing computer input/output (I/O) functionality within a remote computing environment. The system comprises a host audio controller and a remote audio controller for bridging audio data between a host computing system and at least one remote audio device, a host USB controller and a remote USB controller for bridging USB data between the host computing system and at least one remote USB device, and an encoder module and a remote display decoder for bridging a digital video signal from the host computing system to a remote display, wherein the host audio controller, the host USB controller, and the encoder module are communicatively coupled to the remote audio controller, the remote USB controller, and the remote display decoder, respectively, via a computer network.

Abstract: A communication device is driven by an on-demand driver installed in an apparatus that includes an on-demand driver generating program that generates the on-demand driver for the communication device based on device information of the communication device. The communication device includes a memory unit that stores therein the device information of the communication device, a responding unit that, in response to a request for obtaining the device information from the on-demand driver generating program, sends the device information stored in the memory unit to the apparatus, and an updating unit that is used in externally updating the device information stored in the memory unit.

Abstract: Methods, apparatus, and product are disclosed for expanding functionality of hard drive bays in a computing system that include: providing, by a connector in a hard drive bay, access to two or more data communication busses of different type; receiving, by the connector of the hard drive bay, a device mounted within the hard drive bay; and communicately coupling, by the connector of the hard drive bay, the device to one of the data communication busses.

Abstract: An automation appliance (6) having at least one field bus interface (12) for connection to a field bus (2) and transmission of data packets (DP) with process data (PD) via the field bus (2) and having at least one local bus interface (21) for connection to a local bus (7) and transmission of process data (PD) between field devices (9a, 9b, 9c) connected to the local bus (7) and the automation appliance (6), and having means for converting the data packets (DP) coming from the field bus (2) into a data stream (DS) for the local bus (7) and for converting the data stream (DS) sent from the local bus (7) to the automation appliance (6) into data packets (DP) for the field bus (2) is described.

Abstract: A method of establishing a virtual USB interface for a non-USB device, comprising the steps of establishing a non-USB interface to communicate with the non-USB device, generating a virtual USB physical device object to provide a USB transport layer driver, establishing the virtual USB interface to communicate with the USB transport layer driver, filtering a transmitting command of the USB transport layer driver based on the virtual USB interface, and filtering a returned information of the non-USB device based on the non-USB interface.

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

Abstract: System and method for zero client communications. A zero client device includes a housing, and in the housing, a transcoding processing unit (transcoder) and a communications processing unit coupled to the transcoder. The transcoder is configured to receive input data from human interface device(s), encode the input data, and provide the encoded input data to the communications processing unit for transmission over a network to a server. The communications processing unit is configured to receive the encoded input data from the transcoder, transmit the encoded input data over the network to the server, receive output data from the server, and send the output data to the transcoder. The transcoder is further configured to receive the output data from the communications processing unit, decode the output data, and send the decoded output data to at least one of the human interface devices.

Abstract: A host device includes a first file system, and a storage device includes a plurality of memory units and a plurality of controllers. While the host device is operative coupled to the storage device, the host device creates a second file system corresponding to the storage device and copies host content from the first file system to the second file system. The second file system is segmented into a plurality of segments, each of the plurality of segments being uniquely associated with a particular one of the plurality of controllers. The host device selects a data transfer rate to write the host content from the second file system to the storage device.

Abstract: Various techniques are provided for bridging interfaces, such as different interfaces for use with a host device. In one example, a system includes an asynchronous first interface adapted to transmit and receive data to and from a host device in accordance with a first protocol. A synchronous second interface is adapted to transmit and receive data to and from a device external to the host device in accordance with a second protocol. A bridge controller is adapted to convert the data received from the host device from the first protocol to the second protocol for transmission to the external device. A clock and data recovery (CDR) block is adapted to recover a clock signal from the first interface to synchronize the data received from the host device. The second interface is adapted to synchronize the converted second protocol data transmitted to the external device using the recovered clock signal.

Abstract: A system, circuit and method for improving system-on-chip (SoC) bandwidth performance for high latency peripheral read accesses using a bridge circuit are disclosed. In one embodiment, the SoC includes the bridge circuit, one or more bus masters, at least one high bandwidth bus slave and at least one low bandwidth bus slave that are communicatively coupled via a high bandwidth bus and a low bandwidth bus. Further, the bus masters access the at least one low bandwidth bus slave by issuing an early read transaction request in advance to a scheduled read transaction request. Furthermore, the bridge circuit receives the early read transaction request and fetches data associated with the early read transaction request. In addition, the bridge circuit receives the scheduled read transaction request. The fetched data is then sent to the bus masters upon receiving the scheduled read transaction request.

Abstract: A bridge device for connecting a USB 3 host device with a plurality of downstream, non-USB 3 mass storage devices, such as SATA or PATA devices. The bridge device comprises an embedded hub having a plurality of internal USB 3 devices. The internal USB 3 devices do not have a physical USB 3 interface. The bridge device also has at least one downstream physical non-USB 3 device, to which a mass storage device may be attached. The internal USB 3 devices enable the host device to be presented with a plurality of USB 3 devices. This, in turn, allows transfer to the plurality of downstream physical non-USB 3 devices, via the internal USB 3 devices at an increased rate. The bridge may also include a downstream physical USB 3 interface. This can allow multiple bridge devices to be connected together in a cascade.

Abstract: A solid state disk system is disclosed. The system comprises a user token and at least one level secure virtual storage controller, coupled to the host system. The system includes a plurality of virtual storage devices coupled to at least one secure virtual storage controller. A system and method in accordance with the present invention could be utilized in flash based storage, disk storage systems, portable storage devices, corporate storage systems, PCs, servers, wireless storage, and multimedia storage systems.

Abstract: Described embodiments provide a system having a bridge for connecting two different processor buses. The bridge receives a command from a first bus, the command having an identification field having a value. The command is then entered into a buffer in the bridge unless another command having the same identification field value exists in the buffer. Once the command with the same identification field value is removed from the buffer, the received command is entered into the buffer. Next, the buffered command is transmitted over a second bus. A response to the command is eventually received from the second bus, the response is transmitted over the first bus, and the command is then removed from the buffer. By not entering the received command until a similar command with the same identification value is removed from the buffer, command ordering is enforced even though multiple commands are pending in the buffer.

Abstract: The present invention relates to a wireless protocol adapter assembly for diagnostics, analysis, and monitoring. The wireless protocol adapter assembly provides a common connection interface between a sealed common electronics package and a plurality of vehicle connectors that access a plurality of vehicle networks respectively for translating and transferring signals between the plurality of in-vehicle networks and a host computer. The common connection interface allows the vehicle connector compatible with a particular vehicle type to be coupled to the common electronics package. The common electronics package can recognizes when it is connected to a vehicle network running a particular protocol and automatically switch to that protocol. A wireless protocol adapter board having a standard connection pinning arrangement allows wireless links to be changed or altered as wireless standards change and evolve.

Abstract: Embodiments of the invention are generally directed to detection of cable connections for electronic devices. An embodiment of an apparatus includes a port for the connection of a cable, the port being compatible with a first protocol and a second protocol, the port including multiple pins including a first pin for a first line and a second pin for a second line. The apparatus further includes a processor to determine a type of source device connected to the cable, where determination of the type of source device includes the apparatus detecting a low signal on the first line and a high signal on the second line, and, upon detecting the low signal on first line and the high signal on the second line, the apparatus initiates a discovery sequence, the discovery sequence including transmitting a signal sequence on the second line and attempting to receive the signal sequence on the second line.

Abstract: A bridge includes a Peripheral Component Interconnect Express interface supporting at least two lanes, an Extensible Host Controller Interface, and a Universal Serial Bus 3.0 root hub. The Peripheral Component Interconnect Express interface is used for coupling to a host. Each lane of the at least two lanes provides a highest data transmission speed. The Extensible Host Controller Interface is coupled to the Peripheral Component Interconnect Express interface for storing data transmitted by the Peripheral Component Interconnect Express interface. The Universal Serial Bus 3.0 root hub includes a first controller and a second controller. The first controller and the second controller are used for controlling data transmission of four ports, and a highest data transmission speed provided by each port of the four ports is not more than the highest data transmission speed provided by the lane.

Abstract: A mass storage device, system, and method for operating a mass storage device are disclosed. In one such mass storage device, a host bus adaptor emulates a SATA mass storage device over a PCIe interface with a host system. The host system generates commands with the PCIe mass storage device in the same format as if communicating with a SATA mass storage device. The PCIe mass storage device responds in the same SATA format.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: According to an example embodiment of the present invention, a method is implemented for transmitting data between a Media Access Control Layer (MAC) (100) and a Physical Layer (PHY) (150) using an internal data bus for transmitting a set of internal symbols between the MAC (100) and PHY (150). A subset of internal symbols does not have a corresponding PHY symbol. An external data bus carries data symbols. An external interface (102, 118) provides command information on one or more dedicated command lines and provides the data symbols. An encoder (108, 110) encodes the provided command information into one or more of the subset of internal symbols. An internal interface (106, 107, 109, 111) transmits the one or more of the subset of internal symbols and the data symbols between the MAC (100) and PHY (150) using the internal data bus.

Abstract: Open architecture communication systems and methods are provided that allow flexible data transmission between gaming machines and other devices and nodes within a gaming machine network. The gaming machine and other devices employ a communication interface that sends and receives data via a common communication protocol and via common communication hardware. The communication interface and common communication protocol allow data transfer between gaming machines and other network nodes such as gaming service servers, despite the presence of different proprietary gaming machine functions and proprietary communication protocols and despite the presence of various proprietary hardware and proprietary communication protocols relied on by the servers.

Abstract: A method for data communication between a programmable controller (2) and a data processing device (12) via a universal data interface (11b) of the data processing device (12) is described. In the method, at least one communication interface implemented by means of software drivers and selected in dependence on the availability is allocated to a programmable controller (2) connected to a hardware connection in a wire-connected manner or wirelessly.

Abstract: An apparatus and method for converting a protocol interface are provided. A protocol converter may analyze a protocol of protocol data, and may sequentially output a plurality of sub-data of the input protocol data according to types of the plurality of sub-data and a plurality of phase information representing the types of the plurality of sub-data. A phase channel line may transmit phase information received from the protocol converter among the plurality of phase information. A data channel line may simultaneously transmit the received phase information and a sub-data corresponding to the received phase information.

Abstract: Methods, systems, and computer readable media for providing BIOS data and non-BIOS data on the same non-volatile memory. According to one aspect, a system for providing BIOS data and non-BIOS data on the same non-volatile memory includes a controller for controlling access by a host to a non-volatile memory for storing data, the data including BIOS data and non-BIOS data. The controller includes a first bus interface for communicating data to and from the host via a first bus of a first bus protocol, a second bus interface for communicating data to and from the host via a second bus of a second bus protocol, and a third interface for communicating data to and from the non-volatile memory. The first bus comprises a bus that is operable after power-on reset and before BIOS is accessed.

Abstract: Split capture of USB protocol streams is disclosed. A first set of packets associated with a first USB protocol and a second set of packets associated with a second USB protocol are received at a hardware protocol analyzer via a monitored bus. The first set of packets and the second set of packets are maintained as separate streams at the hardware protocol analyzer. The first set of packets and the second set of packets are transferred from the hardware protocol analyzer to an analysis computer via a first logical connection configured to transfer packets comprising the first set of packets and a second logical connection configured to transfer packets comprising the second set of packets.

Abstract: In one embodiment, a converged protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to provide for data transfer across a physical interconnect. This stack can be incorporated in an apparatus that includes a protocol stack for a first communication protocol including transaction and link layers, and a physical (PHY) unit coupled to the protocol stack to provide communication between the apparatus and a device coupled to the apparatus via a physical link. This PHY unit may include a physical unit circuit according to the second communication protocol. Other embodiments are described and claimed.

Abstract: This disclosure involves methods and systems for providing a host with a Bluetooth transceiver by way of a virtual USB connection to a PCI/PCIe bus in which the virtual USB connection is controlled by a modified OHCI. The Bluetooth transceiver is configured to send a status signal when there is data to be transferred to the host. The modified OHCI is configured to activate a list processor upon receipt of the status signal, such that the list processor controls the transfer of the data to be transferred to the host. After delivery of the data to the host, the modified OHCI is configured to inactivate the list processor. Further, the modified OHCI is configured to be compatible with standard USB software resident on the host.

Abstract: Charging a device using a plurality of handshakes. A first device may provide a first handshake to a second device. A device of a first device type may be configured to charge its battery without further communication based on the first handshake. The first device may monitor a connection to the second device for a second handshake corresponding to a device of a second device type. In response to detecting the second handshake, the first device may provide a response to the second device. Accordingly, the second device of the second device type may be configured to charge its battery based on the second handshake.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.