Abstract: A disclosed example system includes a termination panel, and a shared bus on the termination panel. The shared bus is to removably receive a plurality of bases that removably receive modules to communicate with field devices, and communicatively couple the modules to an input/output card to exchange communications between the modules and a controller that is in communication with the input/output card via a second bus.

Abstract: A bus-protocol converting device includes: a command detecting unit that detects a command sent from an external-memory control device, connected to a primary bus, to a primary bus interface controller; a command converting unit that converts the detected command into a command to be sent from a secondary bus interface controller to an external memory device through a secondary bus; a status detecting unit that detects a status sent from the external memory device; a status converting unit that converts the detected status into a status to be sent from the primary-bus interface controller to the external-memory control device through the primary bus; and a data transfer controller that is provided between the primary bus interface controller and the secondary bus interface controller to perform data transfer between the external-memory control device and the external memory device through a DMA bus.

Abstract: An apparatus, system, and method are disclosed for a baseboard management controller (BMC) which includes an FPGA with a monitor module for monitoring the operations parameters of a host computer device. In addition, the BMC has a host connector that connects the BMC to the system bus of the host computing device, allowing the BMC access to the computing elements on the host. The host connector has reconfigurable pins with connection configuration controlled by the FPGA. In addition, the BMC has a server with a processor and associated non-volatile memory on board. The operating system provides services to the host computing device and its constituent components, as well as allowing advanced networking and interconnectivity with other BMCs in a management network.

Abstract: Methods for transmitting application specific or extended commands between a host and a memory card are disclosed. Commands for an extended card protocol are embedded in messages, along with a marker, in the data or command portion of a base card transmission protocol that is used to communicate between the host and the memory card. This allows for the transmission of application specific commands that lack a corresponding command in the base card protocol. The method can be implemented on the host side at the device driver level or the file level. In order to implement a read command in the extended card protocol, a write command in the base card protocol with an encapsulated read command in the extended protocol is first sent to a logical address, followed by a read command to the same logical address. Message set identifiers associate embedded commands and data received in separate transmissions.

Abstract: An embodiment of a multichip module is disclosed. For this embodiment of the multichip module, a transceiver die has transceivers. A crossbar switch die has at least one crossbar switch. A protocol logic blocks die has protocol logic blocks. The transceiver die, the crossbar switch die, and the protocol logic blocks die are all coupled to an interposer. The interposer interconnects the transceivers and the protocol logic blocks to one another and interconnects the protocol logic blocks and the at least one crossbar switch to one another.

Abstract: The present invention pertains to a configurable PCI-Express switch. The configurable PCI-Express switch includes a differential I/O interface capable of being configured in a first configuration or a second configuration. In the first configuration, the differential I/O interface implements a PCI-Express interface with a coupled device. In the second configuration, the differential I/O interface implements a differential interface other than PCI-Express with the coupled device. The configurable PCI-Express switch also includes a switching unit capable of configuring the differential I/O interface in the first configuration or the second configuration.

Abstract: A protocol chip and a communication conversion circuit are provided in a channel adapter package that is in charge of communications with a host. The communication conversion circuit communicates with the protocol chip using a procedure that conforms to a communication protocol. The communication conversion circuit communicates with a microprocessor using a procedure that is common to multiple communication protocols. It appears from the microprocessor as though communications are being carried out with the same type of channel adapter package.

Abstract: A bridge circuit 10 is provided between first data port A1, A2 and second data port B1, B2. The bridge circuit comprises a first transceiver stage 40 comprising at least one input buffer 11, 14 and at least one tri-state output buffer 12, 13 linked to the first data port, a second transceiver stage 50 comprising at least one input buffer 21, 24 and at least one tri-state output buffer 12, 13 linked to the second data port, a first detection circuit 31 for detecting the arrival of a packet by the first data port, a second detection circuit 37 for detecting the arrival of a packet by the second data port. A selection circuitry 34, 35 enables the output of tri-state output buffer of the first or of the second transceiver stage depending of the detection made by the first and second detection circuits.

Abstract: A network system that is part of a main system includes: a first PCI express-network bridge with a first control unit and a first PCI express adapter terminating a first PCI express bus; and a second PCI express-network bridge connected to the first PCI express-network bridge through a network. The second PCI express-network bridge includes a second control unit and a second PCI express adapter terminating a second PCI express bus, wherein the first control unit detects a destination of a packet sent from the first PCI express adapter, searches a physical address of the destination from a packet encapsulating table, and encapsulates the packet in a frame so that the frame includes the physical address, and wherein the second control unit removes the encapsulation tagged to the packet, and transfers the packet to the destination through the second PCI express bus by referring to a PCI express configuration register.

Abstract: A method and structure(s) for providing a data path between and among nodes and processing elements within an interconnection fabric are described. More specifically, a device comprising a first circuit configured to couple between a first bus and a link is described. The circuit may be configured to operate as a bridge, support PCI configuration cycles, send outgoing information serially through the link in a format different from that of the first bus, and allow a host processor, communicating through the first bus, to selectively address one or more remote devices to which the device is configured to allow access. In some embodiments, the first circuit may support “spoof-proof” data protocols, and the device may operate in multiple modes including root bridge, leaf bridge, and gateway mode. Multiple addressing models may also be used.

Abstract: Disclosed are methods and devices, among which is a device including a self-selecting bus decoder. In some embodiments, the device may be coupled to a microcontroller, and the self-selecting bus decoder may determine a response of the peripheral device to requests from the microcontroller. In another embodiment, the device may include a bus translator and a self-selecting bus decoder. The bus translator may be configured to translate between signals from a selected one of a plurality of different types of buses. A microcontroller may be coupled to a selected one of the plurality of different types of buses of the bus translator.

Abstract: Interface adapter systems and methods are provided. An adapter means can be provided for coupling a first interface to a second interface, the second interface configured to accommodate the coupling of a peripheral device. A detector means can be provided for detecting the peripheral device. A means can be provided for communicating a first signal to a first bus when the peripheral device is not detected. A converting means can be provided to convert a first signal to a second signal having a protocol different than the first and a communications means for communicating the second signal to a second bus can be provided when the detecting means has detected the peripheral device.

Abstract: A data diode comprises a USB input port coupled to a first USB to RS422 converter, which is coupled to a first serial port. A second serial port is coupled to a second USB to RS422 converter, which is coupled to a USB output port. The TX-pin of the first serial port is connected to the RX-pin of the second serial port and the TX+ pin of the first serial port is connected to the RX+ pin of the second serial port. The TX ports of the second serial port are not connected to the RX ports of the first serial port, thereby preventing reverse data flow.

Abstract: A remote control system for a vehicle of a type including a data communications bus extending throughout the vehicle and connecting a plurality of vehicle devices within the vehicle may include a remote transmitter and a vehicle remote function controller being responsive to the remote transmitter. The vehicle remote function controller may include a controller data link interface. The remote control system may include a multi-controller data bus adaptor for adapting the vehicle remote function controller to communicate via the data communications bus and may include an adaptor data link interface coupled to the controller data link interface. The multi-controller data bus adaptor may be operable with a given set of controller codes for the vehicle remote controller from among a plurality of different sets of controller codes for a plurality of different vehicle function controllers.

Abstract: An integrated transmission circuit and method for transmitting output data to a chipset via a transmission interface are provided. The integrated transmission circuit includes a first application circuit, a second application circuit, a media access control (MAC) circuit, and a physical layer (PHY) circuit. The first application circuit is used for receiving and processing first data to output first processed data. The second application circuit is used for receiving and processing second data to output second processed data. The MAC circuit is coupled to the first application circuit and the second application circuit, and used for encoding the first processed data and the second processed data so as to output encoded data. The PHY circuit is coupled to the MAC circuit to receive the encoded data so as to output the output data to the transmission interface.

Abstract: Mechanisms are provided for implementing a multi-root PCI manager (MR-PCIM) in a multi-root I/O virtualization management partition (MR-IMP) to control the shared functionality of an multi-root I/O virtualization (IOV) enabled switch fabric and multi-root IOV enabled I/O adapter (IOA) through the base functions (BF) of the switches and IOAs. A hypervisor provides device-independent facilities to the code running in the I/O Virtualization Management Partition (IMP), Multi-Root (MR)-IMP and client partitions. The MR-IMP may include device specific code without the hypervisor needing to sacrifice its size, robustness, and upgradeability. The hypervisor provides the virtual intermediary functionally for the sharing and control of the switch and IOA's control functions.

Abstract: A data storage apparatus having improved data transfer performance. The storage apparatus has: plural controllers connected to each other by first data transfer paths; plural processors controlling the controllers; and second data transfer paths through which the controllers send data to various devices. Each of the controllers has a data-processing portion for transferring data to the first and second data transfer paths. The data-processing portion has a header detection portion for detecting first header information constituting data, a selection portion for selecting data sets having continuous addresses of transfer destination and using the same data transfer path from plural data sets such that a coupled data set is created from the selected data sets, a header creation portion for creating second header information about the coupled data set, and coupled data creation means for creating the coupled data set from the selected data sets and from the second header information.

Abstract: A memory system includes a selection element for selecting a selectable access rate from a plurality of access rates and a memory element for providing or for accepting data at the selectable access rate.

Abstract: A multi-protocol memory controller includes one or more memory channel controllers. Each of the memory channel controllers coupled to a single channel of DIMM, where the DIMM in each single channel operate according to a specific protocol. A protocol engine is coupled to the memory channel controllers. The protocol engine is configurable to accommodate one or more of the specific protocols. Finally, a system interface is coupled to the protocol engine and is configurable to provide electrical power and signaling appropriate for the specific protocols.

Abstract: In order to provide an inexpensive way to share an I/O device loaded in an I/O drawer among a plurality of blades, in a server system including a plurality of servers, a PCI device, and a manager for initializing a PCI switch, the PCI device has a plurality of virtual functions (VFs). The PCI switch, which has VF allocation information which indicates association between the servers and the VFs, is configured to: receive a transaction from one of the servers or from the PCI device; when the received transaction is a transaction sent from the one of the servers, remove a server identifier with which a sender server is identified and transfer the received transaction to the PCI device; and when the received transaction is a transaction sent from the PCI device, attach a server identifier that is determined based on the VF allocation information.

Abstract: A host controller having a first communication interface, or protocol, writes to and reads from one or more slave devices each having a second communication interface, or protocol, which is different from the first, through a translation device, or integrated circuit, that is responsive to command streams from the host controller. The present invention provides a high-level communications protocol by which command information and data are passed to a translation device, and the translation device interprets these commands and engages in the desired data transfer operation between the host controller and the slave devices. In a further aspect of the present invention, the high-level communications protocol also includes commands interpreted by the translation device to achieve data transfers between the host controller and the translation device, including accessing internal registers and I/O ports of the translation device.

Abstract: To provide a data processing device in which a plurality of CPUs can individually and independently communicate with different functions of a USB device using a single communication path. The data processing device is configured so that a USB host module to be coupled to a plurality of central processing units has a plurality of pipes to communicate with an arbitrary end point of a USB device coupled from the outside of the data processing device, the data processing device also includes an access control register to specify which central processing unit should have a right to control the pipe and specify to which extent a range of the content of setting of a function for the pipe should be allowed, and a USB host interface is controlled in accordance with the content of setting of the access control register.

Abstract: Example apparatus and methods to communicatively couple field devices to controllers in a process control system are disclosed. A disclosed example apparatus includes a first interface configured to receive first information from a field device using a first communication protocol. The example apparatus also includes a communication processor communicatively coupled to the first interface and configured to encode the first information for communication via a bus using a second communication protocol. In addition, the example apparatus includes a second interface communicatively coupled to the communication processor and the bus and configured to communicate the first information via the bus using the second communication protocol. The bus is configured to use the second communication protocol to communicate second information associated with another field device.

Abstract: A USB device includes: a communication section that is capable of wirelessly communicating with a communication device that supports a predetermined communication standard; a USB communication section that is capable of communicating with a USB host device; and a connection section that, when a connection to the communication device is requested under the condition that a connection to the USB host device is requested, determines whether or not a protocol supported by the communication device is any of multiple protocols, and establishes the connection to the USB host device through the USB communication section using a device class corresponding to the determined protocol.

Abstract: A method and controller for implementing device physical location identification in a Serial Attached SCSI (SAS) fabric using resource path groups, and a design structure on which the subject controller circuit resides are provided. The device physical location identification includes a Resource Path Group (RPG). Each RPG provides a unique persistent physical locator of a storage device in the system. Each RPG including at least two Resource Paths (RPs) and each RP has a fixed size identifying a type and a series of egress ports. A persistent RPG is stored within the device metadata on the storage device.

Abstract: An information system includes a configuration controller board having a capability to set, to each I/O bus bridge device in the alternative I/O board, the logical bus number set in corresponding I/O bus bridge device in the failed I/O board 20, and to set to the I/O has bridge device in the system board 10 connected with the alternative I/O board, the same downstream side logical bus number as that of the I/O bas bridge device in the system board connected with the failed I/O board.

Abstract: The invention provides an electronic apparatus. In one embodiment, the electronic apparatus comprises a motherboard, a Universal Serial Bus (USB) 3.0 module, and a Peripheral Component Interconnect Express (PCIe) interface. The motherboard comprises a host chip and a power supply module. The USB 3.0 module comprises a USB 3.0 controller chip and a USB 3.0 connector, wherein a USB 3.0 connector is located on a front panel of the electronic apparatus. The PCIe interface couples the USB 3.0 module with the motherboard, transmits a set of PCIe signals between the host chip and the USB 3.0 controller chip, and sends a power generated by the power supply module to the USB 3.0 controller chip and the USB 3.0 connector.

Abstract: A single USB-to-IDE adapter (204) connects two or more IDE devices (208, 210, 212) to a USB apparatus (202). The USB apparatus (202) communicates with each IDE device using a connection identifier associated with the USB connection (206) and a unique identifier associated with each IDE connection (214, 216, 218). The USB-to-IDE adapter (204) may be integrated within the USB apparatus (202) or as a discrete component connected to the USB apparatus (202).

Abstract: A network protocol unit interface is described that uses a message engine to transfer contents of received network protocol units in message segments to a destination message engine. The network protocol unit interface uses a message engine to receive messages whose content is to be transmitted in network protocol units. A message engine transmits message segments to a destination message engine without the message engine transmitter and receiver sharing memory space. In addition, the transmitter message engine can transmit message segments to a receiver message engine by use of a virtual address associated with the receiver message and a queue identifier, as opposed to a memory address.

Abstract: A host device and an accessory exchange information (e.g., commands and data) via an intermediate device. The host device and accessory can each connect to the intermediate device through a direct wired path and can exchange commands and data with the intermediate device. The host device and the accessory can also “tunnel” information to each other through the intermediate device, by packaging the tunneled information as a payload of a command recognizable by the intermediate device; the intermediate device can repackage and forward the payload. In some embodiments, the tunneled information relates to configuring a wireless link (e.g., a Bluetooth pairing) between the host device and the accessory.

Abstract: There is provided an interface card system for SD bus control. The interface card system for SD bus control includes a CPU bus interface 11a and/or an SD bus interface 11b, a host interface module 16 connected to the interfaces which interprets an SD command and controls operation of the whole of the interface card system, first and second internal SD host engines 15a and 15b which function as a host controller, first and second selectors 14a and 14b respectively connected to the internal SD host engines which each select a path for data or a command, first and second SD bus interfaces 13a and 13b respectively connected to the selectors, and a data pass-through control section 17 connected to the SD bus interfaces connected to the selectors which allows an SD command and data to pass through.

Abstract: A bridge includes a host interface via which data/commands are received from and transferred to a host, and a storage device interface via which data/commands are received from and transferred to a storage device. The bridge also includes one SDPC, a controller and a switching system that is configurable by the controller to connect the protocol converter to the host interface and the storage device interface if the storage device protocol used by the host device differs from the storage device protocol used by the storage device, and to connect the host device interface to the storage device interface, not via the bi-directional protocol converter, if the two storage device protocols are the same. The bridge may include two SDPCs, each for converting a different protocol to the host protocol and vice versa, with the switching system being configurable to switch between the two SDPCs.

Abstract: A communication module for connecting a serial bus, which transmits data in packets, to a plurality of system buses of a gateway, which transmit data word by word, the communication module having a communication protocol unit, which is connected to the serial bus, for converting between data packages and messages, which are respectively made up of a plurality of data words, a message relaying unit for relaying messages between at least one message memory and the communication protocol unit, as well as buffer memories, a plurality of interface units, which are respectively connected to an associated system bus of the gateway, each interface unit being connected to at least one associated buffer memory, which stores a message temporarily, a transmission of data words via a plurality of system buses and their associated interface units from and to the buffer memories of the interface units taking place simultaneously, without delay.

Abstract: A method is disclosed in which data is exchanged via a bus coupler (500) between a network (410) designed for transmitting Ethernet telegrams and a lower-level bus system (420), wherein the bus coupler (500) is connected via a first interface (520) to the network (410) and via a second interface (530) to the lower-level bus system (420), and wherein process data is read in and/or output through at least one bus node (610, 620, 630) of the lower-level bus system (420). Furthermore, a bus coupler (500), a bus node (610, 620, 630), and a control system (10) that are designed for execution of the method are disclosed.

Abstract: A storage device has two connectors for transferring data files: a first connector through which data files can be transferred at an accelerated speed, and a second connector through which data files can be transferred at a conventional speed. According to the present disclosure a user can select the speed (i.e., “normal speed” or “accelerated speed”) at which s/he wants to transfer a data file from a host to the storage device, and vice versa, by connecting the host to the proper connector of the storage device. The first connector is internally connected to a plurality of controllers that facilitate data transfers at the accelerated speed, and the second connector is internally connected to a controller that facilitates data transfers at the normal speed.

Abstract: Methods and apparatus for improved performance in communications with a SATA target device. Features and aspects hereof provide for continuing DMA transfers from a storage controller (e.g., a SATA host or a SAS/STP initiator) to a SATA target device without regard to receipt of DMA ACTIVATE Frame Information Structures (FIS). Logic to implement these features may be provided by bridge logic within an enhanced SAS expander coupled with an enhanced SAS/STP initiator or may be provided by suitable logic in an enhanced SATA host coupled directly with an enhanced SATA target device. By continuing DMA transfer of data from the initiator/host to the SATA target device without regard to receipt of a DMA ACTIVATE FIS, more of the available bandwidth of the SAS/SATA communication link may be utilized. Other standard features of the SAS/SATA protocols provide for flow control to prevent overrun of the SATA target device's buffers.

Abstract: The present invention discloses a method for processing data of a flash memory by differentiating levels, which includes steps of separating the communication between a host and a flash memory by a high-level translation layer (HTL) and a low-level abstraction layer (LAL). The HTL receives commands and logical addresses from the host and translates the received logical addresses to the physical addresses of the flash memory. The LAL executes data processing to the corresponding memory cells according to the commands and the physical addresses from the HTL. Since the LAL is disposed between the HTL and the flash memory, the HTL is irrelevant to the structure of the flash memory, and does not have to re-designed with the flash memory which is replaced with another new flash memory.

Abstract: A method for dynamically switching between different device configurations to improve the utilization of the device and save the cost. The method comprises the steps of obtaining the current configuration information of a device connected to a host; and if the current configuration of the device does not meet the requirements of the host, switching the current configuration of the device to a suitable one for the host. A system for the same is also provided to improve the utilization of the device and save the cost.

Abstract: The invention relates to smartcard under SecureMMC standard, the card being connected to a host through a MMC bus and being compliant to ISO/IEC7816 standard. According to the invention, the card is multi-application operation capable and a determined number N of commands can be processed in the card in parallel, being the number of logical channels the card can support, the card has means for using a command or a response which is encapsulated in an information field of a bloc frame, said bloc frame also having at least a prologue field for at least identifying the source node application and the destination node application in a NAD datum, and the card has means for as long as the number p of active commands in the card is lower than N and none is completed, the card is in Secure_Idle state.

Abstract: A system-on-a-chip (SOC) bridge is described that applies an adapted delay, or latency, to data transfers across the bridge to avoid data corruption without reducing data transfer performance. The adapted delay assures that a source SOC service device transferring data to a destination SOC service device via the bridge and an SOC crossbar bus does not prematurely assume that the data transfer is complete upon transferring the data to the bridge. The bridge causes wait states to be inserted into the transfer between the source SOC service device and the SOC bridge until the SOC bridge receives confirmation that the data has arrived at the destination SOC service device. The adapted delay assures that subsequent operations are not prematurely initiated by the source SOC service device and/or the SOC CPU that may interfere with the data transfer from the SOC bridge to the destination SOC service device, resulting in corrupted data.

Abstract: An external bridge system includes a host interface, a first device interface and a second device interface, which uses a communication protocol different from that of the first device interface. A bridge controller translates signals compliant with the communication protocol of a host to or from signals compliant with the communication protocol of the first or second device.

Abstract: Mechanisms for providing a memory region/memory window (MR/MW) access notification on a system area network are provided. Whenever a previously allocated MR/MW is accessed, such as via a remote direct memory access (RDMA) read/write operation, a notification of the access is generated and written to a queue data structure associated with the MR/MW. In one illustrative embodiment, this queue data structure may be a MR/MW event queue (EQ) data structure that is created and used for all consumer processes and all MR/MWs. In other illustrative embodiments, the EQ is associated with a protection domain. In yet another illustrative embodiment, an event record may be posted to an asynchronous event handler in response to the accessing of the MR/MW. In another illustrative embodiment, a previously posted queue element may be used to generate a completion queue element in response to the accessing of the MR/MW.

Abstract: A system including a serialized secondary bus architecture. The system may include an LPC bus, an I/O controller, a serialized secondary bus, and at least one slave device. The LPC bus may be connected to the I/O controller, and the at least one slave device may be connected to the I/O controller via the serialized secondary bus. The serialized secondary bus has a reduced pin count relative to the LPC bus. The I/O controller may receive bus transactions from the LPC bus. The I/O controller may translate and forward LPC bus transactions to the at least one device over the secondary bus. The I/O controller may include a processing unit. The processing unit may initiate bus transactions intended for the at least one slave device. The I/O controller may also include a bus arbitration unit. The bus arbitration unit may arbitrate ownership of the secondary bus between the processing unit and the LPC bus.

Abstract: A host device and an accessory exchange information (e.g., commands and data) via an intermediate device. The host device and accessory can each connect to the intermediate device through a direct wired path and can exchange commands and data with the intermediate device. The host device and the accessory can also “tunnel” information to each other through the intermediate device, by packaging the tunneled information as a payload of a command recognizable by the intermediate device; the intermediate device can repackage and forward the payload. In some embodiments, the tunneled information relates to configuring a wireless link (e.g., a Bluetooth pairing) between the host device and the accessory.

Abstract: A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system.

Abstract: A memory expansion blade for a multi-protocol architecture, includes dual inline memory modules (DIMMs) and a multi-protocol memory controller coupled to the DIMMs and operable to control operations of the DIMMs. The multi-protocol memory controller includes one or more memory channel controllers, with each of the memory channel controllers coupled to a single channel of DIMM, and where the DIMM in each single channel operate according to a specific protocol. The controller further includes a protocol engine coupled to the memory channel controllers, where the protocol engine is configurable to accommodate one or more of the specific protocols, and a system interface coupled to the protocol engine and configurable to provide electrical power and signaling appropriate for the specific protocols.

Abstract: A telecommunications system and constituent two-wire interface module. The two-wire interface module includes a first two-wire interface component configured to receive a first two-wire interface communication following a first two-wire interface protocol, and a second two-wire interface component configured to generate a second two-wire interface communication following a second two-wire interface protocol. The first and second two-wire interface communications each include a header portion and a payload portion. The second two-wire interface component is further configured to use one or more of the data fields from the payload portion of the first two-wire interface communication in the header portion of the second two-wire interface communication.

Abstract: A mechanism for facilitating configuration of port-type Peripheral Component Interconnect Express/Serial Advanced Technology Attachment host controller architecture is described. In one embodiment, an apparatus includes a plurality of PHYs to be used as Peripheral Component Interconnect Express (PCIe) ports and Serial Advanced Technology Attachment (SATA) ports, and logic to facilitate swapping of one or more of the plurality of PHYs between being the PCIe ports and the SATA ports.

Abstract: In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.

Abstract: A multiple processor device generates a control packet for at least one connectionless-based packet in partial accordance with a control packet format of the connection-based point-to-point link and partially not in accordance with the control packet format. For instance, the multiple processor device generates the control packet to include, in noncompliance with the control packet format, one or more of an indication that at least one connectionless-based packet is being transported, an indication of a virtual channel of a plurality of virtual channels associated with the at least one connectionless-based packet, an indication of an amount of data included in the associated data packet, status of the at least one connectionless-based packet, and an error status indication.