Abstract: The present invention relates to a composite data transmission interface and a judgment method thereof which is based on metal contacts shared by a smart card and a USB and comprise steps as follows: link a composite pin to a socket; electrical conductivity is completed with a socket linking a composite pin; a controller connected to the composite pin is activated by electricity; a smart card's or a USB's electrical conductivity mode is enabled by the controller by means of the smart card's or the USB's electrical connection mode.

Abstract: PCIe devices and corresponding methods are provided wherein a length of data to be transferred is aligned to a multiple of a double word length.

Abstract: An intelligent serial interface circuit in accordance with one embodiment of the invention can include a first communication interface circuit for enabling a first communication protocol. The intelligent serial interface circuit can also include a second communication interface circuit for enabling a second communication protocol. Furthermore, the intelligent serial interface circuit can include a detector circuit coupled to the first communication interface circuit and the second communication interface circuit. The detector circuit can be for automatically detecting a factor that indicates automatically enabling the first communication interface circuit and automatically disabling the second communication interface circuit. The detector circuit can be for detecting a coupling of a pin of the first communication interface circuit that is not used by the second communication interface circuit.

Abstract: A memory system controller includes one or more sockets for accommodating NVDIMM cards produced by different NVDIMM providers; a PCIe interface for coupling the memory system controller to a host; and a controller coupled to the PCIe interface over a PCIe-compliant connection and to the one or more sockets over respective DDR2 connections. The controller is configured to manage data transfers between the host and a specified one of the NVDIMM sockets in which an NVDIMM card is accommodated as DMA reads and writes, format data received from the PCIe interface for transmission to the specified NVDIMM socket over the corresponding one or more DDR2 interfaces, and initiate save and restore operations on the NVDIMM card accommodated within the specified NVDIMM socket in response to power failure and power restoration indications.

Abstract: Described embodiments provide a system having a bridge for connecting two different processor buses. The bridge receives a request from a first bus, the request having an identification field having a value. The request is then entered into one of a plurality of buffers having requests therein with the same identification field values. Which buffer receives the request may be based on a variety of techniques, such as random, least recently used, most full, prioritized, or sequential. Next, the buffered request is transmitted over a second bus. A response to the request is eventually received from the second bus, the response is transmitted over the first bus, and the request is then removed from the buffer. By entering the received request to the buffer with request with the same identification value, there is a reduced possibility of head-of-line request blocking when compared to a single buffer implementation.

Abstract: A method and apparatus for a configurable packet routing, buffering and scheduling scheme to optimize throughput with deadlock prevention in SRIO-to-PCIe Bridges have been described. A single level enqueue method with dynamic buffering and dequeuing based on packet re-ordering is disclosed. Single level packet routing and scheduling to meet SRIO and PCIe rules to enqueue packets based on FType/TType is disclosed. Backpressure based on ingress watermarks for different packet types is disclosed. Use of a circular-reorder queue (CRQ) for both ingress and egress allows packet reordering and packet passing.

Abstract: An embodiment integrates non-PCI compliant devices with PCI compliant operating systems. A fabric system mimics the behavior of PCI. When non-PCI compliant devices do not know how to respond to PCI enumeration, embodiments provide a PCI enumeration reply and thus emulate a reply that would typically come from a PCI compliant device during emulation. Embodiments allow system designers to incorporate non-standard fabric structures with the benefit of still using robust and mature PCI infrastructure found in modem PCI compliant operating systems. More generally, embodiments allow an operating system compliant with a first standard (but not a second standard) to discover and communicate with a device that is non-compliant with the first standard (but possibly is compliant with the second standard). Other embodiments are described herein.

Abstract: Disclosed herein is a system having a multi-processor configuration for electronics devices and systems, such as, computing and communication devices like laptop, notebook, tablets, smartphones, etc. In accordance with one embodiment of the subject matter the system comprises a plurality of processors and a multi protocol multi-root input output virtualization (MPMRIOV) switch communicatively coupled to at least one of the plurality of processors. The system further includes a peripheral and interface virtualization unit (PIVU) coupled to the MPMRIOV switch. In said embodiment, the PIVU is configured to communicatively couple at least one of the plurality of processors with at least one of a Peripheral Component Interconnect (PCI) compliant peripheral, a Peripheral Component Interconnect express (PCIe) compliant peripheral, a non PCI compliant peripheral, and a non PCIe compliant peripheral.

Abstract: A connector for communication contains a connecting section, which is connected to communication line; and a network controller, which is connected internally to the connecting section, interprets a designated protocol and controls communication; and a transceiver, which makes possible transmission and receipt on the physical layer of the communication line.

Abstract: A solution is presented to securing endpoints without the need for a separate bus or communication path. The solution allows for controlling access to endpoints by utilizing a management protocol by overlapping with existing interconnect communication paths in a packet format and utilizing a PCI address BDF (Bus number, Device number, and Function number) for verification.

Abstract: A device for transmitting multiple control formats from an audio/video source to an audio/video monitor receiver. The device includes a high definition multimedia interface cable that has a plurality of communication channels, including a consumer electronic control channel. Furthermore, a pair of plugs are coupled to the respective ends of the high definition multimedia interface cable and can be coupled to audio/video sources and receivers. A pair of interface ports are further coupled to the high definition multimedia interface cable and communicatively coupled to the consumer electronic control channel. The device transmits a first control format on the consumer electronic control channel when the input port is not coupled to a switching device and transmits a second control format on the consumer electronic control channel when the input port is coupled to a switching device.

Abstract: Embodiments of the invention relate to optimizing EDRAM refresh rates in a high performance cache architecture. A request is received from a requester to perform an operation on an I/O adapters. It is determined if the request is in a format other than a format supported by an I/O bus and if, the requester requires a completion response for the request. The request is transformed into the format supported by the I/O bus and is transmitted to the I/O adapter. The completion response is received from the I/O adapter, and includes an indicator that the request has been completed. The completion response is in the format supported by the I/O bus and is transmitted to the requester.

Abstract: A serial peripheral interface (SPI) system including a bus adapter is disclosed. The bus adapter may include a data converter that may be adapted to receive respective first and second data from a first master output peripheral input (MOPI) line and a chip select line from a SPI master device. The data converter may also be adapted to interleave the first and second data, and the data converter may be adapted to transmit the interleaved first and second data synchronously with a second clock signal on a second MOPI line. The bus adapter may also include a clock rate adjuster adapted to generate the second clock signal to transmit to a SPI peripheral device. The second clock signal may be adapted to enable the SPI peripheral device to read the transmitted data.

Abstract: Methods and apparatus for tunneling platform management messages through inter-processor interconnects. Platform management messages are received from a management entity such as a management engine (ME) at a management component of a first processor targeted for a managed device operatively coupled to a second processor. Management message content is encapsulated in a tunnel message that is tunneled from the first processor to a second management component in the second processor via a socket-to-socket interconnect link between the processors. Once received at the second management component the encapsulated management message content is extracted and the original management message is recreated. The recreated management message is then used to manage the targeted device in a manner similar to if the ME was directly connected to the second processor. The disclosed techniques enable management of platform devices operatively coupled to processors in a multi-processor platform via a single management entity.

Abstract: A method, device and computer program product for providing multi-protocol communication on an inter-integrated circuit (I2C) bus. The method for providing multi-protocol communication on an inter-integrated circuit (I2C) bus can include issuing a start command by a bus management device onto the I2C bus. Thereafter, the bus management device can send an embedded differential protocol to a non-I2C device. Once communication with the non-I2C device is completed, the bus management device can issue a stop command to release the I2C bus. In one aspect of this embodiment, the method can include receiving a response from the non-I2C device.

Abstract: Certain aspects direct to data transfer between a baseboard management controller (BMC) and a host computer. When the BMC is connected to the host computer via a universal serial bus (USB) interface, the BMC sends USB descriptors to the host computer such that the host computer recognizes the BMC as a specific human interface device (HID) device based on the USB descriptors. To transfer data to the host computer, the BMC converts the data to an Intelligent Platform Management Interface (IPMI) message, and generates a USB HID report containing the IPMI message as the report data. The BMC then sends the USB HID report to the host computer through the USB interface. When the BMC receives a USB HID report from the host computer, the BMC retrieves the report data, which is an IPMI message, from the USB HID report, and process the IPMI message to obtain the data.

Abstract: A processing system is disclosed. The processing system comprises a first integrated circuit. The first integrated circuit includes a processor core, a display interface and memory controller coupled to a first bus interface. The display interface is adapted to display graphical information generated by a graphics engine. A graphics engine is not on the first integrated circuit. The processing system includes a second bus interface for allowing communication with the first integrated circuit via the first bus interface. The second bus interface is adapted to allow for communication to a graphics engine.

Abstract: An adapter facilitates communications between an accessory and a media source. When the adapter is connected to the accessory, the adapter can receive a connection request from the media source. Based on the connection request, the adapter can determine whether the media source supports an accessory protocol. The adapter can receive streamed media from the media source. When a control message is received by the adapter from the accessory, if the adapter determined that the media source supports the accessory protocol, the adapter transmits the control message to the media source using the accessory protocol. If the adapter determined that the media source does not support the accessory protocol, the adapter translates the control message and transmits the translated message to the media source.

Abstract: A mechanism for facilitating configuration of port-type Peripheral Component Interconnect Express/Serial Advanced Technology Attachment host controller architecture is described. In one embodiment, an apparatus includes a plurality of PHYs to be used as Peripheral Component Interconnect Express (PCIe) ports and Serial Advanced Technology Attachment (SATA) ports, and logic to facilitate swapping of one or more of the plurality of PHYs between being the PCIe ports and the SATA ports.

Abstract: The present invention relates to an improved USB connection cable, comprising: a first electrical connector, a second electrical connector and a third electrical connector, wherein the first electrical connector is used for connecting to a host computer, the second electrical connector is adopted for connecting to a first electronic device, and the third electrical connector is adopted for connecting to a second electronic device; Moreover, by way of electrically connecting the internal pins of the first USB electrical connector to the internal pins of the second USB electrical connector and the third USB electrical connector, the first USB electrical connector is able to transmit data to the second USB electrical connector and the third USB electrical connector, respectively; such that the improved USB connection cable can not be a media for data transfer used between the electronic device having an USB 3.0 electrical connector and the host computer with an USB 3.

Abstract: An information processing device including a reader unit connected through a connection switch to a first control section and a second control section. The first control section is connected to the connection switch by a first bus supporting a first specification. The second control section is connected to a conversion unit by a second bus supporting a second specification. The conversion unit is connected to the connection switch by a third bus supporting the first specification. When the connection switch connects the reader unit to the first control section, the second control section halts communication with the conversion unit, thereby avoiding unnecessary use of processing resources.

Abstract: Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A method for managing flow across the multi-protocol I/O interconnect may include providing, by a first port of a switching fabric of a multi-protocol interconnect to a second port of the switching fabric, a first credit grant packet and a second credit grant packet as indications of unoccupied space of a buffer associated with a path between the first port and a second port, and simultaneously routing a first data packet of a first protocol and a second data packet of a second protocol, different from the first protocol, on the path from the second port to the first port based at least in part on receipt by the second port of the first and second credit grant packets. Other embodiments may be described and claimed.

Abstract: A device receives a standard command. The device judges whether an address field and/or a data length field and/or a data field of the standard command includes at least one of a vendor command, a vendor data and a checkword. The device judges whether the address field and/or a data length field and/or the data field of the standard command matches a vendor predetermined pattern. If matched, the device performs a vendor operation based on the vendor command and/or the vendor data of the standard command.

Abstract: In one embodiment, a multi-protocol communication circuit is provided. The communication circuit includes a plurality of protocol bridge circuits, each configured to convert data between a first format and a respective second format corresponding to a respective communication protocol. A switch network provides routable connections between the protocol bridge circuits and one or more interface circuits. Each interface circuit is configured to convert data between the first format and a raw data format. Due to the common first format, an interface circuit may be configured for select ones of different communication protocols by routing data in the first format between the interface circuit and a protocol bridge circuit corresponding to the select one of the different communication protocols.

Abstract: A communication system having one CAN bus and at least two devices interconnected by the CAN bus is described, at least one of the devices including: i) a CAN controller, which is suitable for transmitting CAN data frames over the CAN bus using a first physical protocol in a first operating mode; ii) an asynchronous serial communication interface unit, which is suitable for transmitting ASC data frames over the CAN bus using a second physical protocol in a second operating mode; iii) a first switching means, which is suitable for switching the first operating mode and the second operating mode depending on at least one agreement in effect between the device and at least one of the other devices; and iv) another switching means, which is suitable for switching the device to a third (restricted) operating mode, which differs from the first operating mode and the second operating mode, for powering up the device.

Abstract: An apparatus including a plurality of internal devices that communicates concurrently with a controller by one of the MDIO protocol and the SPI protocol is disclosed. The controller of the invention couples with respective devices by the point-to-point arrangement. The controller couples with the external apparatus by the MDIO protocol and receives a packet containing an address of one of internal devices, the controller communicates with the device defined by the address by the protocol attributed to the device.

Abstract: The subject disclosure pertains to transparent communications in an industrial automation environment amongst automation system components and IT systems. Systems and methods are provided that send and receive data to, from and amongst automation devices and transactional based IT systems. The system is viewed as a control system to the automation device and as a transactional system to the IT system. Accordingly, it is not necessary to provide a custom interface between automation devices and the IT systems.

Abstract: A communication gateway apparatus for a substation automation system, the gateway includes a VERSA Module Eurocard (VME) bus to provide a data communication path, a Peripheral Component Interconnect (PCI)-VME module connected to the VME bus for communication and having a PCI-VME bus bridge circuit to transfer data of the VME bus to a PCI bus or data of the PCI bus to the VME bus, and a plurality of input/output modules connected to the VME bus for communication.

Abstract: Methods and apparatus for implementing a port management protocol which can be used to manage communication between one or more USB devices and a USB host at a distance greater than that allowed by the USB Specifications are provided. In one aspect, a method for prolonging a bus event of a USB device at least until a notification is received that a corresponding bus event has been completed by the USB host is provided; and subsequently exchanging bus traffic between the USB host and USB device upon completion of the bus event by both devices.

Abstract: Methods and apparatus relating to increase Input Output Hubs in constrained link based multi-processor systems are described. In one embodiment, a first input output hub (IOH) and a second IOH are coupled a link interconnect and a plurality of processors, coupled to the first and second IOHs include pre-allocated resources for a single IOH. Other embodiments are also disclosed and claimed.

Abstract: An expansion card and method for controlling a radio system integrates PCDD operations into a PCMCIA or ExpressCard which can be inserted into an external display, smart screen PCMCIA slot, or laptop ExpressCard or PCMCIA slot to allow an operator to control the radio system with a computer without any modification of the computer.

Abstract: An indication of a version of a firmware stored in an input/output adapter may be provided by a method that includes detecting whether a first pin is connected to an external circuit, detecting whether a second pin is unconnected to an external circuit, and causing the indication to be provided if the first pin is connected and the second pin is unconnected. The indication may be provided on the first pin. The first pin may include a power supply pin and the indication may be an average rate of power supplied to the input/output adapter.

Abstract: Embodiments of the invention relate to non-standard I/O adapters in a standardized input/output (I/O) architecture. An aspect of the invention includes initiating a first request to perform an operation on a host system. The first request formatted for a first protocol and including data required to process the first request. A second request is created responsive to the first request, the second request including a header and is formatted according to the second protocol. The creating includes storing the data required to process the first request in the header of the second request. The second request is sent to the host system.

Abstract: The present invention provides a method and apparatus for controlling the operating condition of a peripheral device based on the mode of interconnection of the peripheral device of a host device. The apparatus includes a first connector for connecting the peripheral device, a second connector for connecting the host device and a coupling system operatively interconnecting contacts of the first connector and contacts of the second connector. The coupling system is further configured to provide a supply signal to the peripheral device via the first connector, wherein the supply signal is at least in part indicative of one or more characteristics of the power available to the peripheral device from the host device. The supply signal may provide a means for the peripheral device to control operation thereof in light of the characteristics of the power available.

Abstract: A disclosed example system includes a termination panel, and a shared bus on the termination panel. The shared bus is to removably receive a plurality of bases that removably receive modules to communicate with field devices, and communicatively couple the modules to an input/output card to exchange communications between the modules and a controller that is in communication with the input/output card via a second bus.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: A network protocol unit interface is described that uses a message engine to transfer contents of received network protocol units in message segments to a destination message engine. The network protocol unit interface uses a message engine to receive messages whose content is to be transmitted in network protocol units. A message engine transmits message segments to a destination message engine without the message engine transmitter and receiver sharing memory space. In addition, the transmitter message engine can transmit message segments to a receiver message engine by use of a virtual address associated with the receiver message and a queue identifier, as opposed to a memory address.

Abstract: An information handling system includes a processing node, an input/output (I/O) module coupled to the processing node via a high bandwidth interface, and a service processor coupled to the I/O module via a multi-master interface. A transaction between the processing node and the service processor that is targeted to a low pin count (LPC) bus is executed between the processing node and the service processor via the high bandwidth interface and the multi-master interface.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: A USB-to-SDIO bridge (UTSB) to efficiently transmit SD/SDIO commands in USB packets. The UTSB may allow the majority of the device drivers for a given SD/SDIO device to remain intact, requiring changes only in the lowest hardware adaptation layer to put a USB wrapper around native SD commands. These commands may be sent over USB-to-SD card reader devices that may include various embodiments of a UTSB, where they may be unwrapped and transmitted to the SD port as if the port were native to the host controller. Additionally, the SD/SDIO commands may be packaged into groups of commands, or transactions, to optimize performance. The host driver may instruct the UTSB bridge device to repeatedly read data from the SDIO device until a communications FIFO on the device is empty (corresponding to a termination condition), and return the collected data to the host.

Abstract: A system for implementing non-standard input/output (I/O) adapters in a standardized I/O architecture, comprising an I/O hub communicatively coupled to an I/O bus and a plurality of I/O adapters at I/O adapter addresses, the I/O hub including logic for implementing a method comprising receiving requests from the plurality of I/O adapters, storing the I/O adapter addresses of a requester along with their corresponding target recipient addresses and operation codes, receiving a response from a responder, the response indicating that a request has been completed, determining that the response is in a format other than a format supported by the I/O bus, transforming the response into the format supported by the I/O bus, locating a stored I/O adapter address having a corresponding target recipient address that matches the responder address and a corresponding operation code that matches the responder operation code, and transmitting the response to the stored I/O adapter address.

Abstract: A disclosed example apparatus includes a termination panel, a shared bus on the termination panel, and a plurality of bases on the termination panel along the shared bus. Each of the bases is to removably receive modules that are to communicate with field devices. Each of the bases includes first and second physical interfaces. The first physical interface is to be communicatively coupled to different types of the field devices and to exchange communications with one or more of the field devices via a plurality of different communication protocols. The second physical interface is to communicatively couple the removably receivable modules to the shared bus to communicate with a controller via the shared bus.

Abstract: In one embodiment, a converged protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to provide for data transfer across a physical interconnect. This stack can be incorporated in an apparatus that includes a protocol stack for a first communication protocol including transaction and link layers, and a physical (PHY) unit coupled to the protocol stack to provide communication between the apparatus and a device coupled to the apparatus via a physical link. This PHY unit may include a physical unit circuit according to the second communication protocol. Other embodiments are described and claimed.

Abstract: Structures and methods are disclosed relating to a multi-protocol transceiver including lane-based Physical Coding Sublayer (“PCS”) circuitry that is configurable to adapt to one of a plurality of communication protocols. Particular embodiments of the present invention include lane based configurable data paths through PCS transmit and receive circuitry.

Abstract: A structure for transmitting signals of PCI express and a method thereof provides a converting device and a high-definition multimedia interface (HDMI) cable. The converting device has a plug connector to into a PCI express slot, along with a HDMI connector. The signal converting circuit connects the signal pins of the PCI express slot to the signal pins of HDMI connector. One end of the HDMI cable is connected with the HDMI connector of the converting device. The present invention can extends the signal distance of the PCI express to exactly perform the signal test.

Abstract: In order to provide an inexpensive way to share an I/O device loaded in an I/O drawer among a plurality of blades, in a server system including a plurality of servers, a PCI device, and a manager for initializing a PCI switch, the PCI device has a plurality of virtual functions (VFs). The PCI switch, which has VF allocation information which indicates association between the servers and the VFs, is configured to: receive a transaction from one of the servers or from the PCI device; when the received transaction is a transaction sent from the one of the servers, remove a server identifier with which a sender server is identified and transfer the received transaction to the PCI device; and when the received transaction is a transaction sent from the PCI device, attach a server identifier that is determined based on the VF allocation information.

Abstract: Disclosed is an approach for configuring devices for a multiprocessor system, where the devices pertaining to the different processors are viewed as connecting to a standardized common bus. Regardless of the specific processor to which a device is directly connected, that device can be generally identified and accessed along the standardized common bus. PCIe is an example of a suitable standardized bus type that can be employed, where the devices for each processor node are represented as PCIe devices. Therefore, each of the devices would appear to the system software as a PCIe device. A PCIe controller can then be used to access the device by referring to the appropriate device identifier. This permits any device to be accessed on any of the processor nodes, without separate and individualized configurations or drivers for each separate processor node.

Abstract: An electronic Input/Output Interface and device abstraction system used in gaming machines includes: a game central processing unit (game “CPU”); an intelligent input/output controller board (“IOCB”); an Industry Standard Architecture PC bus (“ISA” bus); and a framed message transport protocol. The IOCB facilitates communications between the game CPU and virtual device services, which are peripheral devices associated with the gaming system. The game CPU communicates to gaming peripherals by sending virtual device messages across the ISA bus to the IOCB. The IOCB routes virtual device messages to appropriate virtual device services. Virtual device services are responsible for handling specific hardware, and include virtual device drivers on the game CPU that communicate with virtual devices on the IOCB. Use of the IOCB and the high speed interface enables the game CPU to use more of its available functions for controlling gaming functions rather than one operation of its associated peripheral devices.

Abstract: A host controller is suitable for transferring data in transactions, each transaction being described by a transfer descriptor, and the transactions include split transactions. The transfer descriptor for a split transaction includes a bit which may be set to indicate whether the split transaction is a start split or a complete split transaction, and, once a transaction comprising split transactions has been started by a first split transaction, subsequent split transactions are generated automatically until the transaction is complete.

Abstract: A control unit includes at least one computing device and at least one separate peripheral module which is connected to the computing device via a serial multiwire bus, the peripheral module including at least one output stage for transferring serial data to means outside of the control unit. In order to keep the number of pins required on a peripheral module to a minimum, thereby reducing costs for the entire control unit, the peripheral module has an asynchronous single-wire interface between one interface for the serial multiwire bus and the output stage. The asynchronous single-wire interface is preferably a UART (universal asynchronous receiver/transmitter) interface. The serial multiwire bus is preferably a microsecond bus.