Abstract: A timing controller provides a cable plug status detection function by receiving a reference lock signal from a graphics system connected via a constituent cable and comparing the reference lock signal to one or more reference time periods to determine the cable plug status.

Abstract: The information processing apparatus includes: a connection unit which an electronic apparatus is adapted to be communicably coupled to; a connection detecting unit which detects coupling of the electronic apparatus to the connection unit; a timer which measures a time duration that elapses under a connection state, in which the electronic apparatus is engaged; and an alerting unit which alerts a user of the information processing apparatus when it is detected by the timer that a predetermined time duration elapses. With this arrangement, it is possible to prevent forgetting to disengage the electronic apparatus from the information processing apparatus, and the convenience of handling of the electronic apparatuses is improved.

Abstract: Methods and systems for communicating information through a USB device using suspend/resume states are presented. A USB host stops transmitting Start-of-Frame (SOF) packets to a USB device, causing the USB device to enter a sleep/suspend state. The USB host then restarts the transmission of SOF packets to trigger the USB device back into a normal/resume state. The USB host repeats this process in a temporal pattern corresponding to a message, such that a circuit monitoring the USB device can determine the message.

Abstract: A method for communication via a bidirectional data link between a processing device and a memory device. The memory device includes a clock source to generate a clock signal for driving a latching at the memory device of data to and/or from the bidirectional data link. The memory device provides the clock signal to the processing device for driving a latching at the processing device of data to and/or from the bidirectional data link.

Abstract: A method according to one embodiment includes receiving a request to perform a backup of data associated with an application running on multiple servers; communicating with I/O Handlers on the servers for initiating a coordinated backup operation on the data at about a same start time; and instructing the I/O Handlers to stretch communication between instances of the application and data storage volumes associated therewith during initiating the backup operation. Additional systems, methods, and computer program products are also disclosed.

Abstract: A computer program product, an apparatus, and a method for processing communications between a control unit and a channel subsystem in an input/output processing system are provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes: sending a command from the channel subsystem to the control unit to initiate an input/output operation; setting a time period for completion of the operation; and responsive to the operation not completing within the time period, sending a message to determine whether the control unit has an exchange open for the command.

Abstract: Provided is a storage device of a serial attached small computer system interface/serial advanced technology attachment (SAS/SATA) type, which provides data storage/reading services through an SAS/SATA interface. The SAS/SATA type storage device includes: a memory disk unit which includes a plurality of memory disks provided with a plurality of volatile semiconductor memories; an SAS/SATA host interface unit which interfaces between the memory disk unit and a host; and a controller unit which adjusts synchronization of a data signal transmitted/received between the SAS/SATA host interface unit and the memory disk unit to control a data transmission/reception speed between the SAS/SATA host interface unit and the memory disk unit.

Abstract: The disclosure provides a system and a method of processing keystrokes entered on an electronic device. The method comprises: monitoring for activation of two or more keys on the keyboard; evaluating whether the activation of those keys occurs within a set window of time; evaluating locations of those keys. After these evaluations, if the keystroke conflict is determined to not have been produced then characters for those keys are generated in order of their activations. If the keystroke conflict is determined to have been produced, then the method arbitrates between those keys to select a key utilizing a dictionary to automatically determine the key to be selected. In the dictionary, its entries are related to each of those keys combined with any previously entered keystrokes. The method then processes the selected key to generate on a display one character, which is associated with the selected key.

Abstract: Methods and apparatus related to techniques for translating requests between a full speed bus and a slower speed device are described. In one embodiment, a translation logic translates requests between a full speed bus (such as a front side bus, e.g., running relatively higher frequencies, for example at MHz levels) and a much slower speed device (such as a System On Chip (SOC) device (or SOC Device Under Test (DUT)), e.g., logic provided through emulation, which may be running at much lower frequency, for example kHz levels). Other embodiments are also disclosed.

Abstract: An interface device allows data communication between a controller and a plurality of circuit units. The interface device has a first interface for a connection to the controller, a second interface for a connection to a second circuit unit, and a third interface for a connection to a second circuit unit. An interface calibrating unit is coupled to the second and third interfaces and a non-volatile calibrating parameter memory is arranged in the interface calibrating unit or coupled to the calibrating unit. The memory is adapted to store calibrating parameters for the second and third interfaces.

Abstract: The invention provides a method and apparatus for providing a synchronized multichannel universal serial bus, the method in one aspect comprising supplementing the signal channels in the USB specification to provide synchronization information from an external source, and in another aspect comprising observing USB traffic and locking a local clock signal of a USB device to a periodic signal contained in USB data traffic, wherein the locking is in respect of phase and/or frequency.

Abstract: A method, apparatus, system, and computer program product for enabling out-of-band access to storage devices through port-sharing hardware. Providing out-of-band access to storage devices enables system management functions to be performed when an operating system is non-functional as well as when the operating system is active. Storage commands originating with a management service can be interleaved with storage commands issued by the host operating system. The host operating system maintains ownership and control over its storage devices, but management activities can be performed while the host operating system is operational.

Abstract: A method for throttling in a file system. The method includes receiving a request by a client from an application to write data to a server, wherein the application is associated with an application bandwidth and wherein the server is associated with a server bandwidth, queuing a first job to write the data to the server on an I/O queue using an application-to-client throttling mechanism using at least one selected from the group of the application bandwidth and the server bandwidth, and issuing the first job from the I/O queue to the server using a client-to-server throttling mechanism and at least one selected from the group of the application bandwidth and the server bandwidth.

Abstract: Methods and systems for detecting a state of a field asset using a packet capture agent is disclosed. A method may include capturing one or more packets transmitted on a shared bus in a field asset and determining the occurrence of a door event based at least one the one or more captured packets.

Abstract: A data processing apparatus receives a communication signal that contains temporally successive bits. A programmable processor circuit executes a plurality of series of programmed instructions for operations such as parity checking, each at a time of reception of a respective one of the bits. The processor circuit suspends operation each time after executing a respective one of the series of instructions. A synchronization circuit triggers execution of respective ones of the series, each time at the time of reception of the respective one of the bits, and, except for a last one of the series, prior to reception of one or more later bits that contribute to the data word.

Abstract: A signal associated with multiple haptic effects is received, each haptic effect from the multiple haptic effects being associated with a time slot from multiple time slots. Each haptic effect from the multiple haptic effects is associated with an effect slot from multiple effect slots at least partially based on the time slot associated with that haptic effect. An output signal is sent for each effect slot from the multiple effect slots, when the associated haptic effect is scheduled for its time slot.

Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

Abstract: Disclosed are a method, upstream processing node, and computer readable medium for dynamically stabilizing a stream processing system. The method includes receiving at least one computing resource allocation target. The method further includes determining that an input data flow rate of at least one upstream processing element varies. The computing resource is dynamically allocated to the upstream processing element in response to the input rate of the upstream processing element varying. Data flow is dynamically controlled between the upstream processing element and at least one downstream processing element.

Abstract: The present invention relates to a device, system and method for controlling a data acquisition device and inserting the acquired data into the memory of an electronic device with minimal buffering of the data. An interface device, separate from the electronic device and capable of highly accurate timing, controls a data acquisition device. This interface device provides an interface between real time data and non real time operating system running on the electronic device. By sending data to a non-real time system in a near real-time manner, the non-real time system can continue the processing of the data either in near real time, or it can store the data for later processing.

Abstract: A method that includes, by one or more computer systems, determining a data retrieval rate policy based on at least one data retrieval rate parameter. The method also includes determining at least one storage subsystem performance parameter. The method further includes determining a fragmentation value based on the data retrieval rate policy and the at least one storage subsystem performance parameter. The method additionally includes determining a storage subsystem fragmentation of a first data object. The storage subsystem fragmentation includes fragmenting the first data object into a plurality of first data object fragments. The method also includes deduplicating the first data object based on the fragmentation value and the storage subsystem fragmentation.

Abstract: A timestamp neural network comprised of sensor elements, internal elements, and motor elements is responsive to timestamps. Sensor elements transform a wide variety of signals into events that trigger the updating of timestamps. Internal elements are responsive to timestamps. Motor elements convert timestamps into useful output signals. A real time video pattern recognition system is implemented.

Abstract: An apparatus comprising a control circuit, a buffer circuit and a memory. The control circuit may be configured to present a plurality of pairs of signals in response to (i) one or more input signals operating at a first data rate and (ii) an input clock signal operating at a second data rate. The second signal in each of the pairs comprises a clock signal operating at the second data rate. The buffer circuit may be configured to generate a buffered signal in response to each of the pairs of signals. Each of the buffered signals operates at the second data rate. The memory may be configured to read and write data at the second data rate in response to the buffered signals.

Abstract: In some embodiments, a method includes characterizing a plurality of channels, each of the plurality of channels being a channel between a location and a respective one of the plurality of communication interfaces; for each of the plurality of communication interfaces, supplying signals to the communication interface and detecting interference that occurs at the location as a result of emissions radiated from the plurality of communication interface while the signals are supplied thereto; for each of the plurality of communication interfaces, determining an estimate of interference that would occur at the location as a result of emissions radiated from the communication interface while the signals are supplied thereto, based at least in part on the characterization of the channel between the location and the communication interface; and for each of the plurality of communication interfaces, comparing the estimate of interference that would occur at the location to the detected interference that occurs at the

Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

Abstract: According to one embodiment, the host controller includes a transmission circuit that encodes transmission data, according to a serial transfer format, a reception circuit that decodes received data, according to the serial transfer format, a variable frequency clock generator that generates a card clock and a transfer clock, a card clock output unit that outputs the card clock to the memory card, an interface unit includes a transmission interface that transfers the transmission data from the transmission circuit to the memory card in synchronization with the transfer clock, and a reception interface that transfers received data from the memory card to the reception circuit in synchronization with the transfer clock, and a setting register circuit that holds setting information concerning an input/output method of the memory card, and controls frequency of the transfer clock generated by the variable frequency clock generator, based on the setting information.

Abstract: The present disclosure relates to performing maintenance operations in a data system using configurable parameters. In one embodiment, a method in a data system is provided. The method includes receiving an indication of a data latency threshold and performing at least one maintenance operation in the data system based on the data latency threshold.

Abstract: An electronic device is adapted to be connected to a plurality of peripheral devices, and includes a storage unit and a control circuit. The storage unit records a preset time and a control list. The control list lists at least a selected one of the electronic device and the peripheral devices, and an operation mode therefor. The control circuit detects whether the preset time matches a reference time, and if so, controls operation of the selected one of the electronic device and the peripheral devices according to settings in the control list.

Abstract: A synchronization device includes a receiver that receives data from at least two synchronization devices establishing synchronization, and extracts synchronization information and register selection information from the received data, a transmitter that transmits data to each of the at least two synchronization devices establishing synchronization among a plurality of synchronization devices, a first and a second receiving state register that each stores the extracted synchronization information, a second receiving state register that stores the extracted synchronization information, and a controller that stores the extracted synchronization information into the first receiving state register and the second receiving state register alternately based on the register selection information, and controls the transmitter to transmit data including the register selection information to each of the at least two synchronization devices when the extracted synchronization information is completed in one of the first a

Abstract: A method is described that involves detecting the presence of a pairing partner. Prior to establishing a paired relationship with the pairing partner, a user is prompted to verify himself/herself. In response to the user properly verifying himself/herself, the paring partner is paired with. The pairing includes invoking a remote storage protocol that contemplates a network between the partners to establish on a first of the partners access to non volatile storage resources for general use. The non volatile storage resources are located on a second of the partners. The second of the partners is a handheld device that provides wireless cell phone service, wireless Internet service and music playback service.

Abstract: A method of controlling an apparatus including a processor and an I/O controller includes storing execution information, receiving a first and a second requests successively, determining whether initiation of each execution of the first and the second requests is to be supervised by either of the processor and the I/O controller in reference to the execution information, transmitting the first request to the processor from the I/O controller, and upon completion of execution of the first request at the processor, transmitting the second request to the processor from the I/O controller when the initiations of executions of the first and second request is supervised by the I/O controller, and transmitting the first and second requests to the processor regardless of completion of execution of the first request by the processor when the initiations of executions of the first and second requests is supervised by the processor.

Abstract: A program disposed on a computer readable medium, having a main program with a first routine for issuing commands in an asynchronous manner and a second routine for determining whether the commands have been completed in an asynchronous manner. An auxiliary program adapts the main program to behave in a synchronous manner, by receiving control from the first routine, waiting a specified period of time with a wait routine, passing control to the second routine to determine whether any of the commands have been completed during the specified period of time, receiving control back from the second routine, and determining whether all of the commands have been completed. When all of the commands have not been completed, then the auxiliary program passes control back to the wait routine. When all of the commands have been completed, then the auxiliary program ends.

Abstract: A method for performing write transactions in an interconnect fabric is described. A burst write transaction is received by a bridge coupled to a master. The burst transaction is initiated by a command phase that includes a wait state attribute. The bridge is also coupled to a second bus that is coupled to a slave destination device or to another bridge. The bridge may initiate a cut-through transaction to the second bus when the wait state attribute indicates a master inserted wait state will not be incurred during the burst transaction.

Abstract: A networking device includes a network port configured to receive a message from a remote networking device. The network port includes a detector configured to detect reception of the message. A queue controller is configured to integrate a timestamp with the message to generate a modified message. An ingress timer is configured to generate the timestamp based on an arrival time of the message at the network port.

Abstract: A system, method, and computer readable medium. A method includes setting a maximum translation delay. The method includes, while a current delay is less than the maximum transfer delay, repeatedly performing the steps of searching for an additional transfer having a same source and target as a current transfer, and when an additional transfer is found, adding the additional transfer to a transfer list that identifies transfers to be made together. The method includes performing a transfer of the transfers identified by the transfer list when the current delay has met or exceeded the maximum transfer delay.

Abstract: Method and apparatus to control delay between lanes in an I/O interface is disclosed. To control the delay between the lanes in the I/O system a programmed delay may be determined and introduced between the lanes. For this purpose the effective time “T” of the lanes is determined. The number of lanes “N” in the I/O interface is identified. The programmed lane to lane delay “D” is determined and a delay circuit having the programmed delay may be introduced between the lanes to reduce AC peak to peak noise in the I/O system.

Abstract: The state of an input/output (I/O) operation is determined in an I/O processing system. A command is received from an I/O operating system at a channel subsystem for initiating the I/O operation, a time period is for completion of the I/O operation, and the command for initiating the I/O operation is sent from the channel subsystem to the control unit. Responsive to the time period nearing elapsing without the I/O operation completing, a cancel instruction is received from the I/O operating system at the channel subsystem. Responsive to a determination by the I/O operating system to interrogate the control unit, an instruction to interrogate the control unit is received with the cancel instruction from the I/O operating system.

Abstract: A host device is managed that communicates with a peripheral device via an interface on the basis of a high frequency clock; the host device is in a suspended state in which the high frequency clock is deactivated. At the host device, an activation state of the peripheral device is detected (21) on the interface. Then the duration of a period of time (T1) since the detection of the activation state is counted, on the basis of a low frequency clock. Then this activation state is maintained on the interface (23) by means of hardware before the period of time expires.

Abstract: Method and system a first network node communicating with a second network node using a plurality of network links grouped as a trunk is provided. The method includes determining a peak data transfer rate for the trunk during a monitoring duration; comparing the peak data transfer rate to a threshold data transfer rate for the trunk; determining if one or more of the plurality of network links can be deactivated or activated; and based on the determination, activating or deactivating one or more of the plurality of network links.

Abstract: An embodiment of the present invention is directed to a system for synchronizing independent time domain information. The synchronization of the device resource access information allows a memory access device to reliably access memory in a time domain independent of a device issuing requests. The system may synchronize device resource information for requests made by a processor to access (e.g., read/write) locations of a memory device. The present invention synchronizes the device access information without restricting pulse width of a read/write signal or requiring a high speed clock.

Abstract: An Extended Input/output (I/O) measurement word facility is provided. Provision is made for emulation of the Extended I/O measurement word facility. The facility provides for storing measurement data associated with a single I/O operation in an extended measurement word associated with an I/O response block. In a further aspect, the stored data may have a resolution of approximately one-half microsecond.

Abstract: Sample-count feedback from bus functional models and a binary convergence algorithm are to generate optimal sampling values for an accelerator, or hardware assisted simulator. The simulator includes a bus functional model and a driver program. A software readable register maintains a count of a number of samples provided the simulator in execution of a transaction on the bus functional model. For each supported bus functional model, a sample count retrieved from the bus functional model and a last sampling value given the hardware assisted simulator is maintained, and a binary convergence algorithm applied to generate sampling values based on the last sampling value given to the hardware assisted simulator and the last actual sampling value used by a given bus functional model for a transaction.

Abstract: In a communication system comprising a link layer device connectable to one or more physical layer devices, the link layer device is configured using an efficient shared architecture for processing data associated with a plurality of links including at least one ingress link and at least one egress link. The link layer device comprises an ingress data clock processor configured to generate an ingress clock signal for processing data associated with said at least one ingress link, an egress data clock processor configured to generate an egress clock signal for processing data associated with said at least one egress link, and a control and configuration unit shared by the ingress data clock processor and the egress data clock processor. Another aspect of the invention relates to a buffer adaptive processor that in an illustrative embodiment limits clock variability in the presence of cell delay variation or cell loss.

Abstract: An apparatus and method for sharing a bus in a mobile telecommunication handset are provided. In one embodiment, a mobile telecommunication handset comprises a first device, a second device, a shared bus, a memory configured to store a reference clock frequency, and a controller configured to simultaneously receive first data from the first device and transmit second data to the second device via the shared bus based on a clock signal of the reference clock frequency. The first device is configured to forward the first data received by the controller, and the second device is configured to receive the second data transmitted by the controller.

Abstract: A programmatic time-gap defect correction apparatus and method corrects errors which may go undetected by a computer system. Buffer underruns or overruns, which may incur errors in data transfers, yet remain undetected and uncorrected in a computer system, are corrected by an error avoidance module in accordance with the invention. Bytes transferred to and from buffers, used by an I/O controllers to temporarily store data while being transferred between synchronous and asynchronous devices, are counted and an error condition is forced based on the count. If the count exceeds the capacity of the buffer, an error condition is forced, thereby reducing chances that errors are incurred into the data transfer.

Abstract: A method of transmitting data on a data line between a central control device and a decentralized data processing device. During a normal operation of the system, the central control device periodically sends synchronization pulses to the at least one data processing device via the data line in order to request data packets, and the decentralized data processing device sends the data thereof to be transmitted, as data packets, to the central control device, following the synchronization pulse. The data line is embodied as a data bus. Each of the decentralized data processing devices is configured by the central control device before the first transmission of data packets to the central control device. In order to configure the system, a bi-directional communication is carried out between the central control device and the at least one decentralized data processing device.

Abstract: A method according to one embodiment includes receiving a request to perform a backup of data associated with an application running on multiple servers; calculating a time value based on communications with the servers, the time value calculation including at least one of a latency of at least one of the communications, and a difference between a reference time clock value and a time clock value of at least one of the servers; and communicating with I/O Handlers on the servers for initiating a coordinated backup operation on the data at about a same start time. Additional systems, methods, and computer program products are also disclosed.

Abstract: There is provided a data transfer method in an IEEE1394 system including a band request node and a transfer band management node. The method includes generating, at the band request node, a transfer request that can detect a data amount of transfer data and transmitting the transfer request from the band request node to the transfer band management node, determining, by the transfer band management node, whether a transfer band requested by the transfer request is ensured or not, notifying, from the transfer band management node, the band request node of the determination result, and transferring data from the band request node according to the determination result.

Abstract: A control apparatus for an input-output device includes a hardware part and a software part, in which a controller in the hardware part carries out a control operation in accordance with a signal from the input-output device, outputs a result of the control operation to a process, and has a timer unit to be excited at a constant period; and the software part has an information process part, a control process part, and an interrupt control unit to switch over the information process part and control process part one another, in which the interrupt control unit suspends an execution of the information process part to execute the control process part in priority and resume the information process part by switching over to the information process part from the control process part, when the execution of the control process part is terminated.

Abstract: A semiconductor device coupled to input/output pins includes a first core to operate a first function and a second core to operate a second function. A multiplexer is arranged to set the input/output pins to the first function or to the second function, and an arbiter is configured to receive requests from the cores to use the input/output pins and to grant use of the input/output pins to a selected core. A register is arranged to store a value indicative of a delay to be applied by the arbiter when granting use of the input/output pins to the second core.

Abstract: Illustrated is a system and method for identifying a memory page that is accessible via a common physical address, the common physical address simultaneously accessed by a hypervisor remapping the physical address to a machine address, and the physical address used as part of a DMA operation generated by an I/O device that is programmed by a VM. It also includes transmitting data associated with the memory page as part of a memory disaggregation regime, the memory disaggregation regime to include an allocation of an additional memory page, on a remote memory device, to which the data will be written. It further includes updating a P2M translation table associated with the hypervisor, and an IOMMU translation table associated with the I/O device, to reflect a mapping from the physical address to a machine address associated with the remote memory device and used to identify the additional memory page.