Abstract: Techniques for providing an interface between a UICC and a processor, included in an access terminal, that supports asynchronous command processing by the UICC, are described. A first complex command, with a first processing time, may be received from the processor. An initial response to the first command, including a token, may be sent to the processor. The first command may be processed for the first processing time. At least one additional command, having a processing time shorter than the first processing time, may be received from the processor. Processing of the first command may be completed. Processing of a current one of the at least one additional command, which was being processed before, during, or after completion of the processing of the first command, may be completed. A response to the current one of the at least one additional command, including the token, may be sent to the processor.

Abstract: A synchronization apparatus, comprising: a USB device having a USB microcontroller, circuitry for observing USB traffic, and circuitry for decoding from a USB data stream a periodic data structure (such as a clock carrier signal) containing information about a distributed clock frequency and phase and outputting a decoded carrier signal; and circuitry for receiving the decoded carrier signal, for generating a software interrupt upon receipt of a predefined data packet (such as a SOF packet) and for passing the software interrupt to the USB microcontroller; wherein the USB microcontroller is configured to respond to the software interrupt (such as with an interrupt service routine provided therein) by generating an output signal adapted to be used as a synchronization reference signal.

Abstract: A controller for a storage device is connected to a host system and the storage device. A buffer memory includes first and second storage areas. A timer counts a preset given time in response to an instruction to start counting and sends a deadline notification when A given time is elapsed. A command responding portion, when receiving a read command from the host system, instructs the timer to start counting and thereafter outputs a read instruction to read data from the storage system. A data processing portion, in response to the read instruction by the command responding portion, reads specified data from the storage device and holds the read data in the second storage area of the buffer memory. A read control portion sends the host system the data held in the second storage area of the buffer memory when the deadline notification is received from the timer.

Abstract: An integrated circuit includes a shared synchronization bus having a plurality of channels assigned to one or more of a plurality of peripheral modules. The integrated circuit further includes a first peripheral module of the plurality of peripheral modules including a control output coupled to the shared synchronization bus and configured to communicate event timing data to an input of a second peripheral module of the plurality of peripheral modules through a selected one of the plurality of channels.

Abstract: A signal associated with multiple haptic effects is received, each haptic effect from the multiple haptic effects being associated with a time slot from multiple time slots. Each haptic effect from the multiple haptic effects is associated with an effect slot from multiple effect slots at least partially based on the time slot associated with that haptic effect. An output signal is sent for each effect slot from the multiple effect slots, when the associated haptic effect is scheduled for its time slot.

Abstract: Operation based polling in a memory system. A device manager is provided to perform efficient polling by utilizing the effective bandwidth of the memory system, in a controller coupled to a communication end point. The device manager includes a detection module for detecting a type of operation sent to the communication end point. The device manager also includes a storage module for storing a polling interval value based on a time period of the type of operation in a polling counter of the controller. Further, the device manager includes a controlling module for controlling a polling operation of the controller in such a way that the controller polls the communication end point after a wait period according to the polling interval value.

Abstract: A storage tiered that satisfies desired performance is configured by recognizing the type and capacity of storage media of a storage apparatus, which are held by a user, and using the storage media.

Abstract: Devices and methods for generating timing signals at a rate that matches a rate of remotely generated timing signals are provided. In some embodiments, a host generates timing signals in accordance with a USB specification, such as keep-alives, start-of-frame packets, or ITPs. An upstream facing port transmits the timing signals over a network to a downstream facing port. The downstream facing port generates and transmits timing signals to a USB device at a predetermined rate, and alters the predetermined rate based on an analysis of the rate at which timing signals are received from the upstream facing port.

Abstract: A method and system of a host device hosting multiple workloads for controlling flows of I/O requests directed to a storage device is disclosed. In one embodiment, a type of a response from the storage device reacting to an I/O request issued by an I/O stack layer of the host device is determined. Then, a workload associated with the I/O request is identified among the multiple workloads based on the response to the I/O request. Further, a maximum queue depth assigned to the workload is adjusted based on the type of the response, where the maximum queue depth is a maximum number of I/O requests from the workload which are concurrently issuable by the I/O stack layer.

Abstract: An apparatus that compensates for misalignment on a synchronous data bus. The apparatus includes a replica distribution network, a bit lag control element, and a synchronous lag receiver. The replica distribution network receives a first signal, and generates a second signal, where the replica distribution network comprises replicated propagation characteristics of a radial distribution network for a strobe. The bit lag control element is configured to measure a propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a value on a lag bus that indicates the propagation time. The synchronous lag receiver is coupled to the bit lag control element, and is configured to receive a first one of a plurality of radially distributed strobes and a data bit, and is configured to delay registering of the data bit by the propagation time.

Abstract: A method, computer program product, and computing system for associating a first I/O scheduling queue with a first process accessing a storage network. The first I/O scheduling queue is configured to receive a plurality of first process I/O requests. A second I/O scheduling queue is associated with a second process accessing the storage network. The second I/O scheduling queue is configured to receive a plurality of second process I/O requests.

Abstract: A method for communicating media between a host and a display system. In one embodiment the method comprises acquiring, by the host and via a wireless connection between the host and the display system, display information of the display system; generating, by the host, an image sequence at a resolution and a frame rate, the resolution and the frame rate determined from the display information; communicating, from the host to the display system and via the wireless connection, an encoding of the image sequence; and displaying, by the display system, a decoding of the encoding.

Abstract: A signal processing device includes an operation control unit configured to control a timing of an operation process executed by an operation unit; and a transfer control unit configured to control a timing of transferring data that is a target of the operation process, such that the data that is the target of the operation process is loaded by the operation unit according to the timing of the operation process controlled by the operation control unit.

Abstract: Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, the circuitry including at least one input for receiving transaction requests; at least one output for outputting transaction requests; at least one path for transmitting the transaction requests between the input and the output. Control circuitry routes received transaction requests from the input to the output in response to a barrier transaction request. An ordering of at least some transaction requests is maintained with respect to the barrier transaction request within a stream of transaction requests passing along one of the at least one paths, by not allowing reordering of at least some of the transactions requests. The control circuitry includes a response signal generator, the response signal generator is responsive to receipt of the barrier transaction request to issue a response signal.

Abstract: A data processing method and system and relevant devices are provided to improve the processing efficiency of cores. The method includes: storing received packets in a same stream sequentially; receiving a Get_packet command sent by each core; selecting, according to a preset scheduling rule, packets for being processed by each core among the stored packets; receiving a tag switching command sent by each core, where the tag switching command indicates that the core has finished a current processing stage; and performing tag switching for the packets in First In First Out (FIFO) order, and allocating the packets to a subsequent core according to the Get_packet command sent by the subsequent core after completion of the tag switching, so that the packet processing continues until all processing stages are finished. A data processing system and relevant devices are provided. With the present invention, the processing efficiency of cores may be improved.

Abstract: Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.

Abstract: The defined architecture allows for format-efficient data storage on bit-patterned media, while allowing for typical variations in the drive, such as reader to writer gap variations. The defined BPM architecture relaxes some timing requirements on real-time signaling from the formatter to the channel, while enabling bit-accurate alignment between data accesses and the media.

Abstract: A data storage device accepts read and write commands with absolute command completion times based on queue-depth-of-one (qd=1) execution and stores them in an unsequenced commands memory. These commands are requests to access the data storage device and contain both locations on the storage medium where the data is located and whether the requested operation is read or write. For each pair of first and second commands in the memory, the time between execution of the first command and the second command is calculated and stored. A command selector then reads data from the memory based on a resequencing NCQ algorithm which inserts one or more commands from the command memory into the original qd=1 sequence whenever this insertion will not affect the execution time of commands in the original qd=1 sequence. The resequencing algorithm of the present invention increases IOPS and reduced read head actuator travel and wear.

Abstract: The fabric card includes at least one fabric card chip and at least two fabric card connector groups, where each fabric card connector group of the at least two fabric card connector groups includes at least two fabric card connectors, the number of fabric card chips is less than the number of at least two fabric card connector groups, each fabric card chip of the at least one fabric card chip connects to all fabric card connectors in at least one fabric card connector group, all fabric card connectors in the fabric card connector group that connect to the fabric card chip exchange data using the fabric card chip. This fully utilizes an exchange capability of the fabric card chip and saves system resources.

Abstract: In embodiments of a high-speed I/O data system, a first computer chip includes a data transmission system, and a second computer chip includes a data reception system. A data channel communicates an NRZ data signal, and a clock channel communicates a forwarded clock signal, from the data transmission system to the data reception system. The data transmission system includes a first differential serializing transmitter to generate the NRZ data signal from pulsed data, and further includes a second differential serializing transmitter to generate a forwarded clock signal. A first multi-phase transmit clock generator generates transmit clock signals for the first and second differential serializing transmitters. The data reception system includes a data receiver and a de-serializer to receive and de-serialize the NRZ data signal, and includes a multi-phase receive clock generator to generate receive clock signals from the forwarded clock signal for the de-serializing data receiver.

Abstract: According to an embodiment, a control device includes a receiving unit configured to receive an interrupt request requesting an interrupt process to be executed by a processing device that executes one or more processes; a storage unit configured to store therein the interrupt request; a determining unit configured to determine a state of the processing device; a sending unit configured to send the interrupt request to the processing device; and a control unit configured to store the interrupt request received by the receiving unit in the storage unit when the processing device is determined by the determining unit to be in an idle state in which the processing device is not executing the processes and a predetermined condition is not satisfied, and to control the sending unit to send the interrupt request stored in the storage unit to the processing device when the predetermined condition is satisfied.

Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. A plurality of read lines (18), write lines (20) and data lines (22) interconnect the computers (12). When one computer (12) sets a read line (18) high and the other computer sets a corresponding write line (20) then data is transferred on the data lines (22). When both the read line (18) and corresponding write line (20) go low this allows both communicating computers (12) to know that the communication is completed. An acknowledge line (72) goes high to restart the computers (12).

Abstract: A method for regulating I/O requests in a RAID storage system may comprise: receiving a first request to access a first set of one or more logical block addresses (LBAs) of a RAID volume; receiving a second request to access at least one of the first set of one or more LBAs of the RAID volume; and queuing the second request. A system for regulating I/O requests in a RAID storage system may comprise: means for receiving a first request to access a first set of one or more logical block addresses (LBAs) of a RAID volume; means for receiving a second request to access at least one of the first set of one or more LBAs of the RAID volume; and means for queuing the second request.

Abstract: A memory apparatus includes a host device and a slave device. The host device stores verification data. The slave device includes a memory unit, a control unit, and a logic unit. The control unit drives the memory unit to provide storage data in a data transmission sub-period, and further provides a control signal, indicating the first verification data, in a dummy sub-period. The logic unit provides first preamble data, indicating substantially a same data value as the verification data, in the dummy sub-period in response to the first control signal. The preamble data and the storage data are transmitted according to an internal clock signal. The host device samples the first preamble data according to an external clock signal, and determines whether the external and the internal clock signals are synchronized by comparing the first preamble data and the first verification data.

Abstract: An online calibration method and device for a universal serial bus system is disclosed in the present invention. The method comprises following steps: providing a plurality of chirp JK pairs; detecting the plurality of chirp JK pairs, and loading a power on a terminal resistor of a USB device end of the universal serial bus and its coupled to a terminal resistor of a USB host end of the universal serial bus; detecting a voltage level variation of the chirp JK pair; and processing the online calibration according to the voltage level variation to maintain the voltage level within a preset range.

Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more cross-channel work requests that are derived from an operation to be executed by the node. The NI includes a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the cross-channel work requests via the host interface, and to execute the cross-channel work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.

Abstract: In an information processing device according to an embodiment, a generating unit generates a descriptor including information indicating an area in a storage unit and state information indicating a state of an entry in which the information indicating the area is stored, and an update unit updates the state information according to at least one of writing and reading of data to the area indicated in the entry selected according to the state information by the input/output unit. The generating unit generates the descriptor in advance before at least one of writing and reading of data to/from the storage unit is started.

Abstract: A connector can be activated or deactivated by providing power and data signals to the connector at different times. In some embodiments, the power signals are provided to a connector, and then the data signals are provided to the connector after a delay. Providing power and data signals at different times can, in at least some cases, better mimic the timing of signals provided by a connector as the connector is attached to an electronic device. This can aid automated testing of the electronic device. It can also be used to control access of the device through the connector.

Abstract: Computer memory subsystems are disclosed for enhancing signal quality that include: one or more memory modules; a memory bus; and a memory controller connected to the memory modules through the memory bus, the memory controller including a reception buffer connected to the memory bus, the reception buffer capable of receiving an input signal from one of the memory modules, the memory controller including a reception characteristics table capable of storing reception characteristics for each of the memory modules connected to the memory controller, the memory controller including an equalizer connected to the reception buffer and the reception characteristics table, the equalizer capable of equalizing the received input signal in dependence upon the reception characteristics for the memory module from which the input signal was received, and the memory controller including memory controller logic connected to the equalizer, the memory controller logic capable of processing the equalized input signal.

Abstract: Methods and systems for transmitting video pixel data from a transmitter component, such as a controller, to a receiver within a monitor are described. Video data is received at a transmitter at an incoming pixel rate based on a pixel clock. The data is transmitted to the receiver at a link symbol clock rate and is drained from the receiver at the pixel clock rate, which is regenerated by the receiver using the link symbol clock frequency, an M video value, and an N video value. The M video value (Mvid) is determined by the transmitter based on the incoming pixel rate and the N video value (Nvid) may be constant. An accumulator is used within the transmitter to ensure that the transmitter and receiver create a balanced system.

Abstract: A method for providing a content entity from a storage disc is described. The storage disc comprises at least one further content entity. Each content entity comprises a main menu and at least one submenu accessible via the main menu. The storage disc further comprises an entity selection menu. The entity selection menu comprises a link to the main menu of the content entity to be provided. The method comprises providing the entity selection menu for reproduction, receiving a selection of the content entity to be provided, detecting that the storage disc comprises a plurality of content entities, mapping a pre-defined start address to a different start address and providing the selected content entity for reproduction based on the different start address. The pre-defined start address is mapped to a different start address of the storage disc associated with the main menu of the selected content entity to be provided.

Abstract: A source-synchronous capture unit on a receiving circuit includes a first first-in-first-out (FIFO) unit operable to synchronize a write enable signal to generate a synchronized write enable signal that is synchronized with a first free running clock associated with a memory external to the receiving circuit. The write enable sign is generated in response to a read operation by the receiving circuit. The source-synchronous capture unit also includes a second FIFO unit operable to store data from the memory in response to the first free running clock and the synchronized write enable signal, and to output the data in response to a second free running clock associated with the receiving circuit and a read enable signal.

Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

Abstract: In embodiments of a multi-dimension memory timing tuner, a memory device controller that can be interfaced with one or more memory devices is coupled to a memory device for data communication with the memory device via a memory bus. Control registers maintain control register values that are adjustable to tune memory bus timing margins in multi-dimensions. The memory bus timing margins are tunable for implementation of a memory device controller with one or more of the memory devices. A memory timing tuner is implemented to adjust the control register values to tune the memory bus timing margins in the multi-dimensions.

Abstract: A circuit arrangement for signal pick-up and signal generation and a method for operating this circuit arrangement. The circuit has at least one timer module for providing a time basis to a plurality of time control modules connected to it, and has a time routing unit, which is connected to it for the interconnection of the named modules and their signals.

Abstract: Described is a technology by which a virtual hard disk is migrated from a source storage location to a target storage location without needing any shared physical storage, in which a machine may continue to use the virtual hard disk during migration. This facilitates use the virtual hard disk in conjunction with live-migrating a virtual machine. Virtual hard disk migration may occur fully before or after the virtual machine is migrated to the target host, or partially before and partially after virtual machine migration. Background copying, sending of write-through data, and/or servicing read requests may be used in the migration. Also described is throttling data writes and/or data communication to manage the migration of the virtual hard disk.

Abstract: Some of the embodiments of the present disclosure provide a method comprising categorizing each data packet of a plurality of data packets into one of at least two priority groups of data packets; and controlling transmission of data packets of a first priority group of data packets during a first off-time period such that during the first off-time period, data packets of the first priority group of data packets are prevented from being transmitted to a switching module from one or more server blades. Other embodiments are also described and claimed.

Abstract: A method, computer program product, and computing system for associating a first I/O scheduling queue with a first process accessing a storage network. The first I/O scheduling queue is configured to receive a plurality of first process I/O requests. A second I/O scheduling queue is associated with a second process accessing the storage network. The second I/O scheduling queue is configured to receive a plurality of second process I/O requests.

Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

Abstract: A software transactional memory (STM) system allows the composition of traditional lock based synchronization with transactions in STM code. The STM system acquires each traditional lock the first time that a corresponding traditional lock acquire is encountered inside a transaction and defers all traditional lock releases until a top level transaction in a transaction nest commits or aborts. The STM system maintains state information associated with traditional lock operations in transactions and uses the state information to eliminate deferred traditional lock operations that are redundant. The STM system integrates with systems that implement garbage collection.

Abstract: In an embodiment, a system includes a memory controller, processors and corresponding caches. The system may include sources of uncertainty that prevent the precise scheduling of data forwarding for a load operation that misses in the processor caches. The memory controller may provide an early response that indicates that data should be provided in a subsequent clock cycle. An interface unit between the memory controller and the caches/processors may predict a delay from a currently-received early response to the corresponding data, and may speculatively prepare to forward the data assuming that it will be available as predicted. The interface unit may monitor the delays between the early response and the forwarding of the data, or at least the portion of the delay that may vary. Based on the measured delays, the interface unit may modify the subsequently predicted delays.

Abstract: A system program causes, as an execution preparation process for a control operation of a PLC, execution of a process for generating a reception buffer for storing received input data, and execution of a process for generating, for each input data referred to by a control program, an input synchronization buffer used by the control program as a reference target for the input data. The system program causes, as an execution control process for the control operation of the PLC, execution of an input copy process for copying the received input data from the reception buffer to the input synchronization buffer corresponding to the input data, and execution of a control program start process for starting execution of the control program.

Abstract: A bus network passes pending messages from bus interface to bus interface until they are downloaded at a target bus interface by a target device connected to the target bus interface. The messages are tagged with at least one download control bit. The download control bit has a priority state indicating that a message has already passed the target bus interface at least once without being downloaded. When controlling selection of messages for downloading by the target device, the target bus interface selects messages with the download control bit in the priority state with a greater probability than messages not having a download control bit in the priority state.

Abstract: A method of machine control can include providing at least a system master signal, selectively synchronizing at least sub-system master signal to the system master signal based on the value of the system master signal, and carrying out at least one operation based on the value of the other master signal. For example, a machine controller may provide a system virtual master signal and synchronize one or more module virtual master signals to the system virtual master based on the system virtual master count value. One or more components of the module may operate based on the count value of the module virtual master signal. The use of an asynchronous control method may advantageously increase the flexibility of the machine. Because the operation of the components of the machine may depend on respective virtual master signals, a machine using asynchronous control methods may advantageously continue operating one component or module in the event of a fault involving other components.

Abstract: A finite state machine is provided that both serializes virtual GPIO signals and deserializes virtual GPIO signals responsive to cycles of an external clock. The finite state machine frames the serialized virtual GPIO signals into frames each demarcated by a start bit and an end bit.

Abstract: An interface board includes a synchronizer that synchronizes a first time that is a time of the interface board to a base time based on a master synchronization signal that is supplied by an external master time source and that defines the base time. The interface board also includes a comparator that compares a phase of a first synchronization signal that synchronizes to the first time with a phase of a shared synchronization signal sent by an interface controller that controls the interface board, and a notifier that notifies another interface board of a comparison result of the comparator.

Abstract: A method for back-off retry with priority routing in a single, cohesive SAS expander includes routing a data transfer between an input of a single, cohesive SAS expander and an output of the single, cohesive SAS expander, wherein the single, cohesive expander includes a first SAS expander, and at least one additional SAS expander via at least one inter-expander link (IEL). The routing of data may further include routing a first OPEN request on a direct path through the first SAS expander to a port of a device and routing a second OPEN request on an alternate path from the first SAS expander and through a second SAS expander to the port of the device. The method further includes determining link availability between the second SAS expander and the port of the device, and, upon determination of a failed link or a busy link, re-routing the data transfer from the second SAS expander to the first SAS expander or a third SAS expander, or retrying the data transfer through the second SAS expander.

Abstract: An input/output unit for a computer system that is interfaced with a memory unit having a plurality of partitions manages completions of read requests in the order that they were made. A read request buffer tracks the order in which the read requests were made so that read data responsive to the read requests can be completed and returned to a requesting client in the order the read requests were made.

Abstract: A method according to one embodiment includes receiving, at an I/O Handler, an instruction to initiate a backup operation on data associated with an application running on multiple servers; and stretching communication between instances of the application and data storage volumes associated therewith during initiating the backup operation. Additional systems, methods, and computer program products are also disclosed.

Abstract: In a communication system, data is selectively transmitted using single-ended or differential signaling. The data is transmitted in relation to a plurality of clock signals having different relative phases. When the data is transmitted using single-ended signaling, data on adjacent signal lines undergo logic transitions at different times in relation to the plurality of clock signals.