Operation Scheduling Patents (Class 710/6)
  • Patent number: 11698740
    Abstract: In a computer system, in a case where a throughput upper limit value is set as upper limit value 1, a throughput limit notification program executed by a storage device gives a notification to a storage management device when a throughput of a logical volume reaches the upper limit value 1. In response to this notification, a throughput upper limit value setting program executed by the storage management device outputs, to the storage device, a command for switching the throughput upper limit value from the upper limit value 1 to upper limit value 2, such that the throughput upper limit value is switched.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: July 11, 2023
    Assignee: Hitachi, Ltd.
    Inventors: Takanobu Suzuki, Akira Deguchi, Tsukasa Shibayama
  • Patent number: 11614950
    Abstract: A method for controlling at least one setting of a basic input output system (BIOS) of at least one automated transaction machine (ATM) can include provisioning features of an active management technology system of a first computing device associated with an ATM. The method can also include establishing an initial trust between the first computing device and a second computing device that is remote from the first computing device, over a serial-over-lan (SOL) connection that is a feature of the active management technology system. The method can also include configuring the setting of the BIOS of the first computing device and storing a schedule for changing the setting of the BIOS. The method can also include reconfiguring the setting of the BIOS in response to the schedule stored on the database over the SOL.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: March 28, 2023
    Assignee: Diebold Nixdorf Incorporated
    Inventors: Kevin Martin, Richard Brunt, Shon Hostetler, Alvin Golnik, Jr., Richard Steinmetz
  • Patent number: 11609878
    Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a memory controller circuit and a plurality of networks formed from a plurality of individual network component circuits. The memory controller includes a PIO message control circuit that is configured to receive PIO messages addressed to individual network component circuits and determine whether to send the PIO messages to the individual network component circuits based on determine whether previous PIO messages are pending for the individual network component circuits. The PIO message control circuit is configured to delay a first PIO message at the PIO message control circuit in response to determining that previous PIO message is pending for the addressee of the first PIO message.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: March 21, 2023
    Assignee: Apple Inc.
    Inventors: Sergio Kolor, Oren Bar, Ilya Granovsky
  • Patent number: 11561798
    Abstract: A system and method for avoiding write back collisions. The system receives a plurality of instructions at a pipeline queue. Next an issue queue determines a number of cycles for each instruction of the plurality of instructions. The issue queue further determines if a collision will occur between at least two of the instructions. Additionally, the system determines in response to a collision between at least two of the instructions, a number of cycles to delay at least one of the at least two instructions. The instructions are then executed. The system then places the results of the instruction for instructions that had a calculated delay in a result buffer for the determined number of cycles of delay. After the determined number of cycles of delay, the system sends the results to a results mux. Once received at the results mux the results are written back to the register file.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: January 24, 2023
    Assignee: International Business Machines Corporation
    Inventors: Brian D. Barrick, Maarten J. Boersma, Niels Fricke, Dung Q. Nguyen, Brian W. Thompto, Andreas Wagner
  • Patent number: 11544000
    Abstract: A non-volatile memory express (NVMe) switch is located in between a host and storage. A first storage access command is received from a host via a peripheral computer interface express (PCIe) interface to access the storage. The first storage access command conforms to NVMe and the storage comprises two or more solid-state drives (SSDs). A respective second storage access command is sent to the two or more SSDs based on the first storage access command. A respective completion is received from each of the two or more SSDs based on the respective second storage access command. A completion is sent to the host via the PCIe interface based on the received completions from each of the two or more SSDs.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: January 3, 2023
    Assignee: Marvell Asia Pte Ltd.
    Inventors: Scott Furey, Salil Suri, Liping Guo, Chih-Lung Liu, Yingdong Li
  • Patent number: 11520599
    Abstract: A method for controlling at least one setting of a basic input output system (BIOS) of at least one automated transaction machine (ATM) can include provisioning features of an active management technology system of a first computing device associated with an ATM. The method can also include establishing an initial trust between the first computing device and a second computing device that is remote from the first computing device, over a serial-over-lan (SOL) connection that is a feature of the active management technology system. The method can also include configuring the setting of the BIOS of the first computing device and storing a schedule for changing the setting of the BIOS. The method can also include reconfiguring the setting of the BIOS in response to the schedule stored on the database over the SOL.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: December 6, 2022
    Assignee: Diebold Nixdorf Incorporated
    Inventors: Kevin Martin, Richard Brunt, Shon Hostetler, Alvin Golnik, Jr., Richard Steinmetz
  • Patent number: 11392514
    Abstract: A data processing apparatus is specified, having multiple processor devices (4), multiple interface devices (5), to which external devices (E) are respectively connectable, and having connections (8, 10) between the interface devices (5) and the processor devices (4), via which data are transportable between the interface devices (5) and the processor devices (4). In the connections (8, 10), there is provision for at least one data management device (20) for handling data flows between the interface devices (5) and the processor devices (4). The data management device (20) is in the form of a hardware component.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: July 19, 2022
    Assignee: ROCKWELL COLLINS DEUTSCHLAND GMBH
    Inventor: Timo Reubold
  • Patent number: 11328351
    Abstract: There is a provided an apparatus and method to securely communicate an order by efficiently invoking a program application on a computing device. The computing device may operate to receive and present a push notification, even while in a locked state, where the push notification requests input to initiate a performance of a task that is associated with an application defined by instructions stored on the computing device. The computing device receives input and initiates the performance of the task without fully loading the application into an operating memory. The input may initiate a communication of a message to a remote processing system to execute the order.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: May 10, 2022
    Assignee: THE TORONTO-DOMINION BANK
    Inventors: Nasim Sarir, Peter Horvath, Maryam Karbasi
  • Patent number: 11250025
    Abstract: Methods and systems for bulk uploading of data in an on-demand service environment are described. In one embodiment, such a method includes retrieving a bulk transaction request from a transaction queue within a host organization, where the bulk transaction request specifies a plurality of database transactions to be processed against a multi-tenant database system of the host organization. Such a method further includes determining a current computational load of the multi-tenant database system, processing a subset of the plurality of database transactions specified by the bulk transaction request against the multi-tenant database system when the current computational load is below a threshold, and updating a bulk transaction results log based on the subset of the plurality of database transactions processed. Remaining database transactions specified by the bulk transaction request may then be re-queued for later processing.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: February 15, 2022
    Assignee: salesforce.com, inc.
    Inventors: Manoj Cheenath, Simon Z. Fell, Jesper Joergensen
  • Patent number: 11244385
    Abstract: A system for providing coaching includes a system that creates a user-specific coach to assist a user in achieving one or more goals, such as, e.g., a financial goal. The coach is generated based on one or more traits of the user to increase the likelihood that the user will relate and respond to communications from the coach in a manner that enables the user to achieve his/her goal. The traits used by the system to create the coach can include traits input directly by a user, as well as user traits deduced by the system by monitoring various types of user behavior, including the user's usage of computing devices, habits, etc. The system also adapts the coaching provided by the coach in response to trends noted by the coaching system as the system is used by the user as well as others.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: February 8, 2022
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Tyua Fraser, Jennifer A. Hammer, Josh Neal, Dana Neitz, Masoud Vakili, Molly Wilcox
  • Patent number: 11201963
    Abstract: Methods, systems, and apparatus for prioritizing communications are described. Metadata that characterizes an electronic communication is obtained and a machine learning algorithm is applied to the metadata to generate a scoring model. A score for the electronic communication is generated based on the scoring model.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: December 14, 2021
    Assignee: eHealth, Inc.
    Inventors: Yvonne French, Nicholas Jost, Michael Tadlock, Qingxin Yu
  • Patent number: 11188485
    Abstract: A memory system includes a first memory comprising at least one first code region; a second memory comprising at least one second code region; and a control unit configured to perform a first operation by executing a first code loaded to the first code region, and perform a second operation by executing a second code loaded to the second code region. The control unit performs a swap operation on the first code and the second code, based on a swap condition.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: November 30, 2021
    Assignee: SK hynix Inc.
    Inventor: Jeen Park
  • Patent number: 11188247
    Abstract: In certain techniques, a plurality of storage devices of a storage system are sorted into a sequence of storage devices by capacity. A first number of at least one storage device with maximum capacity in the sequence of storage devices is determined. A group of storage devices are selected from the sequence of storage devices based on the first number, a device number of storage devices in the sequence and a threshold device number, the number of storage devices in the group of storage devices being less than or equal to the threshold device number. A user storage system is built based on storage space in the group of storage devices, the user storage system having a predetermined width for representing a sum of a data width and a parity width in one stripe of the user storage system. Accordingly, efficiency of storage space utilization can be improved.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: November 30, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Haiying Tang, Xiaobo Zhang, Jian Gao, Geng Han, Xinlei Xu
  • Patent number: 11150613
    Abstract: A control system may include a display device and a processor that receives one or more inputs from the display device. The processor may generate a cause and effect visualization to be depicted on the display device, such that the cause and effect visualization represents a cause and effect logic configured to control one or more operations of a first set of industrial devices based one or monitored conditions. The processor may receive the inputs via the display device, such that the inputs include one or more configuration settings associated with the operations of the first set of industrial devices, the monitored conditions, or any combination thereof. The processor may then control the one or more operations of the first set of industrial devices based on the cause and effect logic and the inputs.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: October 19, 2021
    Assignee: Sensia LLC
    Inventors: Peter Graham Skipp, Allan Brian Rentcome, Robert Terrill Gebert
  • Patent number: 11099992
    Abstract: Embodiments include a method performed by a computing device. The method includes (a) receiving a plurality of access requests to access data of a multilayered storage system; (b) in response to determining that a first access request can be served from a top data layer, executing the first access request by accessing the top data layer; (c) in response to determining that a second access request cannot be served from the top data layer, determining whether a current concurrency number of the top data layer is less than a permitted concurrency number (PCN) of the top data layer; and (d) in response to determining that the current concurrency number of the top data layer is not less than the PCN, waiting until the current concurrency number of the top data layer is less than the PCN and then executing the second access request by accessing another data layer below the top layer.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: August 24, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Xinlei Xu, Ruiyong Jia, Liam Xiongcheng Li, Lifeng Yang, Jian Gao
  • Patent number: 11093140
    Abstract: A computer having a plurality of accounts and a storage device having a host interface, a controller, non-volatile storage media, and firmware. An account is configured with at least a predetermined speed in accessing the non-volatile storage media by allocating a number of input/output submission queues in the buffer area of the host. The number can be determined from a ratio between the predetermined speed configured for the account and a saturated speed of the storage device with sufficient submission queues. Data access requests from the account are evenly distributed to the submission queues allocated for the exclusive use by the account; and the controller, configured via the firmware, processes with equal priority the submission queues configured for the storage device. Thus, the account can have at least the predetermined speed in accessing the non-volatile storage media, regardless of how other accounts access the storage device.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: August 17, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Alex Frolikov
  • Patent number: 11086752
    Abstract: The subject matter described herein relates to vendor-neutral testing and scoring of a system under test. One method for vendor-neutral scoring of a system under test includes generating a pre-testing snapshot of a system under test. The method further includes executing vendor-neutral testing of plural different subsystems of the system under test. The method further includes generating a vendor-neutral score based on the testing. The method further includes generating a post-testing snapshot of the system under test.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: August 10, 2021
    Assignee: KEYSIGHT TECHNOLOGIES SINGAPORE (SALES) PTE. LTD.
    Inventor: Avinash Ramanath
  • Patent number: 11036656
    Abstract: An industrial automation system employing a mesh topology of input/output allows flexibility in pairing field devices and controllers though the I/O mesh. Field devices can be connected to the geographically closest I/O module channel without regard to the location of the necessary controller. Modular prefabrication and deployment of the I/O modules becomes less complex and less time consuming thereby reducing costs.
    Type: Grant
    Filed: April 7, 2019
    Date of Patent: June 15, 2021
    Assignee: Honeywell International Inc.
    Inventors: Paul Francis McLaughlin, Christopher Paul Ladas, Angela Lee Lordi, James Michael Schreder, Stanley Robert Gorzelic
  • Patent number: 10990287
    Abstract: A data storage device may include: a nonvolatile memory device; and a controller configured to control an operation of the nonvolatile memory device. In response to an unmap command is received from a host, the controller may generate an unmap descriptor including logical block addresses to be trimmed, stores the generated unmap descriptor, and transfer a response signal to the host. The response signal indicates that an unmap caching operation corresponding to the unmap command is completed.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: April 27, 2021
    Assignee: SK hynix Inc.
    Inventors: Young Ick Cho, Byeong Gyu Park, Sung Kwan Hong
  • Patent number: 10990523
    Abstract: A memory controller configured to control a memory device including a plurality of banks. The memory controller may determine whether a number of write commands enqueued in a command queue of the memory controller exceeds a reference value, calculate a level of write power to be consumed by the memory device in response to at least some of the write commands from among the enqueued write commands when the number of enqueued write commands exceeds the reference value, and schedule, based on the calculated level of write power, interleaving commands executing an interleaving operation of the memory device, from among the enqueued write commands.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: April 27, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong-ho Lee, Young-sik Kim, Eun-chu Oh, Young-kwang Yoo, Young-geun Lee
  • Patent number: 10909050
    Abstract: A gateway apparatus is provided, including: a storage unit storing a plurality of different filter information pieces each including an application target ECU configuration, a filter condition indicating a condition of data allowed to be transferred to the ECU and a filter version, in a manner associated with each other; a selection unit selecting, from among the plurality of different filter information pieces, a filter information piece whose application target ECU configuration corresponds to an ECU configuration of an ECU installed in the vehicle; a notification unit notifying an information processor of a filter version included in the filter information piece selected by the selection unit; and a filter processing unit judging whether or not data received from the information processor is to be transferred to the ECU installed in the vehicle in accordance with a filter condition included in the filter information piece selected by the selection unit.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: February 2, 2021
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Shiro Ouchi, Hiroki Keino
  • Patent number: 10896199
    Abstract: An apparatus for controlling a storage system having a data replication function, comprises: a storage array component being operable to send notification to a replication engine that a write of data to a primary storage location by a host is subject to data replication; the replication engine being operable to receive the notification and in response to instruct the storage array to copy the data to a secondary storage location; wherein the data is copied to the secondary storage location unmediated by the replication engine.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: January 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kenneth F. Day, Robert B. Nicholson, Lee J. Sanders, William J. Scales
  • Patent number: 10885023
    Abstract: A database system may implement asynchronous processing for synchronous requests received at the database. A pool of request processing threads may be maintained. As access requests for the database are received from clients, an available request processing thread in the pool may process the access request. The access request may be dependent on a persistent storage I/O operation, such that processing of the access request waits at least until the persistent storage I/O operation is complete. The request processing thread may perform processing operations for the access request so that persistent storage I/O operation is performed and become available to process other access requests. A response processing thread may determine that the persistent storage I/O operation for the access request is complete, and send a response to the client.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: January 5, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Anurag Windlass Gupta, Alexandre Olegovich Verbitski, Kamal Kant Gupta
  • Patent number: 10884624
    Abstract: Methods and systems of updating serial attached small computer system interface (SAS)/serial advanced technology attachment (SATA) hard disk drive (HDD) firmware (FW) using a management controller (MC) are provided. The method includes uploading the HDD FW to the MC via the local area network (LAN), breaking the HDD FW into a plurality of chunks, issuing a plurality of write commands and writing the plurality of chunks into the SAS HDD.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: January 5, 2021
    Assignee: QUANTA COMPUTER INC.
    Inventor: Te-Hsien Lai
  • Patent number: 10860225
    Abstract: An information processing apparatus includes a memory and a processor and accesses a first storage device and a second storage device wherein an access speed of the second storage device is higher than an access speed of the first storage device. The memory stores information relating to a request in a request from the information processing apparatus to the second storage device. The processor, which is connected to the memory, determines a load on the second storage device based on the information relating to the request.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: December 8, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Satoshi Kazama, Shinya Kuwamura, Eiji Yoshida, Junji Ogawa
  • Patent number: 10846098
    Abstract: An apparatus and method of data processing are provided. The apparatus comprises at least two execution pipelines, one with a shorter execution latency than the other. The execution pipelines share a write port and issue circuitry of the apparatus issues decoded instructions to a selected execution pipeline. The apparatus further comprises at least one additional pipeline stage and the issue circuitry can detect a write port conflict condition in dependence on a latency indication associated with a decoded instruction which it is to issue. If the issue circuitry intends to issue the decoded instruction to the execution pipeline with the shorter execution latency then when the write port conflict condition is found the issue circuitry will cause use of at least one additional pipeline stage in addition to the target execution pipeline to avoid the write port conflict.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: November 24, 2020
    Assignee: Arm Limited
    Inventors: Cédric Denis Robert Airaud, Luca Nassi, Damien Robin Martin, Xiaoyang Shen
  • Patent number: 10817181
    Abstract: An apparatus comprises a host device configured to communicate over a network with a storage system comprising a plurality of storage devices. The host device comprises a multi-path input-output driver configured to schedule input-output operations for delivery to the storage system over the network. The multi-path input-output driver is further configured to measure latencies of respective ones of a plurality of paths from the host device to the storage system, to schedule particular ones of the input-output operations for delivery to the storage system over particular ones of the paths based at least in part on the measured latencies, and to control transmission of the particular input-output operations over the particular paths in accordance with the scheduling.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: October 27, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Sanjib Mallick, Vinay G. Rao, Subin George, Arieh Don
  • Patent number: 10776753
    Abstract: Updating a data storage unit using tenant specific update policies is disclosed. In an embodiment, a plurality of application events from an events publisher is received at a data pipeline manager. The plurality of application events are associated with data at a source data storage unit and are stored at a data pipeline data storage unit. An update process is initiated, based on an update policy associated with a particular tenant. During the update process, one or more application events associated with the particular tenant are selected from among the plurality of application events stored at the data pipeline data storage unit. Data associated with the one or more selected application events is selected from the source data storage unit. Data selected from the source data storage unit is stored at a target data storage unit.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: September 15, 2020
    Assignee: XACTLY CORPORATION
    Inventors: Vasudev Krishnamoorthy, Tony Wang, Denis Gefter, Ron Rasmussen
  • Patent number: 10564895
    Abstract: An infrastructure, method and controller card for managing flash memory in a storage infrastructure. A system is provided that includes flash memory; and a controller that includes: an I/O request handler for handling standard read and write (R/W) operations requested from a host; a garbage collection (GC) system that performs a GC process on the flash memory in response to a threshold condition, wherein the GC process includes GC-induced R/W operations; and a scheduler that interleaves standard R/W operations with GC-induced R/W operations, wherein the scheduler calculates minimum and maximum boundaries for GC-induced R/W operations for a GC process based on an estimated GC latency.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: February 18, 2020
    Assignee: SCALEFLUX, INC.
    Inventors: Qi Wu, Duy Nguyen, Prathamesh Amritkar, Qing Li
  • Patent number: 10423414
    Abstract: In an embodiment, a device including a processor, a plurality of hardware accelerator engines and a hardware scheduler is disclosed. The processor is configured to schedule an execution of a plurality of instruction threads, where each instruction thread includes a plurality of instructions associated with an execution sequence. The plurality of hardware accelerator engines performs the scheduled execution of the plurality of instruction threads. The hardware scheduler is configured to control the scheduled execution such that each hardware accelerator engine is configured to execute a corresponding instruction and the plurality of instructions are executed by the plurality of hardware accelerator engines in a sequential manner. The plurality of instruction threads are executed by plurality of hardware accelerator engines in a parallel manner based on the execution sequence and an availability status of each of the plurality of hardware accelerator engines.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: September 24, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ajit Deepak Gupte, Mahesh Mehendale, Navin Acharya, Mel Alan Phipps
  • Patent number: 10394728
    Abstract: A processor includes a core and an interrupt controller. The interrupt controller includes logic to read interrupt data from a memory, the interrupt data including a timestamp, an allowable delay value, and at least one interrupt vector. The interrupt controller also includes a delay-comparison circuit to determine a time lapse based on the timestamp and a system clock signal and to compare the time lapse to the allowable delay value. Further, the interrupt controller includes a second logic to determine whether to invoke an interrupt handler based on the comparison of the time lapse to the allowable delay value.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventor: Yen Hsiang Chew
  • Patent number: 10387036
    Abstract: A semiconductor memory device according to the present disclosure includes: a memory cell array including a plurality of planes; a command processing unit configured to generate an internal command to be executed by at feast one plane among the plurality of planes on the basis of external commands received from an external controller; a status register configured to store status information of the external commands by a tag included in the external command according to results of performing the internal command.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: August 20, 2019
    Assignee: SK hynix Inc.
    Inventor: Beom Ju Shin
  • Patent number: 10348796
    Abstract: A processor performing functions of a video client may measure an occupancy of a video buffer, select a video chunk having a first video encoding bitrate based upon the occupancy, and provide a deadline for a delivery of the video chunk to a multipath transport layer module. The processor may further activate a deadline aware scheduler of the module when the occupancy exceeds a first threshold and when the deadline aware scheduler was previously disabled, and deactivate the deadline aware scheduler when the occupancy falls below a second threshold and when the deadline aware scheduler was previously enabled. The module may request packets of the video chunk from a video server and select at least one active interface for the video server to send each packet. The deadline aware scheduler may select whether a secondary network interface is to be an active interface or a non-active interface.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: July 9, 2019
    Assignees: AT&T Intellectual Property I, L.P., Indiana University Research and Technology Corporation
    Inventors: Bo Han, Lusheng Ji, Vijay Gopalakrishnan, Feng Qian
  • Patent number: 10338830
    Abstract: The invention introduces a method for accessing a solid state disk for QoS (Quality of Service), performed by a processing unit, including at least the following steps: obtaining execution histories of VMs (virtual machines); selecting one of the FIFO (First-In-First-Out) queues according to the execution histories and QoS; obtaining a first data access request, which was entered earliest in the selected FIFO queue; and directing a storage device to complete a data access operation according to the first data access request.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: July 2, 2019
    Assignee: SHANNON SYSTEMS LTD.
    Inventors: Zhen Zhou, Ningzhong Miao
  • Patent number: 10270861
    Abstract: The various embodiments herein provide a method and system for dual role handling between at least two devices in a wireless environment. The method comprises seeking, by a first device, at least one device with a specified connection topology, establishing a connection with a second device having a same connection topology, establishing an Application service platform (ASP) session with the second device once the connection is established between the first device and the second device, sending, by the first device, a role negotiation message comprising a request for role change to the second device, wherein the role negotiation message corresponds to a WSB message, receiving a custom message for confirmation, if the second device accepts the role change, and changing the connection topology between the first device and the second device once the role negotiation between the first device and the second device is completed.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: April 23, 2019
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Mayuresh Madhukar Patil, Venkateswar Jeedigunta, Jong-Hyo Lee, Karthik Srinivasa Gopalan
  • Patent number: 10241835
    Abstract: A storage resource scheduling method and a storage and computing system, where the storage and computing system has a computing system and a storage system, the computing system has at least one computing unit, and the storage system has at least one storage unit. The method executed by the computing system includes: identifying a task type of a computing unit in the at least one computing unit; sending task type information to the storage system, where the task type information carries the task type; acquiring a scheduling policy of the task type according to the task type information; and scheduling, according to the scheduling policy, a storage unit corresponding to the computing unit. In the method, different tasks of a computing unit are perceived, and resource scheduling is performed according to a task type, thereby implementing scheduling and management on different tasks of a same storage unit.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: March 26, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Li Wang
  • Patent number: 10209990
    Abstract: A conditional fetch-and-phi operation tests a memory location to determine if the memory locations stores a specified value and, if so, modifies the value at the memory location. The conditional fetch-and-phi operation can be implemented so that it can be concurrently executed by a plurality of concurrently executing threads, such as the threads of wavefront at a GPU. To execute the conditional fetch-and-phi operation, one of the concurrently executing threads is selected to execute a compare-and-swap (CAS) operation at the memory location, while the other threads await the results. The CAS operation tests the value at the memory location and, if the CAS operation is successful, the value is passed to each of the concurrently executing threads.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: February 19, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David A. Wood, Steven K. Reinhardt, Bradford M. Beckmann, Marc S. Orr
  • Patent number: 10191691
    Abstract: Systems, methods, apparatuses, and software for data storage systems are provided herein. In one example, a data storage platform includes one or more data storage modules each comprising storage drives coupled over a Peripheral Component Interconnect Express (PCIe) fabric with at least one processing module that receives storage operations directed to the one or more data storage modules over one or more network interfaces. The processing module is configured to assign service levels in a queue to the storage operations that are received over the one or more network interfaces. Based at least on the service levels, the processing module is configured to service the storage operations from the queue with the one or more data storage modules over the PCIe fabric.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: January 29, 2019
    Assignee: Liqid Inc.
    Inventors: Phillip Clark, James Scott Cannata, Jason Breakstone
  • Patent number: 10169948
    Abstract: Storage operation requests from any device of a computing environment can be numerous and frequent. In particular, if there is a high frequency initiation of storage operation requests to store, retrieve, or modify data, then targeted storage systems have to easily and quickly decide in which order to satisfy the storage operation requests, such as when two requests occur to retrieve identical data. Storage operation requests can be prioritized at the end device instead of any intermediary device or enabling a complex ordering algorithm. Moreover, the storage on a cloud model consists of similar storage services which serve consumers of different needs. Some applications/users can afford longer service time than other applications/users. Differentiation in required service time allows price differentiation. The solution will serve premium customers faster than it serves customers who paid less.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mudi M Fluman, Yaacov Frank, Janice M Girouard, Yehuda Shiran
  • Patent number: 10163135
    Abstract: Data storage devices and methods to combine user content with supplemental content at a data storage device are disclosed. The data storage device includes a host interface, a controller coupled to the host interface, a first storage area coupled to the controller, and a second storage area coupled to the controller. The host interface is configured to enable the data storage device to receive one or more user content items from a host device when the data storage device is operationally coupled to the host device. The controller is configured to store the one or more user content items in the first storage area. The controller is also configured to combine a particular supplemental content item stored in the second storage area with a particular user content item from among the one or more user content items.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: December 25, 2018
    Assignee: SANDISK IL LTD.
    Inventor: Rafi Ben-Rubi
  • Patent number: 10146695
    Abstract: An apparatus includes a memory and a processor coupled to the memory. The processor is configured to perform the steps of: receiving a first head link for a page invalidation chain, the page invalidation chain including a plurality of page invalidation tables (PITs); receiving a second head link for an active real page table (RPT) chain, the active RPT chain including a plurality of RPTs; accessing a PIT, wherein the PIT includes a first data structure and a second data structure; invalidating the one or more RPTs, whereas the one or more RPTs are invalidated simultaneously in a batch; and releasing the one or more RPTs to a free RPT chain, the free RPT chain includes a plurality of released RPTs.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: December 4, 2018
    Assignee: UNISYS CORPORATION
    Inventors: David W Schroth, Kerry M Langsford, Max J Heimer, Michael J Rieschl
  • Patent number: 10067888
    Abstract: Providing I/O operations to a storage device includes selecting a portion of original I/O operations based on a first set of criteria, determining whether to subdivide each of the portion of original I/O operations that are selected according to a second set of criteria different than the first set of criteria, and converting each of the original I/O operations selected for subdivision into a plurality of subdivided I/O operations for different portions of data for a corresponding one of the original I/O operations, where at least two of the different portions are from a single track of data on the storage device. The first set of criteria may include whether the I/O operations are for multiple tracks of data and whether the storage device supports subdividing a single track. The second set of criteria may include determining a measured amount of performance improvement for previous subdivision operations.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: September 4, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Douglas E. LeCrone, Paul A. Linstead
  • Patent number: 10055253
    Abstract: A method includes, in a processor, receiving first and second operations for periodic execution with respective specified time periods. Respective actual time periods having no common divisor are derived from the specified time periods. The first and second operations are executed periodically with the respective actual time periods.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: August 21, 2018
    Assignee: Mellanox Technologies, Ltd.
    Inventor: Itai Baz
  • Patent number: 10055170
    Abstract: A method for execution by a dispersed storage and task (DST) execution unit includes generating low-load prediction data, which includes selecting a time period corresponding to a predicted low-load, based on a plurality of historical load samplings. Maintenance task scheduling data is generated based on the low-load prediction data. Generating the maintenance task scheduling data includes assigning a maintenance task to a scheduled time that is within the time period corresponding to the predicted low-load. The maintenance task is executed at the scheduled time.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: August 21, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jason K. Resch, Ethan S. Wozniak
  • Patent number: 10027969
    Abstract: A parallel decoder for decoding compressed video picture data including inter-coded picture item data with motion vector data. A decoding module decodes picture data stored in a temporary storage. The decoding module includes an inter-prediction module that uses inter-prediction item data to decode an inter-coded picture item by referring to already decoded reference picture item data. The structure of inter-prediction item data in the temporary storage is a function of the positions of corresponding reference picture items. The decoding order of stored inter-prediction item data by the inter-prediction module is prioritized as a function of a decoding order of reference picture item data.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: July 17, 2018
    Assignee: NXP USA, INC.
    Inventors: Hongzhang Yang, Chaofan Huang, Peng Zhou
  • Patent number: 10007438
    Abstract: A computing device having interface, memory, and processing module, transmits write requests for a set of encoded data slices to storage units (SUs) of a dispersed storage network (DSN) based on a write request process and to receive proposal records for a subset of the set of encoded data slices from at least some of the SUs. The computing device interprets the proposal records to determine whether it or any another computing device has a threshold number of its respective write requests in a first priority position in the ordered list of pending write requests. When no computing device has the threshold number, the computing device determines whether any computing device can be blacklisted and/or eliminated and whether a winner of the ballot can be determined after such determination. When a winner is determined, the computing device transmits finalize commands to the storage units.
    Type: Grant
    Filed: June 25, 2016
    Date of Patent: June 26, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Greg R. Dhuse, Ravi V. Khadiwala, Ethan S. Wozniak
  • Patent number: 9990137
    Abstract: Providing I/O operations to a storage device includes selecting a portion of original I/O operations based on a first set of criteria, determining whether to subdivide each of the portion of original I/O operations that are selected according to a second set of criteria different than the first set of criteria, and converting each of the original I/O operations selected for subdivision into a plurality of subdivided I/O operations for different portions of data for a corresponding one of the original I/O operations. The first set of criteria may include whether the I/O operations are for multiple tracks of data. The second set of criteria may include determining a measured amount of performance improvement for previous subdivision operations. Performance of subdivided I/O operations may be monitored. A number of subdivided I/O operations may be limited by a number of available parallel I/O routes.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: June 5, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Douglas E. LeCrone, Paul Linstead
  • Patent number: 9983831
    Abstract: A system and method for providing consistent performance in a storage device, such as a solid state drive. A threshold value for command execution time for a command in a category of command (e.g., a read command or a write command) and a command size, is stored in the storage device. When a host command in the category (e.g., a read command) and corresponding size is received, the storage device executes the command, and if it completes execution of the command in a time that is less than the threshold value, the solid state drive waits until an amount of time equal to the threshold value has elapsed before sending the command completion.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: May 29, 2018
    Assignee: NGD SYSTEMS, INC.
    Inventors: Joao Alcantara, Ricardo Cassia, Kamyar Souri, Vladimir Alves, Guangming Lu
  • Patent number: 9986576
    Abstract: Network devices are steered to preferred access points using a probability function. A probe request for connection is received from a network device. The probe request can be from a network device attempting to use a wireless network (e.g., a IEEE 802.11-type network or other suitable type of network). A probability function that defines a likelihood of granting the network device a connection is used to determine whether to accept or deny the response. The probe response is then sent to the network device.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: May 29, 2018
    Assignee: Fortinet, INC
    Inventors: Sung-Wook Han, Mohan Ram
  • Patent number: 9910524
    Abstract: An electronic device detects a change in intensity of an input on an input element that includes detecting an increase in intensity followed by a decrease in intensity, and recognizes at least a portion of the change in intensity of the input as a first input event that is associated with a first operation, for example a single click operation. After recognizing the first input event, the device delays performance of the first operation while monitoring subsequent changes in intensity of the input for a second input event, wherein the delay is limited by a default delay time period. If the second event is recognized before default delay time period has elapsed, a second operation is performed and the first operation is not performed. However, if early-confirmation criteria for the first input event are met before the default delay period elapses, the first operation is performed.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: March 6, 2018
    Assignee: APPLE INC.
    Inventors: Nicole M. Wells, Leah M. Gum, Kenneth L. Kocienda, Camille Moussette, Jean-Pierre M. Mouilleseaux, Joshua B. Kopin, Jules K. Fennis