Abstract: A computer program product is provided for performing input/output (I/O) processing at a host computer system. The computer program product is configured to perform: generating an address control structure for each of a plurality of consecutive data transfer requests specified by an I/O operation, each address control structure specifying a location in the local channel memory of a corresponding address control word (ACW) that includes an Offset field indicating a relative order of a data transfer request; generating and storing in local channel memory at least one ACW specifying one or more host memory locations for the plurality of consecutive data transfer requests and including an Expected Offset field indicating a relative order of an expected data transfer request; receiving a transfer request from the network interface and comparing the Offset field and the Expected Offset field to determine whether the data transfer request has been received in the correct order.

Abstract: Disclosed are apparatus and methods for use in a USB device with multiple processors, allowing shared USB connectivity in the device. The disclosed apparatus and methods allow selective coupling of a first processor to a USB port of the device or to a USB hub operable to route a plurality of USB connections including connection of a second processor to the port. Providing selective coupling of the processors to the port by switching the coupling of the first processor and selectively powering the hub on and off for selective coupling of the second processor, thereby selectively enabling tethered networking such as wireless networking, affords increased power savings in the device. Furthermore, default coupling of the first processor to the port allows for USB battery charger detection, or direct connectivity to USB peripheral devices, as well as providing programming capability via the default coupling of the port to the first processor.

Abstract: A computer program product is configured for performing a method including: receiving at least one command message specifying an I/O operation at a control unit from a channel subsystem, the at least one command message including one or more device command words (DCWs) having a data count and a suppress-length indication (SLI), the SLI configured to instruct the control unit whether to continue to perform the I/O operation in response to the control unit detecting an incorrect length condition; processing at least one of the one or more DCWs; and returning a transport response message including an incorrect length (IL) value, the IL value being a first IL value in response to the SLI being a first SLI value and the data count not matching the amount of data required, the IL value being a second IL value in response to the SLI being a second SLI value and the data count not matching the amount of data required.

Abstract: A computer program product is provided for performing an input/output (I/O) processing operation at a host computer system. The computer program product is configured to perform: obtaining a transport command word (TCW) at a channel subsystem for an I/O operation, the TCW including an address of a transport command control block (TCCB) having a transport command area (TCA) configured to hold a first plurality of device command words (DCW) and control data associated with respective DCWs, the first plurality of DCWs including a transfer TCA extension (TTE) DCW that specifies a TCA extension, the TCA extension configured to hold one or more DCWs and control data associated with respective DCWs; gathering the TCCB from one or more locations specified in the TCCB address and transferring the TCCB to the control unit; gathering the TCA extension specified by the TTE DCW; and transferring the TCA extension to the control unit.

Abstract: Techniques are disclosed for managing the flow of IO jobs from a client to a hardware device such that resource starvation is reduced without significantly impacting throughput. Each flow can be assigned an amount of time that a hardware device can deplete completing IO jobs from the client. When the allocated amount of time is used IO jobs associated with the client can be stored in a queue until the client obtains more time.

Abstract: A computer program product is configured for performing a method including: receiving at least one command message specifying an I/O operation at a control unit from a channel subsystem, the at least one command message including one or more device command words (DCWs) having a data count and a suppress-length indication (SLI), the SLI configured to instruct the control unit whether to continue to perform the I/O operation in response to the control unit detecting an incorrect length condition; processing at least one of the one or more DCWs; and returning a transport response message including an incorrect length (IL) value, the IL value being a first IL value in response to the SLI being a first SLI value and the data count not matching the amount of data required, the IL value being a second IL value in response to the SLI being a second SLI value and the data count not matching the amount of data required.

Abstract: A device and a method for testing a DMA controller. The device includes: (i) a DMA controller that includes a first data transfer path and a second data transfer path, wherein the first data transfer path and the second data transfer path are mutually independent; (ii) a test unit, connected to the first and second data transfer paths, that is adapted to control a transfer of data between the first data transfer path and the second data transfer path during a test mode, while masking from a first memory unit coupled to the DMA controller, at least one control signal associated with the transfer of data.

Abstract: In one embodiment of the invention, a memory system includes non-volatile-memory-devices (NVMDs) coupled to memory channels to share busses and a memory controller coupled to the memory channels in communication between the plurality of NVMDs. Each NVMD independently executes a read, write, or erase operation at a time. The memory controller includes channel schedulers to schedule control and data transfers associated with the read, write, and erase operations on the memory channels; and high priority and low priority queues coupled to the channel schedulers. The channel schedulers prioritize operations waiting in the high priority queues over operations waiting in the low priority queues. The channel schedulers further prioritize read operations waiting in either the high priority queue or the low priority queue over write and erase operations waiting in each respective queue.

Abstract: A serial peripheral interface of an integrated circuit including multiple pins is provided. The pins are coupled to the integrated circuit. The integrated circuit receives an instruction through only one of the plurality of pins. The integrated circuit receives an address through the plurality of pins. The integrated circuit sends a read out data through the plurality of pins.

Abstract: One embodiment of the present invention sets forth a technique for arbitrating requests received by an L1 cache from multiple clients. The L1 cache outputs bubble requests to a first one of the multiple clients that cause the first one of the multiple clients to insert bubbles into the request stream, where a bubble is the absence of a request. The bubbles allow the L1 cache to grant access to another one of the multiple clients without stalling the first one of the multiple clients. The L1 cache services multiple clients with diverse latency and bandwidth requirements and may be reconfigured to provide memory spaces for clients executing multiple parallel threads, where the memory spaces each have a different scope.

Abstract: A computer program product for procuring information from entities in a network via an Input/Output (I/O) processing system includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving, at a channel subsystem, at least one network topology information request from an operating system. The method also includes building at least one command request that includes the at least one network topology information request, and sending the at least one command request from the channel subsystem to at least one network entity. The method further includes receiving a response to the at least one command request from the at least one network entity by the channel subsystem, and forwarding the response from the channel subsystem to the operating system.

Abstract: Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer.

Abstract: A unique system and method for ordering commands may reduce disc access latency while giving preference to pending commands. The method and system involves giving preference to pending commands in a set of priority queues. The method and system involve identifying a pending command and processing other non-pending commands in route to the pending command if performance will not be penalized in doing so. The method and system include a list of command node references referring to a list of sorted command nodes that are to be scheduled for processing.

Abstract: A license issue system includes a user terminal and a license information issue server that are connected to a network. In the case in which there is a transfer source device in which license information issued by the license information issue server has been installed, and there is a transfer destination device that is to take over the license information installed in the transfer source device, the license issue system has the feature that the user terminal transmits, to the license information issue server, information regarding the transfer source device and the transfer destination device, and a license period during which the license can be used simultaneously in the transfer source device and the transfer destination device, and the license information issue server issues time-restricted license information to the transfer source device.

Abstract: A computer program product is provided for performing: sending, by a channel subsystem, a process login (PRLI) request message to the control unit that indicates whether the channel subsystem supports bi-directional data transfer; receiving a PRLI response message from the control unit that indicates whether the control unit supports bi-directional data transfer; gathering a plurality of commands, at least one which specifies an input data transfer and at least one specifying an output data transfer; sending at least one output data message to the control unit including output data to be transferred to the control unit, the output data message associated with the at least one of the plurality of commands specifying an output data transfer; and receiving at least one input message from the control unit including input data to be stored in a main storage of the host computer system.

Abstract: An aspect of the invention is a storage networking system comprising subsystems coupled with a network. The subsystems include an initiator subsystem having an initiator I/O (input/output) control unit, and a plurality of target subsystems each having a target I/O control unit. The initiator subsystem is configured to: place priority information in packet address of an I/O command packet, the priority information being based on a priority table; send the I/O command packet to one or more of the plurality of target I/O control units; and receive a return I/O packet from each of the target I/O control units that received the sent I/O command packet, the return I/O packet having the same priority information. The priority information provided in the priority table is priority of storing I/O data. The I/O data is transferred according to the priority information placed in the packet address of the I/O command packet.

Abstract: The present invention discloses a method for accessing multiple card slots and an apparatus for the same, which relate to data communication field. The method comprises establishing a connection from a CCID to a host, declaring at least a pair of IN/OUT endpoints used for implementing a response pipe and a command pipe as BULK-IN and BULK-OUT endpoints, declaring at least one IN endpoint used for implementing an event notification pipe as an interrupt endpoint, and declaring, by the CCID, the CCID itself as a device compliant with a CCID standard and the number of card slots supported by the CCID to the host; accessing the CCID by the host; receiving, by the CCID, a BULK-OUT packet and determining, by the CCID, a type of a CCID command issued by the host according to the BULK-OUT packet; in case the CCID command is a channel extension command, determining if it is a channel switch command; and if so, parsing the channel switch command and activating a card slot the host tries to access.

Abstract: An input/output (I/O) scheduling device comprises a plurality of trans-descriptor operators each corresponding to one of a plurality of hosts and configured to sustain a trans-descriptor and transmit the trans-descriptor to a hardware module, a transmitting scheduler configured to schedule transmission of trans-descriptors through communication with the plurality of trans-descriptor operators, and a receiving scheduler configured to schedule reception of trans-descriptors through communication with the trans-descriptor operators.

Abstract: There is provided a control system comprising: a master device that includes: a first transmission section that transmits, to a plurality of slave devices connected thereto through a network, a control command for the slave devices to control a device to be controlled and a flag that have two or more values; and a second transmission section that transmits, to the plurality of slave devices, a control start command for the slave devices to simultaneously start performing control based on the control command transmitted by the first transmission section, and a slave device that includes: a reception section that receives the control command and flag transmitted from the master device; a control command storage section that stores the control command received by the reception section in a storage section in the case where the flag received by the reception section has a specified value; and a first control start section that receives the control start command transmitted from the master device and starts perfor

Abstract: One or more embodiments provide a method and system of reading data from a variable-latency memory, via a serial input/output memory data interface. The system includes a memory having a variable-latency access time, a memory controller, and a serial data bus coupling the memory controller to the memory. The memory controller communicates a Read command to the memory and forces the serial data bus low for a limited time. The memory then forces the bus low and the memory controller then releases the bus. When the memory is ready to provide data, the memory provides a high signal on the serial data bus.

Abstract: A method, apparatus, system, and computer program product for enabling out-of-band access to storage devices through port-sharing hardware. Providing out-of-band access to storage devices enables system management functions to be performed when an operating system is non-functional as well as when the operating system is active. Storage commands originating with a management service can be interleaved with storage commands issued by the host operating system. The host operating system maintains ownership and control over its storage devices, but management activities can be performed while the host operating system is operational.

Abstract: A management apparatus and method that manage a storage system, in which an access node and a storage node, with which the management apparatus is in communication via the network. The management apparatus includes a logical volume judging unit that acquires a plurality of processing requests to each of the plurality of storage areas, references a logical volume allocation information storage unit that stores a correspondence relationship between the plurality of storage areas and the plurality of logical volumes in the storage node, and judges a logical volume corresponding to a storage area to become a processing object of each processing request, and a processing request breakdown calculating unit that counts an acquisition count of each processing request for each logical volume based on a judgment result by the logical volume judgment unit, and calculates a proportion of each acquisition count to a total of respective acquisition counts.

Abstract: One embodiment of the present invention sets forth a technique for processing cache misses resulting from a request received from one of the multiple clients of an L1 cache. The L1 cache services multiple clients with diverse latency and bandwidth requirements, including at least one client whose requests cannot be stalled. The L1 cache includes storage to buffer pending requests for caches misses. When an entry is available to store a pending request, a request causing a cache miss is accepted. When the data for a read request becomes available, the cache instructs the client to resubmit the read request to receive the data. When an entry is not available to store a pending request, a request causing a cache miss is deferred and the cache provides the client with status information that is used to determine when the request should be resubmitted.

Abstract: One embodiment of the present invention sets forth a technique for arbitrating requests received from one of the multiple clients of an L1 cache and for providing hints to the client to assist in arbitration. The L1 cache services multiple clients with diverse latency and bandwidth requirements and may be reconfigured to provide memory spaces for clients executing multiple parallel threads, where the memory spaces each have a different scope.

Abstract: An image processing apparatus includes a converter converting an interlace image including a first number of pixels into a first progressive image, an interpolator interpolating the first progressive image to generate a second progressive image including a second number of pixels, a classification unit classifying, in accordance with a feature of the second progressive image, into classes, subject pixels forming a third progressive image, which serves as a target image, including the second number of pixels and having a quality higher than the second progressive image, a storage unit storing a prediction coefficient for each of the classes obtained by conducting learning using a plurality of progressive images, each including the second number of pixels, and a computation unit performing computation using the second progressive image and the prediction coefficient for each of the classes to determine the third progressive image from the second progressive image.

Abstract: A signal associated with multiple haptic effects is received, each haptic effect from the multiple haptic effects being associated with a time slot from multiple time slots. Each haptic effect from the multiple haptic effects is associated with an effect slot from multiple effect slots at least partially based on the time slot associated with that haptic effect. An output signal is sent for each effect slot from the multiple effect slots, when the associated haptic effect is scheduled for its time slot.

Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

Abstract: Reordering the request queue of the hardware accelerator, wherein, the request queue stores therein a plurality of coprocessor request blocks (CRBs) to be input into the hardware accelerator. A content addressable memory is connected to the request queue for storing the state pointer of each CRB in the request queue at a same physical storage location in the request queue, receiving the state pointer of a new CRB in response to the new CRB asking to join in the request queue and outputting the physical storage location of a CRB in the request queue whose state pointer stored in the content addressable memory is the same as the state pointer of the new CRB.

Abstract: Shared memory device apparatus and related methods are disclosed. An example method includes obtaining memory operation commands. The memory operation commands are received by a command dispatcher in a same order as obtained by the queue arbiter from the host device. The example method further includes separately and respectively queuing the memory operation commands for each of a plurality of memory devices and dispatching the memory operation commands for execution. The example method also includes receiving the dispatched memory operation commands at a plurality of command queues, where each command queue is associated with a respective one of the plurality of memory devices. Each command queue is configured to receive its respective dispatched memory operation commands from the command dispatcher in a same order as received by the dispatcher and provide the received memory operation commands to its respective memory device in a first-in-first-out order.

Abstract: A method and system for automatically sharing a tape drive in a heterogeneous computing environment that includes a first computer and second computer. The first computer receives a message that includes a shared tape drive identifier, a source port identifier of the second computer, and a reservation status change for the tape drive. Based on the tape drive identifier, the first computer determines that the tape drive is connected to the first computer. The source port identifier is determined to not identify any host bus adapter installed in the first computer. In response to the first computer determining that the reservation status change indicates a reservation or a release of the tape drive for the second computer, the first computer sets the tape drive offline or online, respectively, in an application executing in the first computer.

Abstract: Techniques for generating information identifying a next direct memory access (DMA) task to be serviced. In an embodiment, arbitration logic provides a sequence of masking logic to determine, according to a hierarchy of rules, a next task to be serviced by a DMA engine. In certain embodiments, masking logic includes logic to mask information representing pending tasks to be serviced, the masking based on identification of a channel as being a suspended channel and/or a victim channel.

Abstract: Techniques are disclosed for managing data requests from multiple requestors. According to one implementation, when a new data request is received, a determination is made as to whether a companion relationship should be established between the new data request and an existing data request. Such a companion relationship may be appropriate under certain conditions. If a companion relationship is established between the new data request and an existing data request, then when data is returned for one request, it is used to satisfy the other request as well. This helps to reduce the number of data accesses that need to be made to a data storage, which in turn enables system efficiency to be improved.

Abstract: An apparatus for queuing and ordering commands for a data storage device may include a slot tracker module that is arranged and configured to track available slots for commands from a host, a command transfer module that is operably coupled to the slot tracker module and that is arranged and configured to retrieve commands from the host based on a number of the available slots, a pending command module that is operably coupled to the command transfer module and that is arranged and configured to queue and order the commands from the host for processing using an ordered list that is based on an age of the commands and a task dispatch module that is operably coupled to the pending command module and that is arranged and configured to dispatch the commands for processing using the ordered list from the pending command module and an availability of storage locations.

Abstract: A technique for maintaining input/output (I/O) command ordering on a bus includes assigning a channel identifier to I/O commands of an I/O stream. In this case, the channel identifier indicates the I/O commands belong to the I/O stream. A command location indicator is assigned to each of the I/O commands. The command location indicator provides an indication of which one of the I/O commands is a start command in the I/O stream and which of the I/O commands are continue commands in the I/O stream. The I/O commands are issued in a desired completion order. When a first one of the I/O commands does not complete successfully, the I/O commands in the I/O stream are reissued on the bus starting at the first one of the I/O commands that did not complete successfully.

Abstract: In general, techniques are described for performing work conserving packet scheduling in network devices. For example, a network device comprising queues that store packets and a control unit may implement these techniques. The control unit stores data defining hierarchically-ordered nodes, which include leaf nodes from which one or more of the queues depend. The control unit executes first and second dequeue operations concurrently to traverse the hierarchically-ordered nodes and schedule processing of packets stored to the queues. During execution, the first dequeue operation masks at least one of the selected ones of the leaf nodes from which one of the queues depends based on scheduling data stored by the control unit. The scheduling data indicates valid child node counts in some instances. The masking occurs to exclude the node from consideration by the second dequeue operation concurrently executing with the first dequeue operation, which may preserve work in certain instances.

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

Abstract: Techniques for rendering the management of processes supported by a storage device are described. In particular, the efficient allocation of storage array processing resources when managing concurrent processes on a storage array is described.

Abstract: A computer readable storage medium includes executable instructions to assess system cache resources, inter-process communication requirements and staging requirements to divide an extract, transform, load (ETL) dataflow task into a plurality of sub-tasks. The sub-tasks are then executed in parallel on distributed resources.

Abstract: An adaptive bus profiler is described. In embodiment(s), data traffic that is communicated on an adaptive bus can be monitored, and projected data traffic that is scheduled for communication via the adaptive bus can be determined. An adaptive bus profile can be determined based on the data traffic and the projected data traffic. A reconfiguration of a bus width of the adaptive bus can be initiated based on the adaptive bus profile.

Abstract: Methods and apparatuses for delaying execution of input/output (I/O) requests for solid state drives are contemplated. Some embodiments comprise receiving I/O requests for a solid state drive and calculating amounts of time based on characteristics of the requests, such as differences of the logical block addresses (LBAs) of the requests. The embodiments may then delay responses by the solid state drive for the requests. Calculating the amounts of time and delaying the responses by the amounts of time may allow the solid state drives to emulate the responses of various types of hard disk drives. Some embodiments comprise an apparatus for delaying execution of the I/O requests for solid state drives. The apparatuses may have numerous modules, such as a request receiver to receive the I/O requests, a calculation module to calculate the amounts of delay times, and a delay module to delay the responses of the I/O requests.

Abstract: To reduce power consumption, a data transmission apparatus comprises: a memory; a timing instruction unit which indicates a start timing of outputting data from the memory; a first interface which outputs data stored in the memory according to the timing instruction unit; a second interface which transfers the data from the first interface to a buffer; and a control unit which issues a command to perform transition of the first interface and the second interface to a power saving state based on the data output start timing indicated by the timing instruction unit, and a sum of a time required to perform transition of the first interface and the second interface to the power saving state and a time required to return from the power saving state.

Abstract: Architecture that allows programmatic association of devices to sessions and redirects input to the desired session. When the solution is active, input from the devices is not realized by the standard operating system input stack, thereby allowing even reserved key sequences such as Ctrl-Alt-Del to be intercepted and redirected to a desired session. Moreover, in addition to redirecting input to a specific session, the architecture facilitates the filtering of input from unwanted/unmapped devices, the interception and filtering or redirection of reserved key sequences such as Ctrl-Alt-Del, and the maintenance of input state for each session.

Abstract: A method of controlling an apparatus including a processor and an I/O controller includes storing execution information, receiving a first and a second requests successively, determining whether initiation of each execution of the first and the second requests is to be supervised by either of the processor and the I/O controller in reference to the execution information, transmitting the first request to the processor from the I/O controller, and upon completion of execution of the first request at the processor, transmitting the second request to the processor from the I/O controller when the initiations of executions of the first and second request is supervised by the I/O controller, and transmitting the first and second requests to the processor regardless of completion of execution of the first request by the processor when the initiations of executions of the first and second requests is supervised by the processor.

Abstract: A data communication system is provided. The data communication system includes a main processor, and at least one sub-processor or at least one peripheral device connected with the main processor according to a serial peripheral interface (SPI) method and performing an operation corresponding to a command transferred from the main processor. The connection according to the SPI method is made by one or more bus lines including a master in slave out (MISO) line and master out slave in (MOSI) line, a slave select (SS) line, an interrupt line, and a clock transfer line.

Abstract: A system, method, and computer readable medium. A method includes setting a maximum translation delay. The method includes, while a current delay is less than the maximum transfer delay, repeatedly performing the steps of searching for an additional transfer having a same source and target as a current transfer, and when an additional transfer is found, adding the additional transfer to a transfer list that identifies transfers to be made together. The method includes performing a transfer of the transfers identified by the transfer list when the current delay has met or exceeded the maximum transfer delay.

Abstract: The peripheral device management system includes a server, a peripheral device, a data processing device. The data processing device includes an attempting unit, a confirming unit, a notifying unit, a first setting unit, and a second setting unit. The attempting unit attempts to acquire, from the peripheral device, firmware data. The confirming unit confirms, to the server, whether a newer firmware than the firmware installed on the peripheral device is available for downloading from the server. The notifying unit notifies that the newer firmware is available for downloading from the server. The first setting unit sets a first confirmation time as the confirmation time if a result of the attempting unit satisfies a prescribed condition. The second setting unit sets a second confirmation time that precedes the first confirmation time as the confirmation time if the result of the attempting unit does not satisfy the prescribed condition.

Abstract: A direct memory access (DMA) engine schedules data transfer requests of a system-on-chip data processing system according to both an assigned transfer priority and the deadline for completing a transfer. Transfer priority is based on a hardness representing the penalty for missing a deadline. Priorities are also assigned to zero-deadline transfer requests in which there is a penalty no matter how early the transfer completes. If desired, transfer requests may be scheduled in timeslices according to priority in order to bound the latency of lower priority requests, with the highest priority hard real-time transfers wherein the penalty for missing a deadline is severe are given the largest timeslice. Service requests for preparing a next data transfer are posted while a current transaction is in progress for maximum efficiency. Current transfers may be preempted whenever a higher urgency request is received.

Abstract: An electronic device that supports multiple command systems embodies a function for switching from one to another of the multiple command systems regardless of the specifications of the command system being used. A hybrid device 10 that operates based on commands sent from a host computer 200 sets a specific transition condition for changing to another command system after the last command system change corresponding to a switching command sent from the host computer 200. When the set transition condition is met, the computer returns to the command system used before the command system was last changed or changes to another command system.

Abstract: A plurality of command storage areas respectively corresponding to a plurality of priorities and storing I/O commands in a storage control apparatus are common to a plurality of ports and a plurality of processors. Here, regardless of which port receives an I/O command, the I/O command is stored in a command storage area corresponding to a priority which is given to the I/O command. The plurality of processors run the I/O commands in the plurality of command storage areas so that an I/O command with a higher priority is run more often within a given period of time.