Abstract: Automated management of shared I/O resources involves use of a policy engine for implementing I/O scheduling group I/O policies. The I/O policies are used for determining whether corresponding I/O requests should be issued to a shared storage system immediately or should be delayed via corresponding policy-based queues. In the context of database systems, a database administrator can specify policies regarding how I/O resources should be used and the database system itself enforces the policies, rather than requiring the database administrator enforce the I/O usage of the database and of the individual users.

Abstract: The disclosed embodiments provide a system that facilitates the processing of commands in a set of devices. The system includes a host bus adapter that provides an interface for connecting the set of devices to the host and manages the allocation of a set of tags to one or more of the devices. For each device connected to the host, the system also includes a queue-management apparatus that sends a tag request for the device to the host bus adapter. The queue-management apparatus then receives a subset of the tags for the device from the host bus adapter and uses the set of tags to queue commands from the host to the device and track the status of the queued commands.

Abstract: This disclosure describes a system and method for providing I/O scheduling capabilities to a host server executing one or more virtual machine clients and communicating with a cloud-based storage array. An I/O scheduler executing on a virtual machine can identify priority tags associated with requests or commands on the virtual machine. The I/O scheduler can create one or more queues based upon the priority of each request, and can then transmit requests in order of priority. The I/O scheduler can also use information about the storage array, such as layout information or cache information, and can accordingly optimize the transmission of requests to the storage array.

Abstract: An apparent load is determined based on assigning weightings to commands based on various factors including, but not limited to, the limitations of the underlying storage media device(s), where the command queue fullness is viewed from that perspective rather than simply the number of commands outstanding in a storage media device. Also disclosed is the use of a positive bias and a negative bias to artificially influence the apparent load where such a positive bias and/or negative bias may be used to influence temperature of storage media devices.

Abstract: An apparent load is determined based on assigning weightings to commands based on various factors including, but not limited to, the limitations of the underlying storage media device(s), where the command queue fullness is viewed from that perspective rather than simply the number of commands outstanding in a storage media device. Also disclosed is the use of a positive bias and a negative bias to artificially influence the apparent load to influence where a particular data type gets stored.

Abstract: An apparent load is determined based on assigning weightings to commands based on various factors including, but not limited to, the limitations of the underlying storage media device(s), where the command queue fullness is viewed from that perspective rather than simply the number of commands outstanding in a storage media device. Also disclosed is the use of a positive bias and a negative bias to artificially influence the apparent load based on write rate of storage media devices.

Abstract: An apparent load is determined based on assigning weightings to commands based on various factors including, but not limited to, the limitations of the underlying storage media device(s), where the command queue fullness is viewed from that perspective rather than simply the number of commands outstanding in a storage media device. Also disclosed is the use of a positive bias and a negative bias to artificially influence the apparent load where such a positive bias and/or negative bias may be used to influence temperature ranges associated with storage media devices.

Abstract: Techniques for providing an interface between a UICC and a processor, included in an access terminal, that supports asynchronous command processing by the UICC, are described. A first complex command, with a first processing time, may be received from the processor. An initial response to the first command, including a token, may be sent to the processor. The first command may be processed for the first processing time. At least one additional command, having a processing time shorter than the first processing time, may be received from the processor. Processing of the first command may be completed. Processing of a current one of the at least one additional command, which was being processed before, during, or after completion of the processing of the first command, may be completed. A response to the current one of the at least one additional command, including the token, may be sent to the processor.

Abstract: Systems, mediums, and methods are provided for scheduling input/output requests to a storage system. The input output requests may be received, categorized based on their priority, and scheduled for retrieval from the storage system. Lower priority requests may be divided into smaller sub-requests, and the sub-requests may be scheduled for retrieval only when there are no pending higher priority requests, and/or when higher priority requests are not predicted to arrive for a certain period of time. By servicing the small sub-requests rather than the entire lower priority request, the retrieval of the lower priority request may be paused in the event that a high priority request arrives while the lower priority request is being serviced.

Abstract: Improving the performance of multitasking processors are provided. For example, a subset of M processors within a Symmetric Multi-Processing System (SMP) with N processors is dedicated for a specific task. The M (M>0) of the N processors are dedicate to a task, thus, leaving (N-M) processors for running normal operating system (OS). The processors dedicated to the task may have their interrupt mechanism disabled to avoid interrupt handler switching overhead. Therefore, these processors run in an independent context and can communicate with the normal OS and cooperation with the normal OS to achieve higher network performance.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a buffer configured to hold data input to an input/output circuit and to hold data read from the memory cell array, and a controller configured to receive a first command and an address from the outside and to read data, in response to the first command, from a memory cell group coupled to a selected word line designated by the address to the buffer. The controller receives a second command which is input after the first command and indicates a last command of a group of commands including write commands and/or read commands, and starts a write operation from the buffer to the memory cell array in response to the second command.

Abstract: The disclosed packet scheduler implements the deficit round robin (DRR) approximation of weighted fair queuing (WFQ), and is capable of achieving complete fairness across several hundred source flows, for example, each of which can be mapped to one of several destination ports. In addition to achieving fairness, the packet scheduler allows the user to map one or more optional strict-priority flows to each port. The packet scheduler keeps these strict-priority flows “outside” of the group of flows for which fairness is enforced. Each destination port can be optionally configured to chop its data packets into sub-packet pieces. The packet scheduler works in two mutually orthogonal dimensions: (1.) it selects destination ports based on a round-robin scheme, or using another method, such as guaranteed rate port scheduling (GRPS), and (2.) it implements optional strict-priority scheduling, and DRR scheduling.

Abstract: A peripheral interface for use with a control computer and a peripheral device. The peripheral interface has a controller receiving an input data stream from the control computer and delivering an output data stream to the peripheral device, the controller obtaining an instruction from the input data stream for a modification of the output data stream. Prior art devices transfer data streams for peripheral devices blockwise by means of DMA using peripheral interfaces. In conventional peripheral interfaces, a burdensome real-time operating system must be used on the control computer in order have a sufficiently short reaction time to bring about a continuous, uninterrupted data stream. The invention achieves the object using a non-real-time operating system.

Abstract: Described herein are systems and methods for improving concurrency of a request manager for use in an application server or other environment. A request manager receives a request, and upon receiving the request the request manager associates a token with the request. A reference to the request is enqueued in each of a plurality of queues, wherein each queue stores a local copy of the token. A first reference to the request is dequeued from a particular queue, wherein when the first reference to the request is dequeued, the token is modified to create a modified token. Thereafter the request is processed. When other references to the request are dequeued from other queues, the other references to the request are discarded.

Abstract: A data processing device includes a plurality of devices, a processor core, a memory, and a queue manager. The processor core stores one or more commands in a command queue of the memory to be executed by the plurality of devices to implement a data transfer path. The queue manager stores a frame queue for each of the plurality of devices. Each frame queue includes a first field having a pointer to an address of the command queue, and a second field to identify a next-in-sequence frame queue. A first device stores a data descriptor in the frame queue of the second device to initiate a data transfer from the first device to the second device. The data descriptor includes a field to indicate an offset value from the address of the command queue to a location of a command to be executed by the second device.

Abstract: A signal associated with multiple haptic effects is received, each haptic effect from the multiple haptic effects being associated with a time slot from multiple time slots. Each haptic effect from the multiple haptic effects is associated with an effect slot from multiple effect slots at least partially based on the time slot associated with that haptic effect. An output signal is sent for each effect slot from the multiple effect slots, when the associated haptic effect is scheduled for its time slot.

Abstract: A method of implementing a logical unit reset across a plurality of interfaces in a distributed storage system, comprising: initiating a session for implementing the logical unit reset across the plurality of interfaces in response to receiving at a central controller a logical unit reset command from an originator interface, and writing session-data including an indication that the originator interface implemented the respective logical unit reset locally; communicating a logical unit reset command from the central controller to each interface other than the originator interface; updating the session data in response to receiving an indication from an interface that the logical unit was successfully reset locally and when each one of the plurality of interfaces implemented the logical unit reset locally, communicating a success response to each one of the plurality of interfaces.

Abstract: A method for managing storage space in a storage port queue includes establishing a watermark for the storage port queue. The method further receives, at the storage port associated with the storage port queue, a command having an initiator-target-LUN (ITL) nexus associated therewith. Upon receiving the command, the method determines whether the used space in the storage port queue has reached the watermark. In the event the used space has not reached the watermark, the method processes the command. In the event the used space has reached the watermark and a specified number of commands for the ITL nexus are already present in the storage port queue, the method rejects the command. Otherwise, the method may process the command.

Abstract: A method for managing storage space in a storage port queue includes establishing a watermark for the storage port queue. The method further receives, at the storage port associated with the storage port queue, a command having an initiator-target-LUN (ITL) nexus associated therewith. Upon receiving the command, the method determines whether the used space in the storage port queue has reached the watermark. In the event the used space has not reached the watermark, the method processes the command. In the event the used space has reached the watermark and a specified number of commands for the ITL nexus are already present in the storage port queue, the method rejects the command. Otherwise, the method may process the command. A corresponding apparatus and computer program product are also disclosed herein.

Abstract: Data-transfer transactions in the read and write directions may be balanced by taking snapshots of the transactions stored in a buffer, and executing transactions in the same direction back-to-back for each snapshot.

Abstract: A method, computer program product, and computing system for associating a first I/O scheduling queue with a first process accessing a storage network. The first I/O scheduling queue is configured to receive a plurality of first process I/O requests. A second I/O scheduling queue is associated with a second process accessing the storage network. The second I/O scheduling queue is configured to receive a plurality of second process I/O requests.

Abstract: Data-transfer transactions from multiple masters may be balanced by taking snapshots of the transactions stored in a buffer, and executing transactions from each master back-to-back.

Abstract: Registry information systems and methods are presented. In one embodiment, an application dedicated registry hive method comprises: performing application dedicated registry hive agent operations, including: an online initiation phase in which a system independent application dedicated registry hive from a shared resource is loaded into the system namespace; a monitoring phase in which status of the system independent application dedicated registry hive is monitored; and an offline initiation phase in which the system independent application dedicated registry hive is unloaded from the system namespace; and performing an application dedicated registry hive driver filter process, including redirecting read and write operations to the system independent application dedicated registry hive. The system independent application dedicated registry hive can include a registry content file and a corresponding transaction log file.

Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

Abstract: This disclosure describes embodiments of systems and methods for performing inspections of an asset. The systems can include an inspection apparatus that executes a menu directed inspection (MDI) protocol to direct an inspector that performs the inspection. The MDI protocol includes, in one example, reference material that is associated with areas of the asset that the inspector will inspect. This reference material can include data and information (e.g., technical manuals, operating manuals, images, etc.). In one embodiment, the method includes one or more steps for building an inspection tree with inspection points that correspond to the inspection areas on the asset. The method can also comprise steps for assigning or associating the reference material to inspection points, which is then available to the inspector on the inspection apparatus during execution of the MDI protocol.

Abstract: Controlling I/O operations with a storage device includes establishing a quota that corresponds to a maximum amount of data to store on the storage device in a given amount of time, determining if processing an I/O operation would cause the quota to be exceeded, and performing the I/O operation if the quota is not exceeded. The quota may be provided in I/O operations per second or as I/O throughput. Controlling I/O operations with a storage device may also include accumulating credit in response to a rate of I/O operations being less than the quota and performing I/O operations when the quota is exceeded in response to the credit being greater than zero. The credit may be decreased if an I/O operation is performed when the quota is exceeded.

Abstract: A method of prioritizing data transmissions between a SCSI initiator and a SCSI target in a network system with DCB enabled switches. The method includes a switch controller detecting a SCSI set priority response transmitted via a first pair of switch ports from a SCSI target to a SCSI initiator, which communicate SCSI messaging and transmit I/O data via the first pair of switch ports. In response to detecting the SCSI set priority response, the priority data established by the SCSI target is retrieved and, based on the retrieved priority data, the switch controller autonomously sets the DCB priority for the first pair of switch ports to a first DCB priority value correlated to the retrieved priority data. Transmission of the I/O data between the SCSI initiator and the SCSI target is supported with a priority of the first pair of switch ports set to the first DCB priority value.

Abstract: A data storage device accepts read and write commands with absolute command completion times based on queue-depth-of-one (qd=1) execution and stores them in an unsequenced commands memory. These commands are requests to access the data storage device and contain both locations on the storage medium where the data is located and whether the requested operation is read or write. For each pair of first and second commands in the memory, the time between execution of the first command and the second command is calculated and stored. A command selector then reads data from the memory based on a resequencing NCQ algorithm which inserts one or more commands from the command memory into the original qd=1 sequence whenever this insertion will not affect the execution time of commands in the original qd=1 sequence. The resequencing algorithm of the present invention increases IOPS and reduced read head actuator travel and wear.

Abstract: A method for regulating I/O requests in a RAID storage system may comprise: receiving a first request to access a first set of one or more logical block addresses (LBAs) of a RAID volume; receiving a second request to access at least one of the first set of one or more LBAs of the RAID volume; and queuing the second request. A system for regulating I/O requests in a RAID storage system may comprise: means for receiving a first request to access a first set of one or more logical block addresses (LBAs) of a RAID volume; means for receiving a second request to access at least one of the first set of one or more LBAs of the RAID volume; and means for queuing the second request.

Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.

Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more cross-channel work requests that are derived from an operation to be executed by the node. The NI includes a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the cross-channel work requests via the host interface, and to execute the cross-channel work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.

Abstract: An electronic measuring device includes a detection channel module, a sampling module, a control unit, a data path selector and a memory device. A user will be able to selectively enable the desired detection channels and store only data collected from enabled channels. The data collected from the detection channels are in serial data form. The device utilizes a serial-parallel shifter in its sampling module to convert the serial data to parallel data bytes. Two indicators in the storage unit of the memory device allow users to effectively store the parallel data bytes in designated locations. The innovative data conversion and storage methods of this invention will significantly conserve memory space that otherwise will be occupied by data from the disabled channels and allow accurate and efficient reading of the stored data.

Abstract: A storage device includes a memory; and a processor coupled to the memory, wherein the processor executes a process comprising: calculating an upper limit value of the number of input/output processings determined based on priority set to an information processing device, a port that is an interface between the information processing device and the storage device and a memory device of the storage device; scheduling an execution order of input/output processings based on the number of input/output processings received from the information processing device and the calculated upper limit value; and executing the input/output processings in the scheduled execution order.

Abstract: A system architecture that provides an exchange of runtime functionalities, the system architecture includes a first computing element operating to execute a first software stack to operate a first system; and a second computing element operating to execute a second software stack to operate a second system; wherein the first and second software stacks are configured to couple to each other at one or more data layers in the first and second software stacks to exchange functionalities between the first and second software stacks.

Abstract: In one example, multimedia content is requested from a plurality of storage modules. Each storage module retrieves the requested parts, which are typically stored on a plurality of storage devices at each storage module. Each storage module determines independently when to retrieve the requested parts of the data file from storage and transmits those parts from storage to a data queue. Based on a capacity of a delivery module and/or the data rate associated with the request, each storage module transmits the parts of the data file to the delivery module. The delivery module generates a sequenced data segment from the parts of the data file received from the plurality of storage modules and transmits the sequenced data segment to the requester.

Abstract: This invention relates to a communication system including a first apparatus having a first storage medium, and a second apparatus for transmitting data to the first apparatus, the second apparatus comprising: a second storage medium for storing management information of data to be transferred to the first storage medium; communication means for communicating data with the first apparatus; edit means capable of editing the management information; and control means for making a control to transfer data stored in the second storage medium to the first storage medium by way of the communication means on the basis of the management information edited by the edit means.

Abstract: In one embodiment, a computer system, comprises at least one host node, at least one input/output node coupled to the host node, at least one multi-function device coupled to the input/output node via a switch, and a middle manager processor comprising logic to block an enumeration process in a host node for the multi-function devices behind the switch hierarchy, initiate an enumeration process for the multi-function devices in a manager processor separate from the host node, store a routing table for the switch hierarchy in a memory module coupled to the manager processor, and allocate, in the manager processor, endpoint device resources to the host node.

Abstract: A method and apparatus, such as multi-engine controller that can be used to control multiple data processing engines in a command based IO processing system, such as a storage controller, to solve to the problem of scaling the data processing rate to match the advances in the IO interface data rates, including a method of identifying dependencies among various tasks queued up in the system and scheduling tasks out-of-order to avoid head of line blocking, a method to buffer and reorder the completed tasks such that the task output order is the same as that in the input to the system.

Abstract: A method of performing an input/output (I/O) processing operation includes: generating an address control structure for each of a plurality of consecutive data transfer requests, each address control structure specifying a local channel memory location of a corresponding address control word (ACW); receiving a data transfer request from a network interface that includes addressing information specified by a corresponding address control structure; comparing, by a data router in the channel, an Offset field of an address control structure and an Expected Offset field of an ACW to determine whether the data transfer request has been received in the correct order; and based on determining that the data transfer request has been received in the correct order, accessing the ACW by the data router and routing the data transfer request to a host memory location specified in the ACW.

Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

Abstract: A method, apparatus, and system of a priority command queues for low latency solid state drives are disclosed. In one embodiment, a system of a storage system includes a command sorter to determine a target storage device for at least one of a solid state drive (SSD) command and a hard disk drive (HDD) command and to place the command in a SSD ready queue if the SSD command is targeted to a SSD storage device of the storage system and to place the HDD command to a HDD ready queue if the HDD command is targeted to an HDD storage device of the storage system, a SSD ready queue to queue the SSD command targeted to the SSD storage device, and a HDD ready queue to queue the HDD command targeted to the HDD storage device.

Abstract: Systems and methods for indication of activity status of a storage device is described. In one embodiment, an exemplary method comprises receiving, from a digital device, a status request requesting availability of a storage device, determining if one or more background tasks are being performed by the storage device, determining if one or more background tasks are pending to be performed by the storage device, generating a level of urgency indicator based on the determination of the one or more background tasks that are being performed and the determination of the one or more background tasks that are pending to be performed by the storage device, and providing the level of urgency indicator to the digital device.

Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

Abstract: An apparatus for processing data includes a plurality of signal processing units, each signal processing unit including a register that stores identification (ID) information to store a parameter, the signal processing units operative to sequentially perform an operation of storing the parameter or an operation of processing a signal in response to a mode control signal; a storage unit; a data reading unit that selectively reads parameter information or processing data from the storage unit; a data writing unit that selectively writes data corresponding to a data signal output by each of the signal processing units in the storage unit; and a control unit that outputs the mode control signal to each of the signal processing units. During the operation of storing the parameter, when the data signal corresponds to the ID information, each of the signal processing units writes a parameter included in the data signal in the register.

Abstract: Some of the embodiments of the present disclosure provide a method comprising categorizing each data packet of a plurality of data packets into one of at least two priority groups of data packets; and controlling transmission of data packets of a first priority group of data packets during a first off-time period such that during the first off-time period, data packets of the first priority group of data packets are prevented from being transmitted to a switching module from one or more server blades. Other embodiments are also described and claimed.

Abstract: A method, computer program product, and computing system for associating a first I/O scheduling queue with a first process accessing a storage network. The first I/O scheduling queue is configured to receive a plurality of first process I/O requests. A second I/O scheduling queue is associated with a second process accessing the storage network. The second I/O scheduling queue is configured to receive a plurality of second process I/O requests.

Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

Abstract: Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer.

Abstract: A queue number acquiring unit acquires a command queuing number that is the upper limit of the number of process-waiting instructions that can be stored in each of storages that make up a virtual disk for each storage. A minimum queue number selecting unit selects the minimum value of the command queuing numbers of the storages that make up the virtual disk as a minimum queue number. A queue number setting unit sets the selected minimum queue number as the command queuing number of the virtual disk that includes the storage device of which the command queuing number is selected as the minimum queue number for each virtual disk.

Abstract: A disclosed data transfer device includes one or more data transfer control unit configured to control a command issuance and a data transfer separately, a command issuing unit configured to determine priorities of commands and issue the commands in an order from a higher priority, a memory communication control unit configured to perform the data transfer corresponding to the command from and to a memory, and a signal output unit configured to output a completion signal of the data transfer in a case where the data transfer is normally completed. The command issuing unit sets a priority of a command corresponding to a request for resetting the data transfer control unit lower than the priority of the command issued by the data transfer control unit when the request for resetting is received, and the signal output unit outputs a dummy completion signal to the memory communication control unit.