Abstract: An input tracker learns relationships between end user inputs made at a computer and external environment conditions sensed at the computer by external environment sensors integrated in the computer, such as a camera, microphone, hard disk drive motion detector, display ambient light sensor and display orientation accelerometer. An input predictor interfaced with the input tracker applies current external environment conditions sensed by the external environment sensors to the relationships defined by the input tracker to predict future user input and initiates actions by the computer responsive to the predicted future user input before the input is detected to have results responsive to the input prepared for the user upon detection of the input.

Abstract: Data-transfer transactions in the read and write directions may be balanced by taking snapshots of the transactions stored in a buffer, and executing transactions in the same direction back-to-back for each snapshot.

Abstract: Data-transfer transactions from multiple masters may be balanced by taking snapshots of the transactions stored in a buffer, and executing transactions from each master back-to-back.

Abstract: An input tracker learns relationships between end user inputs made at a computer and external environment conditions sensed at the computer by external environment sensors integrated in the computer, such as a camera, microphone, hard disk drive motion detector, display ambient light sensor and display orientation accelerometer. An input predictor interfaced with the input tracker applies current external environment conditions sensed by the external environment sensors to the relationships defined by the input tracker to predict future user input and initiates actions by the computer responsive to the predicted future user input before the input is detected to have results responsive to the input prepared for the user upon detection of the input.

Abstract: A method and apparatus, such as multi-engine controller that can be used to control multiple data processing engines in a command based IO processing system, such as a storage controller, to solve to the problem of scaling the data processing rate to match the advances in the IO interface data rates, including a method of identifying dependencies among various tasks queued up in the system and scheduling tasks out-of-order to avoid head of line blocking, a method to buffer and reorder the completed tasks such that the task output order is the same as that in the input to the system.

Abstract: A method for reusing certified software applications without recertification is provided. The method includes creating a virtual machine, that includes at least one of the software applications, the virtual machine including an operating system and at least one interface, certifying the virtual machines, and deploying the certified virtual machine in at least one representation of an underlying hardware platform.

Abstract: Optimizing a parallel build of an application includes, in parallel execution of commands, recording command sequence numbers and access information of the commands and detecting an execution conflict based on the command sequence numbers and the access information of the commands using a processor. Commands involved in the execution conflict are re-executed serially.

Abstract: A prefetch controller implements an upgrade when a real read access request hits the same memory bank and memory address as a previous prefetch request. In response per-memory bank logic promotes the priority of the prefetch request to that of a read request. If the prefetch request is still waiting to win arbitration, this upgrade in priority increases the likelihood of gaining access generally reducing the latency. If the prefetch request had already gained access through arbitration, the upgrade has no effect. This thus generally reduces the latency in completion of a high priority real request when a low priority speculative prefetch was made to the same address.

Abstract: An apparatus comprises a memory device to store a pre-generated Universal Serial Bus (USB) command before a USB peripheral device is coupled to a USB. The apparatus also includes a processing device to retrieve the pre-generated USB command from the memory device and transmit the pre-generated USB command to the USB peripheral device over the USB. A method comprises identifying a Universal Serial Bus (USB) peripheral device is coupled to a USB. The USB peripheral device is coupled to the universal serial bus after a pre-generated USB command is stored in a memory device. The method further includes transmitting the pre-generated USB command to the USB peripheral device over the USB in response to identifying the USB peripheral device is coupled to the USB.

Abstract: Systems and methods for enhancing multimedia experience are disclosed. A system includes a multimedia device adapted to obtain a multimedia data stream comprising multimedia data and at least one multimedia enhancement data sequence, and adapted to obtain instructions from a multimedia enhancement data sequence. The system further includes auxiliary devices communicatively coupled to the multimedia device, and adapted to receive the instructions from a multimedia device. The multimedia enhancement data sequences each include a start section, a target section, an instruction section, and an end section. A multimedia device is adapted to send instructions to at least one auxiliary device. A method includes obtaining a multimedia data stream comprising multimedia data and at least one multimedia enhancement data sequence using a multimedia device, obtaining instructions from a multimedia enhancement data sequence, and sending instructions to auxiliary devices communicatively coupled to the multimedia device.

Abstract: A data storage device accepts read and write commands with absolute command completion times based on queue-depth-of-one (qd=1) execution and stores them in an unsequenced commands memory. These commands are requests to access the data storage device and contain both locations on the storage medium where the data is located and whether the requested operation is read or write. For each pair of first and second commands in the memory, the time between execution of the first command and the second command is calculated and stored. A command selector then reads data from the memory based on a resequencing NCQ algorithm which inserts one or more commands from the command memory into the original qd=1 sequence whenever this insertion will not affect the execution time of commands in the original qd=1 sequence. The resequencing algorithm of the present invention increases IOPS and reduced read head actuator travel and wear.

Abstract: An apparatus for assigning priority to applications for execution by a hardware resource according to the priority may include a processor and memory storing executable computer program code that cause the apparatus to at least perform operations including assigning priority information to a plurality of applications based in part on receipt of one or more indications specifying a priority of the applications. The computer program code may further cause the apparatus to determine that at least one hardware resource executes commands of at least a subset of the applications. The computer program code may further cause the apparatus to enable the hardware resource to execute one or more of the commands associated with a first application of the subset assigned a higher priority prior to execution of commands associated with at least another application of the subset assigned a lower priority. Corresponding methods and computer program products are also provided.

Abstract: Methods and systems provide a burst access protocol that enables efficient transfer of data between a first and a second processor via a data interface whose access set up time could present a communication bottleneck. Data, indices, and/or instructions are transmitted in a static table from the first processor and stored in memory accessible to the second processor. Later, the first processor transmit to the second processor a dynamic table which specifies particular data, indices and/or instructions within the static table that are to be implemented by the second processor. The second processor uses the dynamic table to implement the identified particular subset of data, indices and/or instructions. By transmitting the bulk of data, indices and/or instructions to the second processor in a large static table, the burst access protocol enables efficient use of data interfaces which can transmit large amounts of information, but require relatively long access setup times.

Abstract: A semiconductor device correctly switches endian modes regardless of the current endian mode of an interface. The semiconductor device includes a switching circuit and a first register. The switching circuit switches an interface to be used in big endian or little endian mode. The first register holds control data of the switching circuit. The switching circuit sets the interface in little endian mode when first predetermined control information is supplied to the first register, and sets the interface in big endian mode when second predetermined control information is supplied to the first register. The control information can be correctly inputted without being influenced by the endian setting status.

Abstract: A method and apparatus, such as multi-engine controller that can be used to control multiple data processing engines in a command based IO processing system, such as a storage controller, to solve to the problem of scaling the data processing rate to match the advances in the IO interface data rates, including a method of identifying dependencies among various tasks queued up in the system and scheduling tasks out-of-order to avoid head of line blocking, a method to buffer and reorder the completed tasks such that the task output order is the same as that in the input to the system.

Abstract: An information processing apparatus registers, in a reservation list, transmission reservation data including a transmission start time and a transmission completion time of charging counter information that is a type of operation information to be regularly transmitted according to a predetermined cycle. The information processing apparatus then registers, in the reservation list, with respect to other types of the operation information to be regularly transmitted (e.g., firmware information), transmission reservation data including a transmission start time and a transmission completion time that are determined so that the operation information is regularly transmitted in a different period than regular transmission of operation information corresponding to transmission reservation data already registered in the reservation list.

Abstract: Disclosed herein is a deadlock avoidance circuit including: a previous-transaction-information management section; a transaction-issuance-termination determination section; and a response-outputting control section.

Abstract: An image processing apparatus includes an input unit configured to input a plurality of page data; a rendering unit configured to convert each of the plurality of page data into rendering data; a supply unit configured to supply the plurality of rendering data to a printing apparatus; an acquisition unit configured to acquire, for each of the plurality of rendering data, delay time from an end of printing of a last page to an end of conversion of rendering data used for next printing; and a scheduling unit configured to delay supply timing of rendering data converted first by the rendering unit among the plurality of page data based on the delay time of the plurality of rendering data.

Abstract: A signal associated with multiple haptic effects is received, each haptic effect from the multiple haptic effects being associated with a time slot from multiple time slots. Each haptic effect from the multiple haptic effects is associated with an effect slot from multiple effect slots at least partially based on the time slot associated with that haptic effect. An output signal is sent for each effect slot from the multiple effect slots, when the associated haptic effect is scheduled for its time slot.

Abstract: Systems and methods schedule periodic and non-periodic transactions in a multi-speed bus environment that includes in a downstream hub a data forwarding component, such as a USB transaction translator, which accommodates communication speed shifts at the hub. The method may comprise receiving a split packet request defining a transaction with a device, tagging the request with an identifier allocated to the data forwarding component, storing the request in a transaction list associated with the identifier, initiating transfer of payload data, and updating a counter associated with the identifier to reflect an amount of payload data for which transfer was initiated. The identifier may have associated therewith a counter for tracking a number of bytes-in-progress to the data forwarding component and one or more transaction lists configured to store a plurality of split packet requests awaiting execution and state information regarding an execution status of the requests.

Abstract: A data transmission method is provided, which includes: obtaining a current queue length of a queue corresponding to an output port; when the current queue length meets a back-pressure requirement, determining a back-pressure priority corresponding to the current queue length according to the current queue length and a mapping relationship between a preset queue length and the back-pressure priority, and generating back-pressure information, where the back-pressure information inhibits a line card from sending data with a data priority less than or equal to the back-pressure priority to the output port; and sending the back-pressure information to a line card.

Abstract: A computer system having a plurality of processor cores utilizes a device driver running in a driver virtual machine to handle I/O with the corresponding device for other virtual machines. A hypervisor in the computer system receives an interrupt from the corresponding device and identifies a virtual machine that best correlates to the received interrupt prior to forwarding the interrupt for handling by the driver virtual machine. The hypervisor then speculatively transmits a notification to the identified virtual machine to wake up and poll a memory shared between the identified virtual machine and the driver virtual machine. Once the driver virtual machine completes handling of the forwarded interrupt, it copies data made available by the corresponding device to the shared memory for access by the polling identified virtual machine.

Abstract: A buffering device buffers data to be subjected to any one of a first process that necessitates a sequential guarantee and a second process that does not necessitate the sequential guarantee, and includes a storage unit that stores therein plurality of target data to be processed; a reading unit that reads the target data from the storage unit one-by-one based on a waiting flag set corresponding to the target data; and a control unit that sets a waiting flag for each of the target data, the waiting flag of a specific target data indicating preceding target data that must be processed before the reading unit reads the specific target data.

Abstract: A computer implemented method includes receiving a request to access a configuration space that is associated with a virtual function. The request may include a configuration space address and a root complex identifier. The computer implemented method may include identifying a root complex based on the root complex identifier. The computer implemented method may also include selecting a slot that is associated with the root complex. The slot may be capable of coupling a hardware input/output adapter to the root complex. The computer implemented method may further include determining whether the configuration space address is associated with the selected slot. The computer implemented method may include accessing the configuration space using an access mechanism in response to determining that the configuration space address is associated with the selected slot.

Abstract: A queue overflow prevention method and apparatus for Hard Disk Drive (HDD) protection in a computer system is provided. The queue overflow prevention method includes measuring acceleration information of the system, determining if the system is in a stable status or an unstable status using the acceleration information, and, while the system is in the unstable status, restricting the generation of a disk Input/Output (I/O) request.

Abstract: Handling of input or output (I/O) to or from a media device may be implemented in a system having a memory, a processor unit with a main processor and an auxiliary processor having an associated local memory, and the media device. An incoming I/O request received from an application running on the processor unit may be serviced according to the schedule. A set of processor executable instructions configured to implement I/O handling may include media filter layers. I/O handling may alternatively comprise: receiving an incoming I/O request from an application running on a main processor; inserting the request into a schedule embodied in the main memory; and implementing the request according to the schedule and one or more filters, at least one of which is implemented by an auxiliary processor.

Abstract: System and methods are provided for dynamically managing a first-in/first-out (FIFO) command queue of a system controller. One or more commands are received into the command queue, a command being associated with a priority parameter. A current command first in line to be executed in the command queue is determined, the current command being associated with a first priority parameter. A second command associated with a second priority parameter is determined, the second priority parameter being largest among priority parameters associated with the one or more commands. A final priority parameter for the current command is computed based at least in part on the second priority parameter.

Abstract: Techniques are disclosed for managing data requests from multiple requestors. According to one implementation, when a new data request is received, a determination is made as to whether a companion relationship should be established between the new data request and an existing data request. Such a companion relationship may be appropriate under certain conditions. If a companion relationship is established between the new data request and an existing data request, then when data is returned for one request, it is used to satisfy the other request as well. This helps to reduce the number of data accesses that need to be made to a data storage, which in turn enables system efficiency to be improved.

Abstract: Input/output (I/O) interrupts are avoided at the completion of I/O operations. A task requests (implicitly or explicitly) an I/O operation, and processing of the task is suspended awaiting completion of the I/O operation. At the completion of the I/O operation, instead of an I/O interrupt, an indicator associated with the task is set. Then, when the task once again becomes the current task to be executed, the indicator is checked. If the indicator indicates the I/O operation is complete, execution of the task is resumed.

Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

Abstract: A data transmission method is provided, which includes: obtaining a current queue length of a queue corresponding to an output port; when the current queue length meets a back-pressure requirement, determining a back-pressure priority corresponding to the current queue length according to the current queue length and a mapping relationship between a preset queue length and the back-pressure priority, and generating back-pressure information, where the back-pressure information inhibits a line card from sending data with a data priority less than or equal to the back-pressure priority to the output port; and sending the back-pressure information to a line card.

Abstract: Methods for controlling an interface operation, the method including stopping an operation being processed in a storage device and switching the state of the storage device to a first state, when a condition for switching the state of the storage device to an idle state occurs in a command processing process according to a communication protocol; performing an operation of deleting information from a previous command stored in hardware of the storage device when the state of the storage device is switched to the first state; and switching the state of the storage device to the idle state after the operation of deleting the information on the previous command is completed, wherein in the first state, the storage device cannot be switched to the first state before the information from the previous command is deleted.

Abstract: A system and method of I/O path virtualization between a RAID controller and an environment service module (ESM) in a storage area network (SAN) is disclosed. In one embodiment, a type of I/O request is identified by an input/output (I/O) control engine upon receiving an I/O request from a host computer via a RAID controller. Further, a priority is assigned to the received I/O request based on the type of I/O request by the I/O control engine. Furthermore, the processing of the prioritized I/O request is interrupted by the I/O control engine. In addition, the prioritized I/O request is separated into a command I/O request or a status request. Also, the separated command I/O request or the status request is sent to an associated queue in a plurality of solid state drive (SSD) buffer queues (SBQ) in the I/O control engine.

Abstract: An aspect of the invention is a storage networking system comprising subsystems coupled with a network. The subsystems include an initiator subsystem having an initiator I/O (input/output) control unit, and a plurality of target subsystems each having a target I/O control unit. The initiator subsystem is configured to: place priority information in packet address of an I/O command packet, the priority information being based on a priority table; send the I/O command packet to one or more of the plurality of target I/O control units; and receive a return I/O packet from each of the target I/O control units that received the sent I/O command packet, the return I/O packet having the same priority information. The priority information provided in the priority table is priority of storing I/O data. The I/O data is transferred according to the priority information placed in the packet address of the I/O command packet.

Abstract: Methods and apparatus for enhancing efficiency (e.g., reducing power consumption and bus activity) in a data bus. In an exemplary embodiment, a client-driven host device state machine switches among various states, each comprising a different polling frequency. A client device on the data bus (e.g., serial bus) checks for non-productive periods of polling activity, and upon discovering such a period, informs the host. The state machine then alters its polling scheme; e.g., switches to a lower state comprising a reduced polling frequency, and polling continues at this reduced frequency. In one variant, the client device continuously monitors itself to determine whether it has any data to transmit to a host device and if so, the host is informed, and the state machine restarts (e.g., to its highest polling state). By eliminating extraneous polling, power consumption and serial bus activity is optimized, potentially on both the host and the client.

Abstract: A storage device includes a memory; and a processor coupled to the memory, wherein the processor executes a process comprising: calculating an upper limit value of the number of input/output processings determined based on priority set to an information processing device, a port that is an interface between the information processing device and the storage device and a memory device of the storage device; scheduling an execution order of input/output processings based on the number of input/output processings received from the information processing device and the calculated upper limit value; and executing the input/output processings in the scheduled execution order.

Abstract: A plurality of devices are operated by storing at a device a first ID number received at a first port of the device and a second ID number received at a second port of the device. The device receives a data command through at least one of the first and second ports. The data command has a command ID number. The device executes the data command when at least one of the command ID number is equal to the first ID number when the data command is received at the first port and the command ID number is equal to the second ID number when the data command is received at the second port.

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: A television with at least one connection, either wired or wireless. Detection of an active device connected to the connection results in proper software and hardware configuration of the television to properly communicate with the device and provide, for example, proper user interface support and access to the device.

Abstract: An approach for automatically sharing a tape drive in a heterogeneous computing environment that includes a first computer and second computer is presented. The first computer receives a message that includes a shared tape drive identifier, a source port identifier of the second computer, and a reservation status change for the tape drive. Based on the tape drive identifier, the first computer determines that the tape drive is connected to the first computer. The source port identifier is determined to not identify any host bus adapter installed in the first computer. In response to the first computer determining that the reservation status change indicates a reservation or a release of the tape drive for the second computer, the first computer sets the tape drive offline or online, respectively, in an application executing in the first computer.

Abstract: Some of the embodiments of the present disclosure provide a method comprising categorizing each data packet of a plurality of data packets into one of at least two priority groups of data packets; and controlling transmission of data packets of a first priority group of data packets during a first off-time period such that during the first off-time period, data packets of the first priority group of data packets are prevented from being transmitted to a switching module from one or more server blades. Other embodiments are also described and claimed.

Abstract: An input/output (I/O) method, system, and computer program product are disclosed. An incoming I/O request is received from an application running on a processor. A tree structure including processor-executable instructions defines one or more layers of processing associated with the I/O request. The instructions divide the data in the I/O request into one or more chunks at each of the one or more layers of processing. Each instruction has an associated data dependency to one or more corresponding instructions in a previous layer. The instructions are sorted into an order of processing by determining a location of each chunk and data dependencies between chunks of different layers of processing. One or more instructions are inserted into a schedule that depends at least partly on the order of processing. The I/O request is serviced by executing the instructions according to the schedule with the processor according to the order of processing.

Abstract: Audio visual or other equipment modules in a common enclosure are controlled through an SNMP control agent by interrogating module locations for the presence of an equipment module; determining an equipment type; determining a list of available control objects associated with that equipment type; associating values identified by equipment type and by control parameter with the control objects of equipment modules to be controlled; and communicating said values across a network.

Abstract: A plurality of command storage areas respectively corresponding to a plurality of priorities and storing I/O commands in a storage control apparatus are common to a plurality of ports and a plurality of processors. Here, regardless of which port receives an I/O command, the I/O command is stored in a command storage area corresponding to a priority which is given to the I/O command. The plurality of processors run the I/O commands in the plurality of command storage areas so that an I/O command with a higher priority is run more often within a given period of time.

Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

Abstract: A method of managing a temporary memory includes: receiving a request to transfer data from a source location to a destination location, the data transfer request associated with an operation to be performed, the operation selected from an input into an intermediate temporary memory and an output; checking a two-state indicator associated with the temporary memory, the two-state indicator having a first state indicating that an immediately preceding operation on the temporary memory was an input to the temporary memory and a second state indicating that the immediately preceding operation was an output from the temporary memory; and performing the operation responsive to one of: the operation being an input operation and the two-state indicator being in the second state, indicating that the immediately preceding operation was an output; and the operation being an output operation and the two-state indicator being in the first state, indicating that the immediately preceding operation was an input.

Abstract: In an embodiment, a peripheral component may include a low priority command queue configured to store a set of commands to perform a transfer on a peripheral interface and a high priority command queue configured to store a second set of commands to perform a transfer on the interface. The commands in the low priority queue may include indications which identify points at which the set of commands can be interrupted to perform the second set of commands. A control circuit may be coupled to the low priority command queue and may interrupt the processing of the commands from the low priority queue responsive to the indications, and may process commands from the high priority command queue.

Abstract: The present invention provides a method and apparatus for data processing and virtualization. The method and apparatus are configured to receive communications, separate a command communication from a data communication, parallel process the command communication and the data communication, generate at least one virtual command based on the command communication, and generate virtual data according to the at least one virtual command. The apparatus can comprise a parallel virtualization subsystem configured to separate data communications from command communications and to parallel process the command communications and the data communications, to generate virtual commands and to generate virtual data according to a virtual command, and a physical volume driver coupled with the parallel virtualization subsystem, wherein the physical volume driver receives the virtual data and configures the virtual data.

Abstract: A system includes multiple nodes coupled using a network of processor buses. The multiple nodes include a first processor node, including one or more processing cores and main memory, and a flash memory node coupled to the first processor node via a first processor bus of the network of processor buses. The flash memory node includes a flash memory including flash pages, a first memory including a cache partition for storing cached flash pages for the flash pages in the flash memory and a control partition for storing cache control data and contexts of requests to access the flash pages, and a logic module including a direct memory access (DMA) register and configured to receive a first request from the first processor node via the first processor bus to access the flash pages.

Abstract: In one example, multimedia content is requested from a plurality of storage modules. Each storage module retrieves the requested parts, which are typically stored on a plurality of storage devices at each storage module. Each storage module determines independently when to retrieve the requested parts of the data file from storage and transmits those parts from storage to a data queue. Based on a capacity of a delivery module and/or the data rate associated with the request, each storage module transmits the parts of the data file to the delivery module. The delivery module generates a sequenced data segment from the parts of the data file received from the plurality of storage modules and transmits the sequenced data segment to the requester.