Abstract: Described is a system to control a flow of packets to and from an electronic processor which includes a packet processor engine programmed to interpret the packets from a packet memory, and to perform switching between packet chains in response to events, a working chain pointer register of the packet processor engine, programmed to indicate progress in executing an active buffer chain, prioritized pointer storage registers of the packet processor engine, each of the registers being programmed to point to one of the active buffer chains, a control register of the packet processor engine having chain start bits and chain protect bits, the chain start bits identifying the chains that have been started and wsa status register of the packet processor engine, having a chain actives group identifying the chain that is currently running, a chain matches group, a chain stops group identifying the chains that have been stopped and a timer expirations group.

Abstract: A method for allowing simultaneous parameter-driven and deterministic simulation during verification of a hardware design, comprising: enabling a plurality of random parameter-driven commands from a random command generator to execute in a simulation environment during verification of the hardware design through a command managing device; and enabling a plurality of deterministic commands from a manually-driven testcase port to execute in the simulation environment simultaneously with the plurality of random parameter-driven commands during verification of the hardware design through the command managing device, the plurality of deterministic commands and the plurality of random parameter-driven commands each verify the functionality of the hardware design.

Abstract: One embodiment provides a system including a communications channel, a first channel master, and a second channel master. The first channel master is configured to obtain latency values and maintain a first schedule of data traffic on the communications channel based on the latency values. The second channel master is configured to obtain the latency values and maintain a second schedule of data traffic on the communications channel based on the latency values. The first channel master manages data on the communications channel via the first schedule and the second channel master manages data on the communications channel via the second schedule.

Abstract: The invention comprises system and method for offloading a processor tasked with calendar processing of channel status information. The method comprises multiplexing channel status information received from a plurality of physical interfaces; grouping the channels based on bandwidth; comparing current and previous status information of a group of channels in a first memory; sending current channel status to the processor only if the status of any of the channels in the group has changed; and periodically synchronizing channel status information in the first memory to status information in the processor's memory. The system comprises: multiplexer to combine channel status information received from the interfaces and means for grouping, based on bandwidth, the channels; hardware assist engine to send current channel status to the processor only if channel status has changed; and device to synchronize channel status information in the hardware assist engine to status information in the processor's memory.

Abstract: A computer program product, an apparatus, and a method for processing communications between a target and an initiator an input/output processing system are provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes: sending a message between the initiator and the target, the message requesting suspension of input/output operations between the initiator and the target for a period of time, the period of time being defined by the message; and responsive to the message, suspending input/output operation messages for the period of time.

Abstract: A computer program product, an apparatus, and a method for processing communications between a control unit and a channel subsystem in an input/output processing system are provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method.

Abstract: A system and method for management of jobs in the cluster environment is provided. Each node a cluster executes a job manager that interfaces with a replicated database to enable cluster wide management of jobs within the cluster. Jobs are queued in the replicated database and retrieved by a job manager for execution. Each job manager ensures that jobs are processed through completion or, failing that, are re-queued on another storage system for execution.

Abstract: Provided are a method, system, and article of manufacture for using priority to determine whether to queue an Input/Output (I/O) request directed to storage. A maximum number of concurrent requests directed to a storage is measured. The measured maximum number of concurrent requests is used to determine a threshold for a specified priority. Subsequent requests of the specified priority directed to the storage are allowed to proceed in response to determining that a current number of concurrent requests for the specified priority does not exceed the determined threshold for the specified priority. Subsequent requests directed to the storage having a priority greater than the specified priority are allowed to proceed. Subsequent requests directed to the storage having the specified priority are queued in a queue in response to determining that the current number of concurrent requests for the specified priority exceeds the overall threshold.

Abstract: A signal associated with multiple haptic effects is received, each haptic effect from the multiple haptic effects being associated with a time slot from multiple time slots. Each haptic effect from the multiple haptic effects is associated with an effect slot from multiple effect slots at least partially based on the time slot associated with that haptic effect. An output signal is sent for each effect slot from the multiple effect slots, when the associated haptic effect is scheduled for its time slot.

Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

Abstract: The present invention is to provide a method of specifying access sequence of a storage device, wherein queues with different priority are created in the storage device for recording access requests from at least one server at the front-end of the storage device to manage the access operation, and are recorded corresponding to the front-end servers and the priority thereof respectively via a priority table. When the front-end server makes an access request, the request will be added to the corresponding queue according to the source front-end server, and each queue will be processed according to the priority thereof. The maximum workload of the access request processed every single time of each queue is set respectively. Thus, the access requests of the queues with higher priority will be processed within a shorter time.

Abstract: An apparatus for queuing and ordering commands for a data storage device may include a slot tracker module that is arranged and configured to track available slots for commands from a host, a command transfer module that is operably coupled to the slot tracker module and that is arranged and configured to retrieve commands from the host based on a number of the available slots, a pending command module that is operably coupled to the command transfer module and that is arranged and configured to queue and order the commands from the host for processing using an ordered list that is based on an age of the commands and a task dispatch module that is operably coupled to the pending command module and that is arranged and configured to dispatch the commands for processing using the ordered list from the pending command module and an availability of storage locations.

Abstract: Methods and apparatus for host-side Serial ATA Native Command Queuing (NCQ) tag management are disclosed. In one aspect, an exemplary apparatus may include a memory and an NCQ tag selection circuit in communication with the memory. The memory may store information for each of a plurality of different NCQ tag values. The information for each NCQ tag value may indicate whether or not a command having the NCQ tag value has been issued. The NCQ tag selection circuit may examine the information in the memory, and may select an NCQ tag value having information that indicates that a command having the NCQ tag value has not been issued. Systems and architectures including such apparatus are also disclosed.

Abstract: To provide a blade server capable of expanding disks of any servers in one chassis, the blade server has one or more server modules, one or more storage modules, a management module for managing the whole of the server, and a back plane via which a signal is transmitted among the modules wherein the server modules, the storage modules, and the management module are installed in slots. The server modules and the storage modules are interconnected via a disk interface on the back plane. Each of the server modules and the storage modules has a module management unit that controls a power in the its own module, and the module management unit controls the power in the its own module according to a power control signal sent from the management module.

Abstract: A method for managing IO requests from a virtual machine to access IO resources on a physical machine includes determining a request priority associated with an IO request. The IO request is placed in an appropriate queue in response to determining the request priority.

Abstract: Provided is a generating apparatus that generates a DVD-Video volume image, and a BD-ROM volume image, that each have: a digital stream, path information, and a jump table, where in the respective digital streams, a button command to be executed by a playback apparatus, in playing back the digital stream, is incorporated. A BD-scenario generating apparatus 7 obtains path information, a jump table, and a button command, which are for the BD-ROM, by converting any one of the description schemes for the path information, the jump table, and the button command for the DVD-Video.

Abstract: In certain, currently available data-storage systems, incoming commands from remote host computers are subject to several levels of command-queue-depth-fairness-related throttles to ensure that all host computers accessing the data-storage systems receive a reasonable fraction of data-storage-system command-processing bandwidth to avoid starvation of one or more host computers. Recently, certain host-computer-to-data-storage-system communication protocols have been enhanced to provide for association of priorities with commands. However, these new command-associated priorities may lead to starvation of priority levels and to a risk of deadlock due to priority-level starvation and priority inversion. In various embodiments of the present invention, at least one additional level of command-queue-depth-fairness-related throttling is introduced in order to avoid starvation of one or more priority levels, thereby eliminating or minimizing the risk of priority-level starvation and priority-related deadlock.

Abstract: Provided are a method and a system for controlling a disk input/output (I/O). The method includes detecting the number of consumed tokens that are the processing units of the disk I/O. Also, the method includes assigning a time slice that is a duration for processing the disk I/O according to the number of the consumed tokens using a preset minimum disk I/O bandwidth and a preset maximum disk I/O bandwidth.

Abstract: A memory controller includes a control circuit configured to provide a control signal, an output interface unit, and a command storage unit coupled to the control circuit and the output interface. The command storage unit is configured to store a plurality of commands, receive the control signal, and provide, in response to the control signal, a selected command of the plurality of commands to the output interface unit.

Abstract: A multi-input/output serial peripheral interface of an integrated circuit includes many pins coupled to the integrated circuit. The integrated circuit receives an instruction under a control of selectively using only a first pin or a combination of the first pin, a second pin, a third pin, and a fourth pin of the multi-input/output serial peripheral interface. The integrated circuit receives an address using the first pin, the second pin, the third pin, and the fourth pin of the multi-input/output serial peripheral interface. The integrated circuit sends a read out data using the first pin, the second pin, the third pin, and the fourth pin of the multi-input/output serial peripheral interface.

Abstract: A method is provided for transmitting data from a transmitting device (121) to a receiving device (125). The transmitting device transmits a first data frame (200) to a receiving device a first time (3100). Then it consecutively transmits the first data frame to the receiving device second through Nth times (3101-310N), each of second through Nth first data frame transmissions being made a first predetermined time period (350) after a respective previous first data frame transmission. After this, the transmitting device transmits a second data frame (200) to the receiving device a second predetermined time period (360) after the Nth first data frame transmission. In this method, N is an integer greater than 1, and the second predetermined time period is less than the first predetermined time period.

Abstract: A method enables a storage device to autonomously (i.e., without intervention of a host device) determines whether an integral sequence of commands, which is related to one or more storage commands issued by the host device, is in a certain state (i.e., it is “active” or “inactive”) or is transitioning from “active” state to “inactive” state, or from “inactive” state to “active” state. Depending on the determined state or transition, the storage device determines whether to refrain from executing Extra-Sequence (“ESQ”) operations and permit executing Intra-Sequence (“ISQ”) operations, or vice versa.

Abstract: A mechanism for reprioritizing high-latency input/output operations in a file system is provided. The mechanism expands a file access protocol, such as the direct access file system protocol, by including a hurry up command that adjusts the latency of a given input/output operation. The hurry up command can be employed in the Direct Access File System.

Abstract: In an information processing system, a host apparatus and a device are communicatively connected such that the host apparatus serves as a master and the device serves as a slave. The device is configured to establish a power-saving mode, when any command is not received from the host apparatus for a prescribed time period. A device driver is provided in the host apparatus. The device driver is configured to transit from a normal state to a suspended state when an operation command for operating the device is not received from an application running in the host apparatus for a prescribed time period, and to transmit a dummy response to the application, when an inquiry command is received from the application while the device driver is placed in the suspended state, without notifying the inquiry command to the device.

Abstract: A data reading method includes the steps of: a reading request issuing step of issuing a reading request for reading predetermined stored data; and a reading request re-issuing step of re-issuing a reading request when read data responsive to the reading request has not arrived within a predetermined time period, wherein: in the reading request re-issuing step, a flag is attached to the re-reading request, and thus, the re-reading request is differed from the first issued reading request.

Abstract: In accordance with the teachings of the present invention, a method for selecting a server to provide content to a client is presented. A media controller receives a request from a client for content. The media controller instructs a plurality of servers each storing the content required by the client to perform a bandwidth measurement referred to in the disclosure as a bandwidth probe. The result of the bandwidth probe is communicated to the media controller. The media controller selects a server (i.e., an identified server) for communication with the client based on the result and communicates the selection in the form of a redirect command to the client. The client then communicates directly with the identified server.

Abstract: A signal associated with multiple haptic effects is received, each haptic effect from the multiple haptic effects being associated with a time slot from multiple time slots. Each haptic effect from the multiple haptic effects is associated with an effect slot from multiple effect slots at least partially based on the time slot associated with that haptic effect. An output signal is sent for each effect slot from the multiple effect slots, when the associated haptic effect is scheduled for its time slot.

Abstract: A memory controller receives read requests from a processor into a read queue. The memory controller dynamically modifies an order of servicing the requests based on how many pending requests are in the read queue. When the read queue is relatively empty, requests are serviced oldest first to minimize latency. When the read queue becomes progressively fuller, requests are progressively, using three or more memory access modes, serviced in a manner that increases throughput on a memory bus to reduce the likelihood that the read queue will become full and further requests from the processor would have to be halted.

Abstract: A method for providing access arbitration for an integrated circuit in a wireless device is provided. The method includes receiving a command from a processing element coupled to the integrated circuit. A preempt signal associated with the command is generated. The preempt signal is operable to identify a priority for the command as one of high and low. The preempt signal is provided to an access arbiter for use in providing access arbitration for the command.

Abstract: A method and system for transferring data between a host and a Serial Attached Small Computer Interface (“SAS”) device using a storage controller is provided. The storage controller includes, a World Wide Name (“WWN”) module that includes a table having plural entries, wherein each row includes a WWN address, an initiator tag value field, an input/output counter value that tracks plural commands for a connection. A WWN index value represents the address of a row having plural entries. The method includes, comparing frame elements of incoming frames, including a unique WWN address with the WWN module entries; and if there is a match, updating a counter value for a connection between the storage controller and a device sending frames. The counter value is increased when a command frame is received and decreased when a command is executed and a response is sent to the device.

Abstract: An input/output control system of an information processing apparatus that includes a first storage area and a second storage area and carries out an input/output processing using a part or whole of the first storage area as a cache.

Abstract: An apparatus comprising at least one processor and at least one memory including computer program code. The at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus at least to detect a first user input corresponding to a first command, begin a first process corresponding to a second command in response to said first user input, detect a second user input corresponding to the second command and complete said first process in response to said second user input.

Abstract: In a system of networked devices such as printers managed by a computer connected to them by a network, a method is described for executing device discovery and device status update at independent time intervals using a SNMP broadcast method while eliminating thread safety risk. Device discovery and status update are executed as subroutines within a main routine and each subroutine has its own decrement counter. The entire routine is repeated one cycle every time unit. In each cycle, the decrement counters are evaluated. If a counter is a positive value, the corresponding subroutine is skipped and the counter is decremented by one. If a counter is zero, the corresponding subroutine is executed and its counter is reset to the user-specified time interval afterwards.

Abstract: A system and method for a die-to-die interconnect interface and protocol for stacked semiconductor dies. One preferred embodiment comprises an integrated circuit (IC) package comprising a first semiconductor die that includes an interface to a memory-mapped device, a second semiconductor die that does not include an interface to a memory mapped device, and a data bus coupling the first semiconductor die to the second semiconductor die (the data bus used to transfer a control word and a data word). The control word comprises a data word start address that corresponds to a location in the memory-mapped device. The data word is transferred from the second semiconductor die to the first semiconductor die and is stored by the first semiconductor die at the location in the memory-mapped device. Both semiconductor dies are mounted within the IC package.

Abstract: A method and apparatus is presented allowing multiple data pointers or addresses to be transferred without acknowledgment to Memory Controller (506) and Memory Controller (510) of Data Controller (500). Data is then transferred in response to the data pointers from BUFFER (512) and Buffer (514) and may be stalled during the transfer in favor of a second data transfer. Once the second data transfer finishes, the first data transfer may be completed.

Abstract: Provided is a method for scheduling operations called by a task on a real-time or non-real-time processor. Execution durations are provided for operations. A call is received from a task for an operation. A determination is made of a latency requirement for a first processor and of the execution duration of the called operation. The called operation is executed on the first processor in response to determining that the determined execution duration is less than the latency requirement. The called operation is executed on a second processor in response to determining that the determined execution duration is greater than the latency requirement.

Abstract: A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.

Abstract: A disclosed data transfer device includes one or more data transfer control unit configured to control a command issuance and a data transfer separately, a command issuing unit configured to determine priorities of commands and issue the commands in an order from a higher priority, a memory communication control unit configured to perform the data transfer corresponding to the command from and to a memory, and a signal output unit configured to output a completion signal of the data transfer in a case where the data transfer is normally completed. The command issuing unit sets a priority of a command corresponding to a request for resetting the data transfer control unit lower than the priority of the command issued by the data transfer control unit when the request for resetting is received, and the signal output unit outputs a dummy completion signal to the memory communication control unit.

Abstract: A data processing apparatus transmits and receives moving image data to and from an external device through a transmission path. A first pipe used for transferring the moving image data and a second pipe used for transferring timing information relating to the processing timing of the moving image data are provided on the transmission path. The moving image data is being transferred to the external device through the first pipe in parallel with the timing information relating to the moving image data being transferred through to the external device through the second pipe.

Abstract: Commands received from an apparatus that does not support virtual channels are assigned to a virtual channel. A command receiver 210 receives, from an external command transmitting entity that does not support virtual channels, a command designating an address. An assignment information storage unit 228 stores an assignment table in which an address space is divided into a plurality of areas and a channel is assigned to each area. A command storage unit 230 contains queues provided for respective channels, wherein each queue stores received commands temporarily. A distribution destination specifying unit 224 specifies a queue corresponding to an address by referring to the assignment table, and an execution unit 222 transfers the received command to the command storage unit 230 that corresponds to the specified queue.

Abstract: A reordering command queue for reordering memory accesses in a computer system. The reordering command queue may reduce the power that is typically used up in computer systems when performing accesses to main memory by improving the scheduling of memory accesses with a pattern that is optimized for power and which has no (or negligible) impacting on performance. During a compare operation, the address corresponding to the command stored in each of one or more current storage locations of the reordering command queue may be compared to the address corresponding to the command stored in an adjacent storage location to determine whether the commands are in a desired order. In response to one or more of the commands not being in the desired order, a reordering operation may be performed, which may reorder each of the one or more commands from a current storage location to the adjacent storage location.

Abstract: A mechanism and technique to transfer data between a communication device and media hardware in a computing device. More particularly, an embodiment of the invention uses a quality of service to assure deterministic latencies in direct data transfers between a memory buffer and each of a communication device and an audio hardware controller.

Abstract: A polling system polls a USB keyboard connected to a USB port of a computing system. A detect module in identifies the keyboard as a low speed USB device. A polling module polls the keyboard with the scheduled interrupt transactions. A key press polling response module detects a key press, stores corresponding key scan data in a key data buffer, and returns the key scan data in response to a scheduled interrupt transaction from the polling module. A key repeat polling response module starts akey repeat polling mode when the key scan data is returned from the key press polling response module, detects whether the key data buffer is empty when a scheduled interrupt transaction is received, and returns the key scan data again if the key scan data buffer is not empty. A stop module stops the key repeat polling mode if the key scan data buffer is empty.

Abstract: A scheduling method and apparatus for use by a processor that controls storage devices of a data storage system is presented. The method allocates processing time between I/O operations and background operations for predetermined time slots based on an indicator of processor workload.

Abstract: An I/O-request processing system which is capable of reducing the maximum value of the time required until the I/O request of each external device is registered. An I/O-request receiving section (501) receives an I/O request issued from an external device (600). A process-information storage section (510) stores an I/O-request delay time (512) for each external device (600). A priority-process judgment section (520) registers the I/O request having a maximum I/O-request delay time (512) among the I/O requests which have been registered into an I/O-request cue (540).

Abstract: To provide a storage system that can control both the number of commands activated per unit time and the response time of each command activated in accordance with the priority level of command. The storage system comprises a queue corresponding to each priority of command and an activation order control part. A command that the storage system receives from a host computer is accumulated in the queue corresponding to the priority specified from the command. The activation order control part decides, for each queue, the number of activation object commands that are the commands to be activated among a plurality of commands accumulated in the queue, based on the priority corresponding to the queue. And the activation order control part decides the activation order of the activation object commands, based on the activation object command number decided for each queue, so that the average value of logical response time of the activation object command may be shorter at the higher priority.

Abstract: In some embodiments a memory controller is disclosed that includes at least one command/address input buffer to receive commands and addresses. The addresses specify a memory bank and a location within the memory bank. An arbiter, coupled to the at least one command/address input buffer, merges commands and addresses from the at least one command/address input buffer and sorts the commands and addresses based on the addresses specified. A plurality of bank buffers, coupled to the arbiter and associated with memory banks, receive commands and addresses for their associated memory banks. A scheduler, coupled to the plurality of bank buffers, groups commands and addresses based on an examination of at least one command and address from the bank buffers. Other embodiments are otherwise disclosed herein.

Abstract: Techniques are provided for managing, within a storage system, the sequence in which I/O requests are processed by the storage system based, at least in part, on a one or more logical characteristics of the I/O requests. The logical characteristics may include, for example, the identity of the user for whom the I/O request was submitted, the service that submitted the I/O request, the database targeted by the I/O request, an indication of a consumer group to which the I/O request maps, the reason why the I/O request was issued, a priority category of the I/O request, etc. Techniques are also provided for automatically establishing a scheduling policy within a storage system, and for dynamically changing the scheduling policy in response to changes in workload.

Abstract: A method and system for processing out of order frames received by a host bus adapter is provided. The method includes, determining if a current frame is out of order; determining if a frame is within a range of transfer for an Exchange; and creating (or appending if not the first out-of-order frame) an out of order list if the current frame is a first out of order frame. The method also includes, determining if an entry in an out of order list has a relative offset value of zero; determining if at least one entry has a relative offset value equal to a total transfer length of an Exchange; and determining if every non-zero starting relative offset has a matching entry. The method also scans an out of order list and combines a last entry with an entry whose starting point matches the end point of the last entry.

Abstract: The present disclosure relates to attempting to initialize and configure a device utilizing a remote server and, more specifically, to attempting to initialize a device with low level device configuration information that is stored on a remote server or servers.