Abstract: Embodiments of the invention relate to process identifier (PID) based cache information transfer. An aspect of the invention includes sending, by a first core of a processor, a PID associated with a cache miss in a first local cache of the first core to a second cache of the processor. Another aspect of the invention includes determining that the PID associated with the cache miss is listed in a PID table of the second cache. Yet another aspect of the invention includes based on the PID being listed in the PID table of the second cache, determining a plurality of entries in a cache directory of the second cache that are associated with the PID. Yet another aspect of the invention includes pushing cache information associated with each of the determined plurality of entries in the cache directory from the second cache to the first local cache.

Abstract: Circuits and methods for performing search operations in a content addressable memory (CAM) array are provided. A system for searching a CAM includes a circuit that selectively activates a main-search of a two stage CAM search while a pre-search of the two stage CAM search is still active.

Abstract: The present disclosure relates to a local caching device, system and method for providing a content caching service. The local caching device receives, from a content provider, at least one part of content requested by a user terminal and then, based on the received part of the requested content, determines whether the requested content is stored in a storage unit. If the requested content is stored, the local caching device registers flow information of the requested content in the storage unit. When content having the same flow information as the registered flow information is requested, the local caching device determines based on content address information whether the requested content is stored.

Abstract: A Dynamic Random Access Memory (DRAM) controller. The DRAM controller includes receiving a plurality of access requests from a plurality of user interfaces to access one or more DRAM devices. Further, the DRAM controller includes storing the plurality of access requests in a Content Addressable Memory (CAM). Furthermore, the DRAM controller includes updating at least one access request of the plurality of access requests to a Next Access Table. In addition, the DRAM controller includes determining at least one paramount access request of the plurality of access requests by a CAM based decision controller for employing a bypass operation in the CAM based decision controller, based on a plurality of pre-defined conditions. Further, the DRAM controller includes issuing the plurality of access requests to the one or more DRAM devices.

Abstract: In one embodiment, a method includes establishing a link between two N_Port Identifier Virtualization (NPIV) switches, the link having a high cost assigned thereto. The NPIV switches are in communication with a plurality of hosts through an N_Port Virtualization (NPV) device. The method further includes receiving at a first of the NPIV switches, an indication of a failure at a second of the NPIV switches, receiving data at the first NPIV switch, the data destined for one of the hosts associated with a domain of the second NPIV switch, and forwarding the data to the NPV device for delivery to the host, wherein a Fibre Channel Identifier (FCID) of the host is the same before and after the failure at the second NPIV switch. An apparatus is also disclosed.

Abstract: Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses.

Abstract: Embodiments of the invention are directed to a TCAM for longest prefix matching in a routing system. The TCAM comprises a plurality of records of which a portion are configured into one or more address clusters each such cluster corresponding to a respective IP address prefix length and another portion of which are configured into a free cluster not corresponding to any IP address prefix length.

Abstract: Systems and methods are disclosed to implement smart zoning using device alias database that preserves TCAM space. Embodiments may consider device types to save an administrator's efforts from splitting application specific zones into two-member (initiator and target) zones.

Abstract: Write-through-read (WTR) comparator circuits and related WTR processes and memory systems are disclosed. The WTR comparator circuits can be configured to perform WTR functions for a multiple port file having one or more read and write ports. One or more WTR comparators in the WTR comparator circuit are configured to compare a read index into a file with a write index corresponding to a write-back stage selected write port among a plurality of write ports that can write data to the entry in the file. The WTR comparators then generate a WTR comparator output indicating whether the write index matches the read index to control a WTR function. In this manner, the WTR comparator circuit can employ less WTR comparators than the number of read and write port combinations. Providing less WTR comparators can reduce power consumption, cost, and area required on a semiconductor die for the WTR comparator circuit.

Abstract: Systems, and methods, including executable instructions and/or logic thereon are provided for ternary content addressable memory (TCAM) updates. A TCAM system includes a TCAM matching array, a TCAM action array that specifies actions that are taken upon a match in the TCAM array, and a TCAM driver that provides a programmable interface to the TCAM matching array and the TCAM action array. Program instructions are executed by the TCAM driver to add a divert object which encompasses actions associated with the TCAM actions array and to apply the divert object to update action fields in the TCAM action array, without changing the relative order of entries in the TCAM matching array, while hardware is simultaneously using the entries.

Abstract: Embodiments of a Content Addressable Memory (CAM) enabling high-speed search and invalidate operations and methods of operation thereof are disclosed. In one embodiment, the CAM includes a CAM cell array including a number of CAM cells and a valid bit cell configured to generate a match indicator, and blocking circuitry configured to block an output of the valid bit cell from altering the match indicator during an invalidate process of a search and invalidate operation. Preferably, the output of the valid bit cell is blocked from affecting the match indicator for the CAM cell array beginning at a start of the invalidate process and continuing until an end of the search and invalidate operation.

Abstract: A method for reducing memory entries in a ternary content-addressable memory may include determining if a first entry and a second entry are associated with the same data value. The method may also include determining if the first entry can be masked such that searching the memory with the content value of either of the first entry or the second entry returns the same data value. The method may further include, in response to determining that the first entry and a second entry are associated with the same data value and determining that the first entry can be masked such that addressing the memory with the content value of either of the first entry or the second entry returns the same data value: (i) masking the first entry such that addressing the memory with the content value of either of the first entry or the second entry returns the same data value; and (ii) deleting the second entry.

Abstract: Techniques for forming and using multi-space associative memory units are disclosed. One example method for retrieving classification rules for data objects begins with the retrieval of a first action for the data object by performing a first lookup in a first associative memory space in a memory unit, using a first key formed from the data object. A second action for the data object is retrieved by performing a second lookup in a second associative memory space, using a second key formed from the data object. The lookups are performed simultaneously, in some embodiments, or serially, in others. In some embodiments, the second lookup is performed after the first, in response to an information element retrieved from the first lookup, the information element indicating that an additional associative memory lookup is needed. A final action for the data object is determined from the results of the first and second lookups.

Abstract: A computer system has extensible firmware interface firmware. The EFI firmware loads incomplete virtual boot data from a resource manager and then completes the boot data. The completed boot data is used to find an operating-system image to boot. The complete virtual boot data is transferred to the resource manager.

Abstract: Ternary CAM cells include a compare circuit including a discharge path having only two pull-down transistors coupled between the match line and ground potential.

Abstract: A content-addressable memory (CAM) for managing the reallocation of erasable objects within a non-volatile memory is conceptually separated into two tables: a first table provides verification of whether or not a logical address has been reallocated and, if so, a second table provides the physical address of the reallocated erasable object.

Abstract: Systems, devices and methods according to these exemplary embodiments provide for memory management techniques and systems for storing data. Data is segmented for storage in memory. According to one exemplary embodiment, each fragment is routed via a different memory bank and forwarded until they reach a destination memory bank wherein the fragments are reassembled for storage. According to another exemplary embodiment, data is segmented and stored serially in memory banks.

Abstract: Methods, systems, and computer readable storage medium embodiments for configuring a lookup table for a network device are disclosed. Aspects in these embodiments include generating a decision tree based upon bit representations of respective data entries from a plurality of data entries where one or more of the plurality of data entries are represented at respective nodes of the decision tree, storing a first bit pattern corresponding to a selected node from the decision tree in a content addressable memory (CAM) at a location associated with an index, and storing one or more second bit patterns at an address in a second memory. The one or more second hit patterns correspond to the one or more data entries represented at the selected node, and the address is associated with the index. Embodiments also include searching a lookup table in a network device.

Abstract: Methods, systems, and computer readable storage medium embodiments for configuring a lookup table, such as an access control list (ACL) for a network device are disclosed. Aspects of these embodiments include storing a plurality of data entries in a memory, each of the stored plurality of data entries including a header part and a body part, and encoding each of a plurality of bit-sequences in the header part of a stored data entry from the plurality of data entries to indicate a bit comparing action associated with a respective bit sequence in the body part of the stored data entry. Other embodiments include searching a lookup table in a network device.

Abstract: A disclosed embodiment is an interruptible write block comprising a primary register having an input coupled to an input of the interruptible write block, a secondary register having an input selectably coupled to an output of the primary register and to an output of the secondary register through an interrupt circuit. The interrupt circuit is utilized to interrupt flow of new data from the primary register to the secondary register during an interrupt of a write operation, such that upon resumption of the write operation the secondary register contains valid data. A method of utilizing an interruptible write block during a write operation comprises loading data into a primary register, interrupting the write operation to perform one or more other operations, loading the data into a secondary register while loading new data into the primary register, and resuming the write operation using valid data from the secondary register.

Abstract: A method and system for controlling multiple client access to cache memory and a single CAM device. Each client has a corresponding integrity controller in communication with the CAM device and all the other integrity controllers associated with the other clients in the system. Each integrity controller monitors states of the other clients, and inhibits its respective client from executing any operation when a common lookup index is detected during a co-pending operation with a first client. Once the operations of the first client are completed, its integrity controller signals the integrity controller of other clients to exit their inhibit or hold states, thereby allowing the other clients to resume their operations. Another advantage of the integrity controller is that its algorithms also prevents multiple host memory fetches of the same key, thereby saving time and improving system performance.

Abstract: A system includes an associative memory, a first table, a second table, a comparator, and an updater. The associative memory may include data and associations among data and may be built from the first table. The first table may include a record with a first and second field. The associative memory may be configured to ingest the first field and avoid ingesting the second field. The second table may include a record with a third field storing information indicating whether the first field has been ingested by the associative memory or has been forgotten by the associative memory. The comparator may be configured to compare the first and second table to identify one of whether the first field should be forgotten or ingested by the associative memory. The updater may be configured to update the associative memory by performing one of ingesting or forgetting the first field.

Abstract: A method and an apparatus for updating table entries of a TCAM are disclosed. The method comprises: creating a virtual TCAM list, of which respective first TCAM table entries are one-to-one corresponding to respective second TCAM table entries stored in a hardware TCAM; determining, in idle resources of the hardware TCAM, a storage position of a second TCAM table entry to be updated corresponding to a first TCAM table entry to be updated, according to a pre-specified precedence relationship between the storage positions of the first TCAM table entry to be updated and other first TCAM table entry in the virtual TCAM list; and performing an updating operation on the second TCAM table entry to be updated based on the determined storage position.

Abstract: A Phase-Change Memory (PCM) Content Addressable Memory (CAM) utilized to store addresses of defective rows or columns of a memory array or memories attached to a backside bus of a concentrator device.

Abstract: Embodiments of the present disclosure provide methods, apparatuses, and systems including a memory device including content addressable memory configured to store an address associated with one or more memory cells while an access operation is performed on the one or more memory cells. Other embodiments may be described.

Abstract: Described are techniques for data processing and caching. In response to a client failing to retrieve contents of a data element from a cache location specified by a first data element identifier including a first content-based identifier, the contents of the data element are obtained and stored at a cache location specified by the first data element identifier. The contents of the data element are updated at a second point in time and stored as second contents in the data element source. The data element at the second point in time has a second content-based identifier. In response to the client failing to retrieve the second contents of the data element from a cache location specified by a second data element identifier including the second content-based identifier, the second contents of the data element are obtained and stored at a cache location specified by the second data element identifier.

Abstract: Some embodiments of the present invention provide a system that processes a request for a cache line in a multiprocessor system that supports a directory-based cache-coherence scheme. During operation, the system receives the request for the cache line from a requesting node at a home node, wherein the home node maintains directory information for all or a subset of the address space which includes the cache line. Next, the system performs an action at the home node, which causes a valid copy of the cache line to be sent to the requesting node. The system then completes processing of the request at the home node without waiting for an acknowledgment indicating that the requesting node received the valid copy of the cache line.

Abstract: A conditionally precharged content addressable memory (CAM) includes forcing a mismatch on a matchline of the CAM if a data entry in the CAM is invalid. The matchline of the CAM is precharged only if the data entry is valid.

Abstract: According to one embodiment, a semiconductor memory device includes a memory and a controller. The memory stores data pieces and search information including entries, where each entry is associated with a search key for specifying one data piece and a real address at which the data piece is stored. Upon reception of a first command, the controller, when the first command specifies a search key, outputs one data piece corresponding to one entry which includes the search key, and when the first command specifies one real address, outputs one data piece corresponding to one entry including the real address.

Abstract: Example methods, apparatus, and articles of manufacture to access data are disclosed. A disclosed example method involves generating a key-value association table in a non-volatile memory to store physical addresses of a data cache storing data previously retrieved from a data structure. The example method also involves storing recovery metadata in the non-volatile memory. The recovery metadata includes a first address of the key-value association table in the non-volatile memory. In addition, following a re-boot process, the locations of the key-value association table and the data cache are retrieved using the recovery metadata without needing to access the data structure to re-generate the key-value association table and the data cache.

Abstract: Described are computer-based methods and apparatuses, including computer program products, for removing redundant data from a storage system. In one example, a data delineation process delineates data targeted for de-duplication into regions using a plurality of markers. The de-duplication system determines which of these regions should be subject to further de-duplication processing by comparing metadata representing the regions to metadata representing regions of a reference data set. The de-duplication system identifies an area of data that incorporates the regions that should be subject to further de-duplication processing and de-duplicates this area with reference to a corresponding area within the reference data set.

Abstract: A method and apparatus for providing TCAM functionality in a custom integrated circuit (IC) is presented. An incoming key is broken into a predefined number of sub-keys. Each sub-key is sued to address a Random Access Memory (RAM), one RAM for each sub-key. An output of the RAM is collected for each sub-key, each output comprising a Partial Match Vector (PMV). The PMVs are bitwise ANDed to obtain a value which is provided to a priority encoder to obtain an index. The index is used to access a result RAM to return a result value for the key.

Abstract: Various embodiments of the present invention are generally directed to an apparatus and associated method for a non-volatile memory with a hybrid index tag array. In accordance with some embodiments, a memory device has a word memory array formed of non-volatile resistive sense memory (RSM) cells, a first index array formed of volatile content addressable memory (CAM) cells, and a second index array formed of non-volatile RSM cells. The memory device is configured to output word data from the word memory array during a data retrieval operation when input request data matches tag data stored in the first index array, and to copy tag data stored in the second index array to the first index array during a device reinitialization operation.

Abstract: A method and system for accessing a dynamic random access memory (DRAM) is provided. A memory controller includes a content addressable memory (CAM) based decision control module for determining a next best access request for the DRAM. The CAM based decision control module includes a CAM access storage module for storing access requests, a next access table module for storing the next best access request, and a decision logic module for determining the next best access request based on results from the CAM access storage module and the next access table module. Further, the memory controller includes a DRAM access control interface for implementing signaling required to access the DRAM. The method includes storing access requests in a CAM access storage module. The method includes determining which of the stored access requests is a next best access request. Further, the method includes processing the next best access request.

Abstract: Methods and apparatus are provided for implementing a lightweight notification (LN) protocol in the PCI Express base specification which allows an endpoint function associated with a PCI Express device to register interest in one or more cachelines in host memory, and to request an LN notification message from the CPU/memory complex when the content of a registered cacheline changes. The LN notification message can be unicast to a single endpoint using ID-based routing, or broadcast to all devices on a given root port. The LN protocol may be implemented in the CPU complex by configuring a queue or other data structure in system memory for LN use. An endpoint registers a notification request by setting the LN bit in a “read” request of an LN configured cacheline.

Abstract: Techniques for performing de-duplication for data blocks in a computer storage environment. At least one chunking/hashing unit receives input data from a source and processes it to output data blocks and content addresses for them. In one aspect, the chunking/hashing unit outputs all blocks without checking to see whether any is a duplicate of a block previously stored on the storage environment. In another aspect, each data block is processed by one of a plurality of distributed object addressable storage (OAS) devices that each is selected to process data blocks having content addresses with a particular range. The OAS devices determine whether each received to data block is a duplicate of another previously stored on the computer storage environment, and when it is not, stores the data block.

Abstract: A digital design and technique may be used to implement a Manhattan Nearest Neighbor content addressable memory function by augmenting a serial content addressable memory design with additional memory and counters for bit serially accumulating in parallel and subsequently comparing in parallel all the Manhattan distances between a serially inputted vector and all corresponding vectors resident in the CAM. Other distance measures, besides a Manhattan distance, may optionally be used in conjunction with similar techniques and designs.

Abstract: Aspects of the disclosure provide a method for encoding ranges in a ternary content addressable memory (TCAM). The method includes determining first positive ranges and first negative ranges corresponding to a first encoding range to be encoded in the TCAM. The first encoding range is in association with a first action. The first positive ranges include the first encoding range. The first negative ranges exclude the first encoding range. At least a first positive range and a first negative range are overlapping. Further, the method includes encoding the first positive ranges in first TCAM entries, and encoding the first negative ranges in second TCAM entries. At least one of the second TCAM entries has a higher priority than one of the first TCAM entries. Then, the method includes associating the first TCAM entries to the first action, and associating the second TCAM entries to a reject action.

Abstract: A content addressable memory system, method and computer program product is described. The memory system comprises a location addressable store having data identified by location and multiple levels of content addressable stores each holding ternary content words. The content words are associated with references to data in the location addressable store. The content store levels might be implemented using different technologies that have different performance, capacity, and cost attributes. The memory system includes a content based cache for improved performance and a content addressable memory management unit for managing memory access operations and virtual memory addressing.

Abstract: A pattern matching system detects strings contained in a target pattern to be detected within a data stream input by 1-byte data, and detects a regular expression representing the target pattern among regular expressions constructed by the detected strings.

Abstract: Quaternary CAM cells are provided that include one or more compare circuits that each has a minimal number of pull-down transistors coupled between the match line and ground potential. For some embodiments, the compare circuit includes two parallel paths between the match line and ground potential, with each parallel path consisting of a single pull-down transistor having a gate selectively coupled to the stored data value in response to a comparand value.

Abstract: A method of controlling a dynamic random access memory (DRAM) and a DRAM memory controller is provided. An example DRAM memory controller includes a content addressable memory (CAM) based decision control module. The CAM based decision control module includes a CAM access storage module, a next access table module, and a decision logic module. Further, the DRAM memory controller includes a DRAM access control interface. The method includes detecting a request for a read-modify-write operation. The method also includes creating a read access request and a write access request based on the detecting. Further, the method includes prioritizing the read access request and the write access request. Moreover, the method includes executing the read access request and the write access request based on the prioritizing.

Abstract: The embodiments of the present invention provide a storage method and a storage apparatus which are based on data content identification. Through the storage method and the storage apparatus which are based on data content identification and provided in the embodiments of the present invention, the data from the host is received, the content of the data is scanned to obtain format characteristics of the data, and the characteristics are matched with format characteristics in a content characteristic base to determine attributes of the data, and the data is sorted and stored according to the data attributes, so that a storage device can obtain attributes of the data to be stored and optimize the data, which improves data storage performance of the storage device.

Abstract: Described are techniques for automatically provisioning storage for an application. A request to provision object-based storage for the application in a data storage system is received The request identifies the application and is received from a user interface interacting with the data storage system at a specified one of a plurality of user levels, each of said plurality of user levels being associated with a different level of abstraction with respect to first processing performed in implementing the request. The first processing is performed to provision object-based storage for the request. The first processing is determined in accordance with the application and includes a level of automation varying in accordance with the specified user level at which the user interface interacts with the data storage system. The automation includes selecting one or more default options in accordance with best practices of the application.

Abstract: A multi-priority encoder includes a plurality of interconnected, single-priority encoders arranged in descending priority order. The multi-priority encoder includes circuitry for blocking a match output by a lower level single-priority encoder if a higher level single-priority encoder outputs a match output. Match data is received from a content addressable memory, and the priority encoder includes address encoding circuitry for outputting the address locations of each highest priority match line flagged by the highest priority indicator. Each single-priority encoder includes a highest priority indicator which has a plurality of indicator segments, each indicator segment being associated with a match line input.

Abstract: A disclosed embodiment is an interruptible write block comprising a primary register having an input coupled to an input of the interruptible write block, a secondary register having an input selectably coupled to an output of the primary register and to an output of the secondary register through an interrupt circuit. The interrupt circuit is utilized to interrupt flow of new data from the primary register to the secondary register during an interrupt of a write operation, such that upon resumption of the write operation the secondary register contains valid data. A method of utilizing an interruptible write block during a write operation comprises loading data into a primary register, interrupting the write operation to perform one or more other operations, loading the data into a secondary register while loading new data into the primary register, and resuming the write operation using valid data from the secondary register.

Abstract: Embodiments of a Content Addressable Memory (CAM) enabling high-speed search and invalidate operations and methods of operation thereof are disclosed. In one embodiment, the CAM includes a CAM cell array including a number of CAM cells and a valid bit cell configured to generate a match indicator, and blocking circuitry configured to block an output of the valid bit cell from altering the match indicator during an invalidate process of a search and invalidate operation. Preferably, the output of the valid bit cell is blocked from affecting the match indicator for the CAM cell array beginning at a start of the invalidate process and continuing until an end of the search and invalidate operation.

Abstract: The techniques introduced here provide a system and method for hardware implemented storage service flow classification using content addressable memory. The techniques described here allow for classification and handling of storage service requests according to service level agreement (SLA) or quality of service (QoS) parameters without consuming valuable storage server resources.

Abstract: A method of and apparatus for searching for a signature in a packet according to a signature location. The method may include extracting a sub-payload to be compared with a signature from a payload of a packet, generating an offset that is location information about a location of the sub-payload in the payload, generating a search key that includes the extracted sub-payload and the generated offset, and performing ternary content addressable memory (TCAM) matching to check if the generated search key matches a TCAM entry.

Abstract: A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.