Abstract: Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a memory device can asynchronously indicate to a connected host that information in a mode register has been changed, obviating the need for repeated polling of the information and thereby reducing both command/address bus and data bus bandwidth consumption. In one embodiment, a memory device comprises a memory; a mode register storing information corresponding to the memory; and circuitry configured to, in response to the information in the mode register being modified by the memory device, generate a notification to a connected host device.

Abstract: Methods, systems and apparatus for approximating a target quantum state. In one aspect, a method for determining a target quantum state includes the actions of receiving data representing a target quantum state of a quantum system as a result of applying a quantum circuit to an initial quantum state of the quantum system; determining an approximate quantum circuit that approximates the specific quantum circuit by adaptively adjusting a number of T gates available to the specific quantum circuit; and applying the determined approximate quantum circuit to the initial quantum state to obtain an approximation of the target quantum state.

Abstract: Methods, systems and apparatus for producing quantum circuits with low T gate counts. In one aspect, a method for performing a temporary logical AND operation on two control qubits includes the actions of obtaining an ancilla qubit in an A-state; computing a logical-AND of the two control qubits and storing the computed logical-AND in the state of the ancilla qubit, comprising replacing the A-state of the ancilla qubit with the logical-AND of the two control qubits; maintaining the ancilla qubit storing the logical-AND of the two controls until a first condition is satisfied; and erasing the ancilla qubit when the first condition is satisfied.

Abstract: In a malware detection device, first characters in a network traffic flow are compared with a plurality of entries within a ternary content addressable memory (TCAM), the plurality of entries including a first entry that constitutes a first segment of a malware signature. In response to an output from the first TCAM indicating that the first characters match the first entry, a variable-character expression engine determines whether second characters in the network traffic flow match a first variable-length regular expression, the variable-length regular expression corresponding to a second segment of the malware signature. A comparand value is generated that includes third characters in the network traffic flow and an expression-match value that indicates whether the second characters match the first variable-length regular expression. The TCAM compares the first comparand value with the plurality of entries therein as part of a determination whether the network traffic flow contains the malware signature.

Abstract: An exemplary method includes sending a storage query to a plurality of storage nodes of a data storage system, the storage query including a data identifier of a data instance and an inquiry as to which of the storage nodes can store the data instance; receiving, in response to the storage query, a plurality of responses from a subset of storage nodes included in the plurality of storage nodes and that have at least a predetermined minimum amount of free storage space, the responses including information about each of the storage nodes included in the subset; selecting, based on the information included in the responses, multiple storage nodes included in the subset; and sending the data instance and the data identifier to the selected storage nodes for storage by the selected storage nodes.

Abstract: A control method of a flash memory controller, wherein the control method includes the steps of: when data is written to a page of any block of a flash memory module, recording a write time in the page; create a write time table, wherein the write time table records block numbers of blocks having data written therein and corresponding write time; compress the write time table to generate a compressed write time table, wherein the compressed write time table contains multiple time ranges and corresponding indexes, each index corresponds to a page of the flash memory module, and the page records block numbers of all blocks whose writing time is within the corresponding time range.

Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.

Abstract: Some embodiments are directed to a data retrieval device 210 for data-obliviously copying a subarray of a first array to a second array. The length of the second array is more than one and less than the length of the first array. The length of the subarray is at most the length of the second array. For each first element at a first index in the first array, the data retrieval device selects a second index in the second array for the first index in the first array; data-obliviously computes a choice bit indicative of whether to copy the first element to the second index in the second array; and replaces a second element at the second index in the second array by a replacement element, the replacement element being data-obliviously set to the first element or the second element based on the choice bit.

Abstract: A test instrument is operable to test Software Communications Architecture (SCA) devices. The test instrument can identify components of an SCA application loaded on an SCA device being tested, and create a test point in the SCA application that may be between components of the SCA application. The test instrument can receive and analyze signals generated at the test point to identify malfunctioning components within the SCA application.

Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.

Abstract: A method includes receiving data objects, determining a predicted lifespan of each data object, and instantiating multiple shard files. Each shard file has an associated predicted lifespan range. The method also includes writing each data object into a corresponding shard file having the associated predicted lifespan range that includes the predicted lifespan of the respective data object and storing the shard files in a distributed system. The method also includes determining whether any stored shard files satisfy a compaction criteria based on a number of deleted data objects in each corresponding stored shard file. For each stored shard file satisfying the compaction criteria, the method also includes compacting the stored shard file by rewriting the remaining data objects of the stored shard file into a new shard file.

Abstract: A memory system includes a memory device including a controller, a nonvolatile memory including physical blocks, a physical block being a unit of data erasure, and a volatile memory that stores block mapping data that maps each physical block to a free or an active physical block and indicates an erase count thereof. The memory system further includes a host device configured to receive the block mapping data from the memory device, compare a first erase count of a free physical block with a second erase count of an active physical block and determine whether a predetermined condition is met, and upon determining that the predetermined condition is met, cause the controller to copy data in the active physical block to the free physical block, and cause the controller to update the block mapping data to remap the active and free physical blocks to free and active physical blocks, respectively.

Abstract: An electronic device is described which has at least one input interface to receive at least one item of a sequence of items. The electronic device is able to communicate with a server, the server storing a neural network and a process which generates item embeddings of the neural network. The electronic device has a memory storing a copy of the neural network and a plurality of item embeddings of the neural network. In the case when there is unavailability at the electronic device of a corresponding item embedding corresponding to the received at least one item, the electronic device triggers transfer of the corresponding item embedding from the server to the electronic device. A processor at the electronic device predicts at least one candidate next item in the sequence by processing the corresponding item embedding with the copy of the neural network and the plurality of item embeddings.

Abstract: In a system including a cross-resonance gate having a superconducting control qubit and having a superconducting target qubit coupled through a bus resonator, echo pulses are generated at a first frequency and directed to the control qubit, wherein the first frequency is on resonance with the control qubit. Cross-resonance pulses are generated at a second frequency on resonance with the target qubit and applied to the control qubit, wherein the generating and applying the cross-resonance pulses induce rotations on the target qubit through an interaction that is mediated by the bus resonator. Cancellation pulses are generated at the second frequency and applied to the target qubit. Sets of Hamiltonian tomographies may be measured to determine appropriate amplitudes and phases of the cross-resonance and cancellation pulses.

Abstract: Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a memory device can asynchronously indicate to a connected host that information in a mode register has been changed, obviating the need for repeated polling of the information and thereby reducing both command/address bus and data bus bandwidth consumption. In one embodiment, a memory device comprises a memory; a mode register storing information corresponding to the memory; and circuitry configured to, in response to the information in the mode register being modified by the memory device, generate a notification to a connected host device.

Abstract: Methods, systems, and devices for timing chains for accessing memory cells are described to implement some delays at logic circuitry under an array of memory cells. The memory array logic may represent CMOS under array logic circuitry. A bank group logic may generate a first memory operation and a longer delay corresponding to a timing between the first operation and a second operation. The first operation may represent an access operation, a precharging operation, or the like. The memory array logic may be signaled regarding the first operation and may generate one or more smaller delays associated with one or more sub-operations of the first operation. The smaller delays may be tunable, which may support a memory device or controller to implement operations or sub-operations with different timings based on different processes, different memory cell characteristics, or different temperatures, among other examples.

Abstract: A memory module is configured to communicate with a memory controller. The memory module comprises DDR DRAM devices arranged in multiple ranks each of the same width as the memory module, and a module controller configured to receive and register input control signals for a read or write operation from the memory controller and to output registered address and control signals. The registered address and control signals selects one of the multiple ranks to perform the read or write operation. The module controller further outputs a set of module control signals in response to the input address and control signals. The memory module further comprises a plurality of byte-wise buffers controlled by the set of module control signals to actively drive respective byte-wise sections of each data signal associated with the read or write operation between the memory controller and the selected rank.

Abstract: Examples disclosed herein relate to updating memory management information to boot an electronic device from a reduced power mode. In one implementation, prior to entering a reduced power mode, an electronic device creates a snapshot of instructions in a logically volatile partition of a partitioned persistent memory and manage the snapshot as a logically persistent partition. Prior to entering a resume mode, the electronic device updates memory management information to remap a portion of the partitioned memory resource including the snapshot to be managed as a logically volatile partition. The electronic device may resume execution from the snapshot.

Abstract: A method of operating a storage controller is provided. The method includes receiving a request from a partition creator, for a first partition within a storage system, the first partition comprising one or more sequentially numbered data blocks, and receiving first partition parameters from the partition creator, the first partition parameters comprising a size of the one or more sequentially numbered data blocks. The method also includes creating the first partition within the storage system, through a storage interface, based on the first partition parameters, receiving first host data from a host, configuring the first host data as first storage data for storage within the first partition within the storage system, and sequentially storing the first storage data in the one or more sequentially numbered data blocks in the first partition, through the storage interface.

Abstract: A power supply unit having a circuit for uninterrupted power supply comprises a first DC-DC converter arranged on the input side, at least one output configured for outputting an output DC voltage, and at least one first output switching controller. A DC link is arranged between the first DC-DC converter and the at least one output switching controller for regulating the at least one output DC voltage on the output side. The first DC link is connected to an energy storage module.

Abstract: A cluster of data transfer devices is used to augment the capabilities of a data storage system. For example, the cluster of data transfer devices may be configured to store a portion of a bundle of redundancy coded shards in a similar fashion as a data storage system. As another example, the cluster may be configured to provide other capabilities incident to the devices used, such as computational capabilities. Data stored on the cluster may be read from and written directly to the cluster without transfer of data to the data storage system. In some embodiments, a connecting entity (such as a customer entity) may interchangeably interface with the data storage system and the cluster, and the requested capabilities may be directed to either in a fashion that is transparent to the requestor.

Abstract: A system includes a volatile random access memory storing first header data and a first data block, the first header data including descriptive information and a first pointer to the first data block, and a non-volatile random access memory. The system includes determination of a memory size associated with the first header data and the first data block, allocation of a first memory block of the non-volatile random access memory based on the determined memory size, determination of an address of the non-volatile random access memory associated with the allocated first memory block, and writing of the descriptive information and a binary copy of the first data block at the address of the non-volatile random access memory.

Abstract: In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

Abstract: A method for fast initialization of a tactical data processing device, includes producing a bootable installation medium suitable for a small set of data processing devices; unlocking a read interface of a medium to allow applications to be executed through the interface from a medium connected to the interface; connecting the installation medium to the unlocked read interface; boot-up of the tactical data processing device; selecting a profile from a list of possible profiles; executing an installation by the execution of a plurality of commands, wherein the plurality of commands depends on the selected profile; locking of a read interface of a medium to prohibit applications being executed through the interface.

Abstract: Systems and methods are disclosed for providing directory data access in a data storage system. A network-attached storage device (NAS) includes a host interface for communicating with a host, an interface for communicating with a data storage drive associated with the NAS, a cache memory, and a controller configured to enter a power-saving mode by requesting directory data from the data storage drive, storing the directory data in the cache memory, and after requesting the directory data, sending a standby command to the data storage drive.

Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

Abstract: A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.

Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.

Abstract: A combination of a component-based automation framework, software-based redundancy patterns, and a distributed, reliable runtime manager, is able to detect host failures and to trigger a reconfiguration of the system at runtime. This combined solution maintains system operation in case a fault occurs and, in addition, automatically restores fault tolerance by using backup contingency plans, and without the need for operator intervention or immediate hardware replacement. A fault-tolerant fault tolerance mechanism is thus provided, which restores the original level of fault tolerance after a failure has occurred—automatically and immediately, i.e., without having to wait for a repair or replacement of the faulty entity. In short, the invention delivers increased availability or uptime of a system at reduced costs and complexity for an operator or engineer by adapting automatically to a new environment.

Abstract: A data transfer device is used to augment the capabilities of a data storage system. The data transfer device may be capable of persistently storing data for an indeterminate amount of time, and may be configured to store a portion of a bundle of redundancy coded shards that span between the data transfer device and a data storage system configured to store the remainder of the bundle. Data stored on the data transfer device may be read from and written directly to the data transfer device without transfer of data to the data storage system. If the data transfer device is not available, the remaining shards of the bundle may provide a regenerated, original form of the data.

Abstract: For system management applied to a computer system, a power supply of the computer system starts to power a motherboard and a CPU thereon. A reset holding module in a system management controller holds the CPU in a Power-on Reset (PoR) state. The system management controller executes an operation requested by a user. The reset holding module releases the CPU from the PoR state in response to the system management controller completing the operation.

Abstract: A method for managing main memory including DRAM and NVRAM in a computer depending on the operation state of the computer is provided. The method includes: (a) upon start of the computer, loading a program and the like into the DRAM, and loading predetermined read-only data and the like into the NVRAM; (b) in a state transition from a normal operation to a suspend state, moving data in the DRAM to the NVRAM; (c) in a state transition from the suspend state to the normal operation, reading data from the NVRAM for program execution; (d) in the case where a data write to the NVRAM occurs, stopping the data write, and moving data in a data area of the NVRAM subjected to the data write, to the DRAM; and (e) performing the data write to the DRAM to which the data has been moved.

Abstract: An endurance parameter value of a non-volatile memory included in a non-volatile dual in-line memory module (NVDIMM) can be monitored and compared against a warning threshold value. In response to the endurance parameter exceeding the warning threshold value, a system alert can be generated, within a host system of the NVDIMM, to inform a system user that the NVDIMM is approaching its end-of-life. If the endurance parameter exceeds a replacement threshold value greater than the warning threshold value, an upgrade process can be initiated. The upgrade process can include copying data from the first non-volatile memory to a volatile memory of the NVDIMM and copying, in response to the first non-volatile memory being replaced with a second non-volatile memory, the data from the volatile memory to the second non-volatile memory.

Abstract: A Solid State Drive (SSD) (505) may include circuitry to receive data from streams (305, 320, 335, 350). Each stream (305, 320, 335, 350) may have a Time-To-Live (TTL) (310, 325, 340, 355). Selection logic (525) may select a stream (305, 320, 335, 350) to write to a block (103). Writing logic (530) may then write data from the selected stream (905) to the block (103). The SSD (505) may change which stream (305, 320, 335, 350) is written to the block (103) over time. As a result, the data stored in the block (103) should expire sooner overall, making garbage collection of the block (103) more efficient.

Abstract: An endurance parameter value of a non-volatile memory included in a non-volatile dual in-line memory module (NVDIMM) can be monitored and compared against a warning threshold value. In response to the endurance parameter exceeding the warning threshold value, a system alert can be generated, within a host system of the NVDIMM, to inform a system user that the NVDIMM is approaching its end-of-life. If the endurance parameter exceeds a replacement threshold value greater than the warning threshold value, an upgrade process can be initiated. The upgrade process can include copying data from the first non-volatile memory to a volatile memory of the NVDIMM and copying, in response to the first non-volatile memory being replaced with a second non-volatile memory, the data from the volatile memory to the second non-volatile memory.

Abstract: Embodiments of the inventive concept include a plurality of memory ranks, a buffer chip including a rank remap control section configured to remap a rank from among the plurality of memory ranks of the volatile memory module responsive to a failure of the rank, and a dynamic serial presence detect section configured to dynamically update a stated total capacity of the volatile memory module based at least on the remapped rank. In some embodiments, a memory module includes a plurality of memory ranks, an extra rank in addition to the plurality of memory ranks, the extra rank being a spare rank configured to store a new page corresponding to a failed page from among the plurality of ranks, and a buffer chip including a page remap control section configured to remap the failed page from among the plurality of ranks to the new page in the extra rank.

Abstract: A hybrid storage device that includes a hard-disk drive (HDD) and a flash memory is described. When control logic in the hybrid storage device receives a request from an external device to write a block of data to a logical address in a first portion of an address space that maps to the HDD, the control logic writes the block of data to the HDD. However, if there is a change in environmental state information of the hybrid storage device during the write operation, the control logic writes at least a portion of the block of data to a logical address for the block of data in a second portion of the address space which maps to the flash memory. Note that the address space may be common to the external device and the hybrid storage device.

Abstract: A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.

Abstract: Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.

Abstract: First data is received for storing in a first asymmetric memory device. A first writing phase is identified as a current writing phase. A first segment included in the first asymmetric memory device is identified as next segment available for writing data. The first data is written to the first segment. Information associated with the first segment is stored, along with information indicating that the first segment is written in the first writing phase. Second data is received for storing in the asymmetric memory. A second segment included in the first asymmetric memory device is identified as the next segment available for writing data. The second data is written to the second segment. Information associated with the second segment and the second memory block is stored along with information indicating that the second segment is written in the second writing phase.

Abstract: Computer-readable storage media, computing apparatuses and methods associated with persistent memory are discussed herein. In embodiments, a computing apparatus may include one or more processors, along with a plurality of persistent storage modules that may be coupled with the one or more processors. The computing apparatus may further include system software, to be operated by the one or more processors, to receive volatile memory allocation requests and persistent storage allocation requests from one or more applications that may be executed by the one or more processors. The system software may then dynamically allocate memory pages of the persistent storage modules as: volatile type memory pages, in response to the volatile memory allocation requests, and persistent type memory pages, in response to the persistent storage allocation requests. Other embodiments may be described and/or claimed.

Abstract: A future proof method and system for securely transferring digital data from a data owner to a data assignee through a third party involving securely registering the data owner possessing the digital data with the third party and securely predefining to the third party a trigger event associated with a data assignee, registering the data assignee with the third party, receiving encrypted digital data and an encrypted trigger event associated with the data assignee transmitted from the data owner to the third party, and securely transferring and releasing the digital data to the at least one data assignee by the third party upon validation by the third party of the occurrence of the trigger event in such a manner that digital data can be used by data assignee on data assignee system.

Abstract: A semiconductor memory apparatus includes a command input unit configured to generate an internal command in response to an external command and a selective input unit configured to transmit selection signals to one of a first internal circuit. The selective input unit transmits the selection signals to the first internal circuit when the internal command is not a predetermined command and transmits the selection signals to the second internal circuit when the internal command is the predetermined command.

Abstract: A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.

Abstract: A semiconductor device includes a column command generation unit suitable for generating a column command delayed by a first delay time from a source command, in response to a first control signal and the source command, a bank address generation unit suitable for generating a bank address delayed by the first delay time from a bank source address, in response to the first control signal and the bank source address, a precharge command generation unit suitable for generating a precharge command delayed by a second delay time from the column command, in response to a second control signal and the column command, and a precharge bank address generation unit suitable for generating a precharge bank address delayed by the second delay time from the bank address, in response to the second control signal and the bank address.

Abstract: A memory system includes a memory and a content addressable memory (CAM). The memory includes a plurality of address locations, wherein each address location configured to store data and one or more error correction bits corresponding to the data. The CAM includes a plurality of entries, wherein each entry configured to store an address value of an address location of the memory and one or more extended error correction bits corresponding to the data stored at the address location of the memory.

Abstract: A memory module having integrated circuit (IC) components, a termination structure, an address/control signal path, a clock signal path, multiple data signal paths and multiple strobe signal paths. The strobe signal paths and data signal paths are coupled to respective IC components, and the address/control signal path and clock signal path are coupled in common to all the IC components. The address/control signal path extends along the IC components to the termination structure such that control signals propagating toward the termination structure arrive at address/control inputs of respective IC components at progressively later times corresponding to relative positions of the IC components.

Abstract: A storage device includes a plurality of magnetic disk devices each having a write cache, a processor unit that redundantly stores data, a rebuild execution control unit that performs a rebuild process, a write cache control unit that, at the time of the rebuild process, enables a write cache of a storage device that stores rebuilt data, and a rebuild progress management unit that is configured using a nonvolatile memory and manages progress information of the rebuild process. In the case where power discontinuity is caused during the rebuild process and then power is restored, the rebuild execution control unit calculates an address that is before an address of last written rebuilt data by an amount corresponding to the capacity of the write cache based on the progress information of the rebuild process managed by the progress management unit and resumes the rebuild process from that calculated address.

Abstract: Example embodiments for configuring a serial non-volatile memory device may comprise a non-volatile configuration register to store a configuration value received from the processor, the configuration value to specify one or more attributes of a memory access operation. The configuration value may be read at least in part in response to power being applied to the memory device.