Abstract: For digest retrieval based on similarity search in deduplication processing in a data deduplication system using a processor device in a computing environment, input data is partitioned into fixed sized data chunks. Similarity elements and digest block boundaries and digest values are calculated for each of the fixed sized data chunks. Matching similarity elements are searched for in a search structure containing the similarity elements for each of the fixed sized data chunks in a repository of data. Positions of similar data are located in the repository. The positions of the similar data are used to locate and load into the memory stored digest values and corresponding stored digest block boundaries of the similar data in the repository. The digest values and the corresponding digest block boundaries of the input data are matched with the stored digest values and the corresponding stored digest block boundaries to find data matches.

Abstract: Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity. An indication of which of the physical memory blocks is active at any point in time is provided. A memory controller provides a non-duplicating write capability, where data to be written to the physical memory is compared to contents of all active physical memory blocks at the time of writing, to ensure that no two active memory blocks have the same data after completion of the non-duplicating write.

Abstract: A memory structure compresses a portion of a memory tag using an indexed tag compression structure. A set of higher order bits of the memory tag may be stored in the indexed tag compression structure, where the set of higher order bits are identified by an index value. A tag array stores a set of lower order bits of the memory tag and the index value identifying the entry in the tag compression structure storing the set of higher order bits of the memory tag. The memory tag may comprise at least a portion of a memory address of a data element stored in a data array.

Abstract: A memory system includes a memory module which further includes a set of memory devices. The set of memory devices includes a first subset of memory devices and a second subset of memory devices. An address bus is disposed on the memory module, wherein the address bus includes a first segment coupled to the first subset and a second segment coupled to the second subset. An address signal traverses the set of memory devices in sequence. The memory system also includes a memory controller which is coupled to the memory module. The memory controller includes a first circuit to output a first control signal that controls the first subset, such that the first control signal and the address signal arrive at a memory device in the first subset at substantially the same time.

Abstract: An apparatus for processing data from a host storage device includes a client processing device configured to be connected by a communication channel to the host storage device. The client processing device includes: a processor configured to request a data set stored at the host storage device, the data set associated with a globally unique identifier; and a cache configured to store a copy of the data set and the globally unique identifier based on the processor receiving the data set from the host storage device, the cache being a persistent storage configured to retain the copy of the data set until the processor stores a new data set in the cache, the cache configured to retain the copy of the data set independent of an amount of time that the data set is stored in the cache.

Abstract: The present disclosure may include a method of handling test packets in an apparatus with a first unit communicatively coupled with a second unit. The method may comprise designating a test packet with type information, the type information indicating whether the test packet is handled by the first unit, the second unit, or either unit. The method additionally may include setting one or more bits of a register of the first unit to select whether the first unit will handle all of the test packets with type information designating either unit. The disclosure further includes associated systems and apparatuses.

Abstract: A ternary content-addressable memory comprises a first switch, a first static random-access memory cell, a second switch and a second static random-access memory cell. The first switch is connected between a first search line and a match line. The first switch has a first control electrode. The first static random-access memory cell has a first storage node connected to the first control electrode of the first switch. The second switch is connected between a second search line and the match line. The second switch has a second control node. The second static random-access memory cell has a second storage node connected to the second control electrode of the second switch.

Abstract: Methods and apparatus for provisioning shared NFS storage in a cloud storage environment having a storage layer, a compute layer, a network layer connecting the storage layer and the computer layer, and a management layer coupled to the compute layer.

Abstract: A method of compressing a plurality of multi-dimensional keys includes receiving, by a computer, the plurality of multi-dimensional keys, where the plurality of multi-dimensional keys have a first length and determining a first plurality of bit slots that are common among the plurality of multi-dimensional keys, wherein the first plurality of bit slots are not a prefix. Also, the method includes forming a mask indicating the first plurality of bit slots and forming a pattern indicating values of the first plurality of bit slots. Additionally, the method includes determining a second plurality of bit slots that vary among the plurality of multi-dimensional keys and forming a plurality of compressed multi-dimensional keys indicating values of the second plurality of bit slots. Further, the method includes storing the mask, the pattern, and the plurality of compressed multi-dimensional keys.

Abstract: A semiconductor memory device includes a setting information area suitable for storing setting information necessary for driving of memory cells, a control logic suitable for loading the setting information stored in the setting information area on a content-addressable memory (CAM) block, a CAM state information storage block suitable for storing information on whether the setting information loaded on the CAM block is changed, wherein when a reloading operation of the setting information stored in the setting information area on the CAM block is requested, the control logic selectively performs the reloading operation based on the information stored in the CAM state information storage block.

Abstract: A computer-implemented method of caching data in a managed runtime computing environment can include loading source data and comparing content of the source data with at least one of a plurality of cache entries. Each cache entry can include a representation of previously received source data and a transformation of the previously received source data. A transformation for the source data from a cache entry can be selected or a transformation for the source data can be generated according to the comparison. The transformation for the source data can be output.

Abstract: A computer-implemented method and system for distributed concurrent data updating of a business object having a structured format.

Abstract: Hardware circuitry may evaluate minimal perfect hash functions mapping keys to addresses in lookup tables. The circuitry may include primary hash function sub-circuits that apply linear hash functions to input key values (using carry-free arithmetic) to produce primary hash values. Each sub-circuit may multiply bit vectors representing key values by a bit matrix and add a constant bit vector to the result. The circuitry may include a secondary hash function sub-circuit that generates secondary hash values by aggregating values associated with multiple primary hash values using signed, unsigned, or modular integer addition, or bit-wise XOR operations. Secondary hash values may be usable to access data values in the lookup table that are associated with particular input key values. The circuitry may determine the validity of input keys and may alter the configuration or contents of the lookup tables. The hash function sub-circuits may include programmable hash tables.

Abstract: A data structure includes three arrays. A first array includes a root node, one or more intermediate nodes, and one or more leaf nodes. A second array includes one or more slices, each of which includes one or more elements; a third array also includes one or more elements. Each root node and intermediate node in the first array points to a respective slice in the second array. Each element in the second array stores a byte and has an associated pointer that points either to a respective intermediate node or to a respective leaf node in the first array. Each leaf node in the first array points to a respective element in the third array, and each element in the third array stores a respective sub-string of bytes. The trie can be particularly advantageous, for example, in applications on resource-constrained computing devices, such as mobile phones, tablets, and other hand-held computing devices.

Abstract: A memory refresh method includes determining positions at which to insert refresh operations of weak rows of a memory block among regularly scheduled refresh operations of normal rows of the memory block. The refresh operations occur at a substantially constant refresh rate. The positions at which to insert are based on an actual weak page address. The method also includes performing inserted refresh operations at the determined positions to coordinate distribution of the inserted refresh operations among the regularly scheduled refresh operations.

Abstract: According to one embodiment, a memory system including a key-value store containing key-value data as a pair of a key and a value corresponding to the key, includes an interface, a memory block, an address acquisition circuit and a controller. The interface receives a data write/read request or a request based on the key-value store. The memory block has a data area for storing data and a metadata table containing the key-value data. The address acquisition circuit acquires an address in response to input of the key. The controller executes the data write/read request for the memory block, and outputs the address acquired to the memory block and executes the request based on the key-value store. The controller outputs the value corresponding to the key via the interface.

Abstract: First characteristic information indicating a characteristic of input data is extracted from the input data that is input as data to be stored in any of the storages. Second characteristic information elements are read from a memory unit storing the second characteristic information elements indicating respective characteristics of stored data elements stored in the storages. A specific storage in which the input data is to be stored is determined, out of the storages, by determining a degree of match between the extracted first characteristic information and the second characteristic information elements read. The input data to the determined specific storage is read. The second characteristic information element indicating the characteristic of the stored data element stored in the specific storage is updated, out of the second characteristic information elements retained in the memory unit, on the basis of the extracted first characteristic information.

Abstract: System and methods for enhanced data processing and analysis in a storage device, such as a solid state drive (SSD) include an SSD having a data storage and a controller. The data storage stores a plurality of data sets. The controller has a pattern buffer and a data engine. The controller receives a query, processes the query to extract a pattern, loads the pattern into the pattern buffer, and accesses the data storage. The data engine searches a data subset from the data storage for instances of the pattern using a rolling window method. The controller generates a result from the search.

Abstract: A scheme for non-volatile ternary content-addressable memory with resistive memory device is proposed. The non-volatile ternary content-addressable memory comprises five transistors including a pair of search transistors with a first search transistor and a second search transistor, a read transistor, a write transistor and a match line transistor, wherein a match line is coupled to the match line transistor; and a pair of variable resistances have a first variable resistance and a second variable resistance. The pair of search transistors is coupled to the pair of variable resistances.

Abstract: A filter in a DOCSIS bridge performs IP Filtering of incoming Ethernet packets in hardware. The filter includes a parser circuit which, in hardware, parses each of the incoming Ethernet packets and then utilizes the parsed information in combination with a content-addressable memory (CAM) that stores filtering information, to filter and route the incoming Ethernet packets. Detailed statistical data may also be generated to provide information on the type of filtering being performed by the DOCSIS bridge.

Abstract: A storage system has a data storage device, a tag storage device and a controller. The tag storage device has a plurality of first tag entries and a plurality of second tag entries, wherein each of the first tag entries is associated with one data storage line allocated in the data storage device. The controller is coupled between the data storage device and the tag storage device, and arranged to set a specific second tag entry in the tag storage device to associate with a specific data storage line with which a specific first tag entry in the tag storage device is associated.

Abstract: Aspects of the disclosure provide a circuit that includes a first memory, a second memory and a comparator. The first memory is configured to store a plurality of values corresponding to a first plurality of ranges and generate an output value in response to a lookup key. The output value is indicative of the lookup key matching a stored value corresponding to a first range in the first plurality of ranges. The second memory is configured to store limiting values of a second plurality of ranges, and output a set of limiting values for a second range in association with the first range based on the output value of the first memory. The comparator is configured to compare the input value with the set of limiting values to determine whether the second range is inclusive of the lookup key.

Abstract: A memory address space for each of a plurality of physical memories in a microprocessor-based system is allocated prior to knowing the desired logical size of at least one of the physical memories. At least two of the allocated memory address spaces overlap at least a portion of each other. After the system is fabricated, a pointer value set that corresponds to an address boundary between at least two physical memories of the fabricated system is set during boot time and/or during run time when the size of the physical memories are known. The technique provides a faster time-to-market for microprocessor-based systems by allowing, for example, Application Specific Integrated Circuits (ASICs) comprising microprocessor systems on-chip be manufactured prior to the final firmware and software being fully developed. Additionally, the subject matter disclosed herein permits changes in memory-space allocation for finalized ASIC designs.

Abstract: Methods and systems for feature extraction of LIDAR surface manifolds. LIDAR point data with respect to one or more LIDAR surface manifolds can be generated. An AHAH-based feature extraction operation can be automatically performed on the point data for compression and processing thereof. The results of the AHAH-based feature extraction operation can be output as a compressed binary label representative of the at least one surface manifold rather than the point data to afford a high-degree of compression for transmission or further processing thereof. Additionally, one or more voxels of a LIDAR point cloud composed of the point data can be scanned in order to recover the compressed binary label, which represents prototypical surface patches with respect to the LIDAR surface manifold(s).

Abstract: A device including a data analysis element including a plurality of memory cells. The memory cells analyze at least a portion of a data stream and output a result of the analysis. The device also includes a detection cell. The detection cell includes an AND gate. The AND gate receives result of the analysis as a first input. The detection cell also includes a D flip-flop including an output coupled to a second input of the AND gate.

Abstract: There is provided an externally readable memory for storing information in each memory address, and this memory is provided with an information refinement detection function; this memory comprises: an input means for entering first input data for comparing data items stored in the memory and second input data for comparing addresses in the memory, wherein the first and second comparison data are externally; means for determining matches/mismatches of both data items stored in the memory and addresses of the memory according to both of the input data provided by the input means, and further performing logic operations on both of the match/mismatch determination results; and means for outputting addresses with positive results of the logic operations. This memory may be applicable in a broad range of fields including intelligent information search as well as artificial intelligence.

Abstract: Examples are described herein of dynamic switching of data masking and data bus inversion functionality of a memory input. Both dynamic switching and a static setting for the memory input may be supported in some examples described herein. Use of a command indicating a functionality of the memory input is described.

Abstract: Storing and retrieving files based on hashes for the files. One method for storing files includes: identifying a file; identifying a hash calculated based on the file; renaming the file based on the hash based on the file; and storing the file in a particular location based on the hash calculated based on the file. Another method for retrieving files includes: identifying a hash for a given file; using the hash, traversing a hierarchical file structure to find a location where the given file should be stored; determining that the file is at the location; and as a result, retrieving the file.

Abstract: A network switch includes packet processing units in a first processor core. An interface module is connected to the packet processing units. The interface module supports a unified table search request interface and a unified table search response interface. A common memory pool is connected to the interface module. The common memory pool includes a variety of memory types configurable to support multiple parallel table search requests.

Abstract: According to one embodiment, a memory system including a key-value store containing key-value data as a pair of a key and a value corresponding to the key, includes a first memory, a control circuit and a second memory. The first memory is configured to contain a data area for storing data, and a table area containing the key-value data. The control circuit is configured to perform write and read to the first memory by addressing, and execute a request based on the key-value store. The second memory is configured to store the key-value data in accordance with an instruction from the control circuit. The control circuit performs a set operation by using the key-value data stored in the first memory, and the key-value data stored in the second memory.

Abstract: An example method includes partitioning a memory element of a router into a plurality of segments having one or more rows, where at least a portion of the one or more rows is encoded with a value mask (VM) list having a plurality of values and masks. The VM list is identified by a label, and the label is mapped to a base row number and a specific number of bits corresponding to the portion encoding the VM list. Another example method includes partitioning a prefix into a plurality of blocks, indexing to a hash table using a value of a specific block, where a bucket of the hash table corresponds to a segment of a ternary content addressable memory of a router, and storing the prefix in a row of the segment.

Abstract: The semiconductor device of the present invention includes a search memory mat having a configuration in which a location with which an entry address is registered is allocated in a y-axis direction, and key data is allocated in an x-axis direction and a control circuit connected to the search memory mat. In the search memory mat, a plurality of separate memories is formed such that a region to which the key data is allocated is separated into a plurality of regions along the y-axis direction. The control circuit includes an input unit to which the key data is input, a division unit which divides the key data input to the input unit into a plurality of pieces of key data, and a writing unit which allocates each piece of divided key data by the division unit into the separate memory using the divided key data as an address.

Abstract: A system including a source display, externally updatable, an image compression algorithm database, a network connection, and a frame transfer engine. The algorithm database comprises a plurality of image compression algorithms. The frame transfer engine is configured to receive a plurality of updates made to the source display, store at least some of the updates in a queue, and select, based on a bandwidth of the network connection, a size of the update, and sizes and times of updates currently present in the queue, an image compression algorithm in the algorithm database for current transfer over the network connection.

Abstract: A system, method, and computer program product are provided for utilizing a data pointer table pre-fetcher. In use, an assembly of a data pointer table within a main memory is identified. Additionally, the data pointer table is pre-fetched from the main memory. Further, data is sampled from the pre-fetched data pointer table. Further still, the sampled data is stored within a data pointer table cache.

Abstract: A network system for launching a cyber-offensive countermeasure to improve network security is provided. For example, a system that enables launching a cyber-offensive countermeasure on a network may include a receiving section that receives packets routed on the network and analyzes the received packets to detect an attack directed toward a device on the network when the attack is external to the device, an editing section that edits the received packets, and a transmitting section that transmits the edited packets on the network.

Abstract: An apparatus and method for saving power during TLB searches is disclosed. In one embodiment, a TLB includes a CAM having a plurality of entries each storing a virtual address, and enable logic coupled to the CAM. Responsive to initiation of a TLB query by a thread executing on a processor that includes the TLB, the enable logic is configured to enable only those CAM entries that are associated with the initiating thread. Entries in the CAM not associated with the thread are not enabled. Accordingly, an initial search of the TLB for responsive to the query is conducted only in the CAM entries that are associated with the thread. Those CAM entries that are not associated with the thread are not searched. As a result, dynamic power consumption during TLB searches may be reduced.

Abstract: An error correction code decoder, including a computational memory array having at least a variable node section, a check node section, and a plurality of computational memory cells, each cell capable of storing at least one bit of memory and of performing operations at least on the bit and each cell implementing one node. A controller instructs the computational memory to perform the operations and to write the results of computations on a block of variable nodes into associated set of blocks of check nodes and to write the results of computations on a block of check nodes into associated set of blocks of variable nodes.

Abstract: A ferroelectric memory device includes a memory array including a plurality of ferroelectric memory cells, a code generating circuit configured to multiply write data and a parity generator matrix to generate check bits, thereby producing a Hamming code having information bits and the check bits arranged therein, the information bits being the write data, and a driver circuit configured to write the Hamming code to the memory array, wherein the parity generator matrix has a plurality of rows, and a number of “1”s in each of the rows is an even number.

Abstract: A data storage device includes a nonvolatile memory device; and a controller suitable for controlling an operation of the nonvolatile memory device in response to a request from an external device, wherein the controller comprises a victim block setup unit suitable for setting a victim block for a merge operation based on an error count, which is detected when a read operation of the nonvolatile memory device is performed, and for storing information of the victim block for the merge operation, and wherein the controller converts the victim block into a free memory block during the merge operation and reuses the free memory block to store data.

Abstract: Embodiments of content addressable memories for internet protocol devices and operations are described herein. Other examples and related methods are also disclosed herein.

Abstract: Systems and methods may determine a boundary value data unit in a large data set in parallel with determining an associated index of the determined boundary value data unit into the large data set using a single instruction multiple data (SIMD) instruction set architecture and a specialized data layout of array entries. In one example, the specialized data layout of array entries combines a data value and its associated index to an array into a single array entry.

Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a base address, a starting bit position, and a mask size. In response to the command, the TM pulls an input value (IV). A selecting circuit within the TM uses the starting bit position and the mask size to select a first portion of the IV. The first portion of the IV and the base address value are summed to generate a memory address. The memory address is used to read a word containing multiple result values and multiple reference values from memory. A second portion of the IV is compared with each reference value using a comparator circuit. A result value associated with the matching reference value is selected using a multiplexing circuit and a select value generated by the comparator circuit. The TM sends the selected result value to the processor.

Abstract: A method and host device for packing and dispatching read and write commands are provided. In one embodiment, a host device receives commands from at least one application, wherein the commands include read commands and write commands. The host device stores the commands in the memory. The host device then selects the read commands from the memory and packs them together but separately from the write commands. The same thing is done for the write commands. The host device then sends the packed read commands and the packed write commands to the storage device. In another embodiment, the host device determines when to send the packed commands to the storage device based on at least one parameter.

Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. Only final result values are stored in memory. The command includes a base address, a starting bit position, and mask size. In response to the lookup command, the TM pulls an input value (IV). A selecting circuit within the TM uses the starting bit position and mask size to select a portion of the IV. The portion of the IV and the base address are used to generate a memory address. The memory address is used to read a word containing multiple result values (RVs) from memory. One RV from the word is selected using a multiplexing circuit and a result location value (RLV) generated from the portion of the IV. A word selector circuit and arithmetic circuits are used to generate the memory address and RLV. The TM sends the selected RV to the processor.

Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a base address, a starting bit position, and a mask size. In response to the lookup command, the TM pulls an input value (IV). The TM uses the starting bit position and the mask size to select a portion of the IV. A first sub-portion of the portion of the IV and the base address are summed to generate a memory address. The memory address is used to read a word containing multiple result values (RVs) from memory. One RV from the word is selected using a multiplexing circuit and a second sub-portion of the portion of the IV. If the selected RV is a final value, then lookup operation is complete and the TM sends the RV to the processor, otherwise the TM performs another lookup operation based upon the selected RV.

Abstract: In one example, a network device receives a packet to be forwarded according to a label switching protocol, determines a service to be performed on the packet by a service network device, sends a label request message to the service network device, wherein the label request message indicates support for labels having a particular length, wherein the particular length is larger than twenty bits (e.g., forty bits), and wherein the label request message specifies the service to be performed on the packet, receives, in response to the label request message, a label mapping message defining a label of the particular length, appends the label to the packet to form a Multi-Protocol Label Switching (MPLS)-encapsulated packet, and forwards the MPLS-encapsulated packet according to the label switching protocol.

Abstract: A pre-computation based TCAM configured to reduce the number of match lines being pre-charged during a search operation to save power is disclosed. The pre-computation based TCAM stores additional information in a secondary TCAM that can be used to determine which match lines in a primary TCAM storing data words to be searched need not be pre-charged because they are associated with data words guaranteed to not match. The additional information stored in secondary TCAM can include a pre-computation word that represents a range inclusive of a lower and upper bound of a number of ones or zeroes possible in a corresponding data word stored in the primary TCAM.

Abstract: A system and method for enforcing quotas in a data storage system. In one embodiment, a method includes the operations of receiving a first request that defines a storage quota for a pool of virtual tapes that is allocated to a user entity; defining the storage quota for the pool of virtual tapes according to the request, wherein the defined storage quota limits a quantity of data that the user entity can store in physical storage of the storage system; receiving a second request from the user entity to write data to the virtual tape of the pool of virtual tapes; and returning a first status that indicates the data to be written from the second request cannot be written and failing the second request where a quantity of the data from the user entity's second request exceeds the defined storage quota.

Abstract: A content addressable storage (CAS) system is provided in which each storage unit is assigned to one of a plurality of sibling groups. Each sibling group is assigned the entire hash space. Within each sibling group, the hash space is partitioned into hash segments which are assigned to the individual storage units that belong to the sibling group. Chunk retrieval requests are submitted to all sibling groups. Chunk storage requests are submitted to a single sibling group. The sibling group to which a storage request is submitted depends on whether any sibling group already stores the chunk, and which sibling groups are considered full.

Abstract: A method in an example embodiment includes creating a first search key from variable data of a message received in a network environment, creating a second search key from constant data of the message, identifying a first database entry in a first database based on the first search key, and identifying a second database entry in a second database based on the second search key. The method can also include performing an action associated with the first database entry when a correlation is identified between the first and second database entries. In specific embodiments, the variable data are modified and the constant data are not modified. The first search key can be created prior or subsequent to forwarding the message. In further embodiments, the correlation is identified when an offset of the first database entry is the same as an offset of the second database entry.