Abstract: Aspects of the invention include systems and methods for tree style memory zone traversal. A non-limiting example computer-implemented method includes receiving, by a processor, a request from a requestor for available memory space in a main memory. The processor searches a plurality of memory zones in the main memory for the requested available memory space, wherein the memory zones are arranged in a ring structure and a separate tree structure, and the searching is based at least in part on both of the ring structure and the tree structure. In response to the processor finding the requested available memory space, processor allocates the found available memory space to the requestor.

Abstract: A computer-implemented method, according to one embodiment, includes: receiving a sub-logical page read command for data stored in NVRAM at a first LBA, and creating a searchable entry which includes the first LBA. Data read from the NVRAM is also received, where the received data corresponds to a given LBA. In response to determining that the given LBA matches the first LBA of the searchable entry, a copy of the received data is stored in a buffer. Moreover, in response to determining that a received sub-logical page write command is for data stored in the NVRAM at the first LBA, the copy of the received data in the buffer is coalesced with data included in the sub-logical page write command to form a full-logical page write. Furthermore, instructions to perform the full-logical page write in the NVRAM are sent.

Abstract: Implementations described herein provide apparatus and methods for storing data in, and retrieving data from, storage buffer having an odd number of storage locations using minimal additional logic. A binary address symbol with a maximum value of one less than twice the number of storage locations is used to allow use of Gray code in transferring the storage location pointers between clock domains. An offset value is added to the binary address symbol to further facilitate use of Gray code. The Gray code is converted back to a binary symbol at the read side, the offset value is subtracted therefrom, and a pointer to a particular storage location is resolved.

Abstract: A method of allocating a virtual register stack (10) of a processing unit in a stack machine is provided. The method comprises allocating a given number of topmost elements (11) of the virtual register stack (10) in a physical register file (17) of the stack machine and allocating subsequent elements of the virtual register stack (10) in a hierarchical register cache (13) of the stack machine.

Abstract: Methods, systems, and apparatus, including an apparatus for processing an instruction for accessing a N-dimensional tensor, the apparatus including multiple tensor index elements and multiple dimension multiplier elements, where each of the dimension multiplier elements has a corresponding tensor index element. The apparatus includes one or more processors configured to obtain an instruction to access a particular element of a N-dimensional tensor, where the N-dimensional tensor has multiple elements arranged across each of the N dimensions, and where N is an integer that is equal to or greater than one; determine, using one or more tensor index elements of the multiple tensor index elements and one or more dimension multiplier elements of the multiple dimension multiplier elements, an address of the particular element; and output data indicating the determined address for accessing the particular element of the N-dimensional tensor.

Abstract: This disclosure relates to method and system for data compression and data storage optimization. The method of compression may include converting each data block into a matrix, compressing each data block by processing the corresponding matrix to form a minimum state matrix based on a sequential set of compression rules, deriving a granular metadata for each data block based on the corresponding minimum state matrix, and storing the granular metadata and the sequential set of compression rules for each data block. Further, the method of decompression may include accessing a granular metadata and a sequential set of compression rules for each data block, deriving a minimum state matrix for each data block based on the corresponding granular metadata, decompressing each data block by processing the corresponding minimum state matrix to form a matrix based on the sequential set of compression rules, and building each data block from the corresponding matrix.

Abstract: A processor may include reservation stations to host instructions waiting to be issued to the execution units. Instructions in reservation stations comprise wrap bits and indexes, assigned by modulo counters. If wrap bits of two instructions are equal, then instruction with smaller index is older. If wrap bits of two instructions are different, then instruction with larger index is older. Responsive to exception event, wrap bit and index of an instruction executed with exception is compared with wrap bits and indexes of instructions in reservation stations to determine relative age. Instructions younger than the instruction executed with exception may be flushed from the reservation stations. Instructions in reservation stations may be grouped in pairs. In each pair, older ready instruction is selected using ready-to-issue bits, wrap bits, and indexes. Grouping and selecting instructions is repeated until one instruction remains. The remaining instruction is referred to as the oldest ready instruction.

Abstract: A technique to enable efficient instruction fusion within a computer system is disclosed. In one embodiment, a processor includes multiple cores, each including a first-level cache, a fetch circuit to fetch instructions, an instruction buffer (IBUF) to store instructions, a decode circuit to decode instructions, an execution circuit to execute decoded instructions, and an instruction fusion circuit to fuse a first instruction and a second instruction to form a fused instruction to be processed by the execution circuit as a single instruction, the instruction fusion occurring when both the first and second instructions have been stored in the IBUF prior to issuance to the decode circuit, and wherein the first instruction was the last instruction to be stored in the IBUF prior to the second instruction being stored in the IBUF, such that the first and second instructions are stored adjacently in the IBUF.

Abstract: SPI frame for simultaneously entering 8 bit daisy-chain mode from 16 bit register addressable mode. Some products that implement SPI may be connected in a daisy chain configuration, the first slave output being connected to the second slave input, etc. The SPI port of each slave is designed to send out during the second group of clock pulses an exact copy of the data it received during the first group of clock pulses. The whole chain acts as a communication shift register; daisy chaining is often done with shift registers to provide a bank of inputs or outputs through SPI. Large latency occurs during the entry into daisy-chain mode which increases as a function of the number of linked SPI devices. A means for simultaneously instructing all connected devices to enter/enable daisy-chain mode is disclosed.

Abstract: A data recording and playback system and method with a memory device adapted to receive and temporarily store input signal data as data frames with time stamps, the memory device having addresses associated thereto, and a circular storage buffer having a memory mapped file with same address space as the memory device for storing the input signal data. In one embodiment, an event controller provides an event signal associated to time of an event, and an event processor is provided that copies plurality of data frames stored in the circular storage buffer that have time stamps proximate to the time of the event. Another embodiment is adapted to allow playback of stored input signal data from the circular storage buffer without interrupting simultaneous recording of new input signal data into the circular storage buffer.

Abstract: A split head invalidation system includes a first memory including a ring buffer, a second memory, and a processor in communication with the first memory. The processor includes a consumer processor and a producer processor. The consumer processor is configured to maintain a head and tail pointer, detect a request to copy a memory entry from the ring buffer, and consume the memory entry. Consuming the memory entry includes iteratively testing a value associated with the memory entry in a slot indicated by the head pointer, retrieving the respective memory entry from the slot, and advancing the head pointer to the next slot until reaching a threshold quantity of slots. Additionally, the consumer processor is configured to invalidate each slot from the head pointer to the tail pointer after reaching the threshold quantity.

Abstract: Techniques are provided in which a ring buffer comprises multiple slots for a queued sequence of data items. New data items are sequentially added to the queued sequence and sequentially removed for further processing. A base record comprises a reference indicator, wherein a value of the reference indicator is indicative of a current slot of the multiple slots of the ring buffer. A pending update record is provided comprising a subject slot indicator, an update slot indicator, and a next update pointer for pointing to another pending update record. The base record further comprises a pending update record pointer. When there is an update to be applied to the value of the reference indicator of the base record, but the update is out-of-order, i.e. references a different slot to the current slot, a new pending update record is generated indicative of the update. Techniques for allocating and releasing elements in an array shared by multiple threads are also disclosed.

Abstract: Embodiments are directed to a processor for adjusting an index, wherein the index identifies a location of an element within an array. The processor includes a shift circuit configured to perform a single operation that adjusts a first parameter of the index to match a parameter of an array address. The single operation further adjusts a second parameter of the index to match a parameter of an array element.

Abstract: A memory pipeline for performing a write operation in a memory device is disclosed. The memory pipeline comprises an input register operable to receive a first data word and an associated address to be written into a memory bank. The pipeline also comprises a first write register of a first pipe-stage coupled to the input register and operable to receive the first data word and the associated address from the input register, wherein the first write register is further operable to perform a first attempt at writing said data word into the memory bank. Further, the pipeline comprises a second write register of the second pipe-stage coupled to the first write register and operable to receive the first data word and the associated address from the first write register, wherein the second write register is further operable to perform a second attempt at writing the first data word into the memory bank at the location corresponding to the associated address.

Abstract: Techniques are described herein for automatic generation of multi-source breadth-first search (MS-BFS) from high-level graph processing language. In an embodiment, a method involves a computer analyzing original software instructions. The original software instructions are configured to perform multiple breadth-first searches to determine a particular result. Each breadth-first search originates at each of a subset of vertices of a graph. Each breadth-first search is encoded for independent execution. Based on the analyzing, the computer generates transformed software instructions configured to perform a MS-BFS to determine the particular result. Each of the subset of vertices is a source of the MS-BFS. In an embodiment, parallel execution of the MS-BFS is regulated with batches of vertices. In an embodiment, the original software instructions are expressed in Green-Marl graph analysis language.

Abstract: In one aspect, a method includes making a first active buffer a passive buffer, generating a second active buffer to receive new I/Os, making a list of locations that need realignment in the passive buffer, flushing open I/Os at a splitter, reading I/Os which need realignment, discarding re-aligned I/Os for overwritten areas and sending the passive buffer to a replica site.

Abstract: This invention provides a cache system and method based on instruction read buffer (IRB). When applied to the field of processor, it is capable of filling instructions to the instruction read buffer which can be directly accessed by processor core and the processor core outputs instruction to the processor core for execution autonomously and achieve a high cache hit rate.

Abstract: Certain example embodiments described herein relate to techniques for automatically protecting, or hardening, software against exploits of memory-corruption vulnerabilities. The techniques include arranging a plurality of guard regions in the memory in relation to data objects formed by the application program, identifying an access by the application program to a guard region arranged in the memory as a disallowed access, and modifying the execution of the application program in response to the identifying, the modifying being in order to prevent exploitation of the memory and/or to correctly execute the application program.

Abstract: Systems and methods are provided to allow advertisers to make ads available to publishers through an advertising system. The advertising system provides tamper proof tracking of conversion activity between publishers and advertisers. Further, advertisers can define plural different conversions to be associated with a single ad click through.

Abstract: Various aspects provide for managing data associated with a cache memory. For example, a system can include a cache memory and a memory controller. The cache memory stores data. The memory controller maintains a history profile for the data stored in the cache memory. In an implementation, the memory controller includes a filter component, a tagging component and a data management component. The filter component determines whether the data is previously stored in the cache memory based on a filter associated with a probabilistic data structure. The tagging component tags the data as recurrent data in response to a determination by the filter component that the data is previously stored in the cache memory. The data management component retains the data in the cache memory in response to the tagging of the data as the recurrent data.

Abstract: A scheduling apparatus for dynamically setting a size of a rotating register of a local register file during runtime ids provided. The scheduling apparatus may include a determiner configured to determine whether a non-rotating register of a central register file is sufficient to schedule a program loop; a selector configured to select at least one local register file to which a needed non-rotating register is allocated in response to a determination that the non-rotating register of a central register file has a size which is sufficient to loop a program loop; a scheduler configured to schedule a non-rotating register of the at least one selected local register file.

Abstract: Described systems and methods allow protecting a computer system from computer security threats such as malware and spyware. In some embodiments, a security application executes a set of detection routines to determine whether a set of monitored entities (processes, threads, etc.) executing on the computer system comprise malicious software. The detection routines are formulated in bytecode and executed within a bytecode translation virtual machine. Execution of a detection routine comprises translating bytecode instructions of the respective routine into native processor instructions, for instance via interpretation or just-in-time compilation. Execution of the respective routines is triggered selectively, due to the occurrence of specific events within the protected client system. Detection routines may output a set of scores, which may be further used by the security application to determine whether a monitored entity is malicious.

Abstract: A semiconductor memory device includes a nonvolatile semiconductor memory in which writing is carried out at a page unit and erasing is carried out at a block unit larger than the page unit, and a controller for transferring data between a host device and the nonvolatile semiconductor memory. The controller includes a log-management section that is configured to: (i) record a page unit of log data in a buffer area each time a monitored event (e.g., error) occurs, the buffer area being partitioned into a plurality of pages and the page unit of log data is recorded in a designated page of the buffer area, and (ii) prior to recording the page unit of log data in the designated page, copy part of the designated page to another page of the buffer area.

Abstract: Various embodiments are disclosed of a multiprocessor system with processing elements optimized for high performance and low power dissipation and an associated method of programming the processing elements. Each processing element may comprise a fetch unit and a plurality of address generator units and a plurality of pipelined datapaths. The fetch unit may be configured to receive a multi-part instruction, wherein the multi-part instruction includes a plurality of fields. A first address generator unit may be configured to perform an arithmetic operation dependent upon a first field of the plurality of fields. A second address generator unit may be configured to generate at least one address of a plurality of addresses, wherein each address is dependent upon a respective field of the plurality of fields. A parallel assembly language may be used to control the plurality of address generator units and the plurality of pipelined datapaths.

Abstract: A slot reservation method is disclosed. The slot reservation method generates slot reservations in two dimensions to address starvation and to reduce bounce of messages transmitted through an interconnect. An interconnect implemented using the slot reservation method is capable of being scaled to larger network-on-chip implementations.

Abstract: In general, techniques are described for parallelizing a high-volume data stream using a data structure that enables lockless access by a multi-threaded application. In some examples, a multi-core computing system includes an application that concurrently executes multiple threads on cores of the system. The multiple threads include one or more send threads each associated with a different lockless data structure that each includes both a circular buffer and a queue. One or more receive threads serially retrieve incoming data from a data stream or input buffer, copy data blocks to one of the circular buffers, and push metadata for the copied data blocks to the queue. Each of the various send threads, concurrent to the operation of the receive threads, dequeues the next metadata from its associated queue, reads respective blocks of data from its associated circular buffers based on metadata information, and offloads the block to a server.

Abstract: A data processing system includes a processor configured to execute processor instructions and a branch target buffer having a plurality of entries. Each entry is configured to store a branch target address and a lock indicator, wherein the lock indicator indicates whether the entry is a candidate for replacement, and wherein the processor is configured to access the branch target buffer during execution of the processor instructions. The data processing system further includes control circuitry configured to determine a fullness level of the branch target buffer, wherein in response to the fullness level reaching a fullness threshold, the control circuitry is configured to assert the lock indicator of one or more of the plurality of entries to indicate that the one or more of the plurality of entries is not a candidate for replacement.

Abstract: A multiprocessor system or a system of hardware accelerators is provided to reduce cache ping-ponging and to provide improved single producer single consumer (SPSC) queues and methods. The systems are configured for specifying separate cache attributes for inner (e.g., local) cache and outer (e.g., shared) cache for promoting lower system overhead. Separate cache attributes are specified such that shared variables are cacheable only in a cache level shared by multiple processors.

Abstract: Some of the embodiments of the present disclosure provide a system comprising a queue configured to store a plurality of instructions, wherein the queue comprises a plurality of entries, wherein each entry of the plurality of entries of the queue is associated with a corresponding identification comprising a corresponding wrap bit and corresponding position bits; and a processing unit configured to receive (i) a first identification associated with a first entry storing a first instruction, and (ii) a second identification associated with a second entry storing a second instruction, compare (i) a first wrap bit of the first identification and (ii) a second wrap bit of the second identification, and determine a relative age of the first instruction with respect to the second instruction.

Abstract: Embodiments of the disclosure serializing wrapping of a circularly wrapping trace buffer via a compare-and-swap (CS) instruction by a method including executing a CS loop to advance to a location in the buffer indicated by a next free pointer. The method also includes incrementing a master wrap sequence number each time the next free pointer returns to a top of the buffer and executing another CS loop to increment a wrap number stored in a trace block corresponding to the location indicated by the next free pointer. Based upon determining that the wrap number stored in the trace block is one less than or equal to the master wrap sequence number, the method includes reserving space in a buffer associated with the trace block and storing the wrap number stored in the trace block as an old wrap number and incrementing a use-count of the trace block.

Abstract: A system and method are disclosed is to prevent the screen tearing in a video display system with self-refresh features while limiting space used for memory size in the self-refreshing sink device. A flexible method is utilized to manage a frame buffer and control self-refresh display timing to prevent screen tearing. The sink device has capabilities including one or more of self-refreshing and applying single frame updates as well as burst single frame updates while self-refresh is active. The memory utilized by the frame buffer during self-refresh is limited to less than that needed to store two full frames of video.

Abstract: An impairment unit, method, and machine readable storage media for emulating network impairments. A first network interface may receive network traffic including a plurality of received packets. A classifier may determine an impairment class of each received packet based on test information contained within a payload portion of each received packet, the impairment class of each received packet being one of a plurality of impairment classes, each impairment class uniquely associated with a corresponding one of a plurality of impairment profiles. An impairment engine may impair each of the plurality of impairment classes in accordance with the corresponding impairment profile to provide impaired network traffic. A second network interface may transmit the impaired network traffic to the network.

Abstract: A mechanism is provided for recirculating transactions within a pipeline while reordering outputs. A set of transactions associated with a block of data is received and each transaction in the set of transactions is processed via the pipeline. For each transaction processed via the pipeline, responsive to the transaction exiting the pipeline, a determination is made as to whether the transaction needs further processing. Responsive to the transaction needing further processing, the transaction is re-circulated via the pipeline forming a recirculated transaction.

Abstract: In general, embodiments of the present invention provide a home storage system and method of production. Specifically, in a typical embodiment, the home storage system includes a main controller that is coupled to a display controller, an external memory controller, an external interface, and a PCI-Express-based hybrid RAID controller. Further, a set of semiconductor storage device (SSD) memory units and a set of hard disk drive (HDD/Flash) memory units are coupled to the hybrid RAID controller. The external interface allows the storage system to establish network connectivity, while the external memory controller allows the storage device to be coupled to different types of external memory devices.

Abstract: A transactional memory (TM) includes a control circuit pipeline and an associated memory unit. The memory unit stores a plurality of rings. The pipeline maintains, for each ring, a head pointer and a tail pointer. A ring operation stage of the pipeline maintains the pointers as values are put onto and are taken off the rings. A put command causes the TM to put a value into a ring, provided the ring is not full. A get command causes the TM to take a value off a ring, provided the ring is not empty. A put with low priority command causes the TM to put a value into a ring, provided the ring has at least a predetermined amount of free buffer space. A get from a set of rings command causes the TM to get a value from the highest priority non-empty ring (of a specified set of rings).

Abstract: A Solid State Drive (SSD) controller is disclosed. When a data read command is transmitted by a host, the SSD controller may select a representative pointer from at least one first pointer by checking a point in time when data writing is completed in a buffer by at least one memory, read the data from the buffer by referring to a second pointer, and transmit the read data to the host, based on the representative pointer.

Abstract: A microprocessor includes a memory interface to obtain data envelopes of a first length, and control logic to implement an instruction to load an initial data envelope of a stream of data values into a buffer, each data value having a second length shorter than the first length, the stream of data values being disposed across successive data envelopes at the memory interface. Another instruction merges current contents of the buffer and the memory interface such that each invocation loads one of the data values into a first register, and moves at least a remainder of the current contents of the memory interface into the buffer for use in a successive invocation. Another instruction loads a reversed representation of a set of data values obtained via the memory interface into a second register. Another instruction implements an FIR computation including a SIMD operation involving multiple data values of the stream and the reversed representation.

Abstract: An image forming apparatus includes a processor, and a storage controller that writes band data to a storage device and reads the band data. The processor: (a) generates a write-side process and a read-side process; (b) generates a write-side thread by the write-side process; (c) generates a read-side thread and a file read thread by the read-side process; (d) notifies the read-side process of an identifier within the storage device, and causes the storage controller to sequentially write the band data; and (e) requests the file read thread to cause the storage controller to sequentially read out the band data corresponding to the identifier and causes the storage controller to sequentially read out the band data and one or more subsequent band data.

Abstract: An image forming apparatus includes a processor, and a storage controller that writes band data to a storage device and reads the band data. The processor: (a) generates a write-side process and a read-side process; (b) generates a write-side thread by the write-side process; (c) generates a read-side thread and a file read thread by the read-side process; (d) notifies the read-side process of an identifier within the storage device, and causes the storage controller to sequentially write the band data; and (e) requests the file read thread to cause the storage controller to sequentially read out the band data corresponding to the identifier and causes the storage controller to sequentially read out the band data and one or more subsequent band data.

Abstract: A register file includes a substrate, a plurality of entries, and a plurality of read ports. Each entry includes a corresponding subset of a plurality of memory cells defined on the substrate. Each read port includes a plurality of access elements defined on the substrate. Each access element is associated with a particular common bit position of each of the entries. A plurality of entry access groups are disposed in adjacent columns on the substrate. Each entry access group is associated with a corresponding one of the plurality of entries and includes the access elements for all of the read ports for the corresponding entry.

Abstract: Disclosed are systems and methods for transporting data using shared memory comprising allocating, by one of a plurality of sender application, one or more pages, wherein the one or more pages are stored in a shared memory, wherein the shared memory is partitioned into one or more pages, and writing data, by the sender application, to the allocated one or more pages, wherein a page is either available for use or allocated to the sender applications, wherein the one or more pages become available after the sender application has completed writing the data. The systems and methods further disclose sending a signal, by the sender application, to a receiver application, wherein the signal notifies the receiver application that writing the data to a particular page is complete, reading, by the receiver application, the data from the one or more pages, and de-allocating, by the receiver application, the one or more pages.

Abstract: A multi-granularity parallel storage system including a plurality of memories, a shift generator, an address increment lookup unit, an address shifter, a row address generator, and a plurality of address adders. The shift generator is configured to generate a shift value. The address increment lookup unit is configured to generate input data for the address shifter. The address shifter is configured to cyclically shift the input data rightward by Shift elements and then output the shifted data. The row address generator is configured to generate a row address RowAddr and input the generated row address RowAddr to the other input terminal of each address adder. Each address adder is configured to perform a non-sign addition of the input data at the two input terminals to obtain a read/write (R/W) address for one of the memories and input the R/W address to an address input terminal of the memory.

Abstract: An indication of a virtual address is received. A current page size of a plurality of available page sizes is read from a register. A shift amount is determined based, at least in part, on the current page size. A bit shift of the virtual address is performed in which the virtual address is bit shifted by, at least, the determined shift amount.

Abstract: In described embodiments, a multiple first-in, first-out buffer pointers (multi-FIFO pointers) alignment system includes synchronization circuitry to align multiple FIFO buffer operations. A FIFO read clock stoppage signal is generated by master logic that stops the read clock shared by all the transmit channels and then re-starts the read clock to align them. The FIFO read clock stoppage signal is applied to the read clock of all FIFOs which need to be aligned and, when rate change is needed, the FIFO read clock stoppage signal suspends the read clock, causing local write and read pointers to be reset. After the FIFO read clock stoppage signal is de-asserted, the read clock starts to all FIFOs concurrently, thereby aligning the channels.

Abstract: An adaptive synchronous FIFO includes a plurality of input data latch stages that sample variable-length input data at a write clock frequency, and a data compression circuit that combines the variable-length input data, together with partial-row data from a row of the FIFO storage array, and writes the combined data at a read clock frequency. The number of data latch stages is adaptive according to the ratio of the read and write clock frequencies.

Abstract: A system according to one embodiment includes a processor; logic in the processor and/or a memory configured to determine a furthest physical position on a magnetic medium that unobscured data has been written to; and logic configured to store an indicator of the furthest physical position on at least one of the magnetic medium and a memory coupled thereto. A system according to another embodiment includes a processor; logic in the processor and/or a memory configured to receive an instruction to obscure data on a magnetic medium; logic configured to read an indicator of a furthest physical position on the magnetic medium that unobscured data has been written to; and logic configured to cause obscuring of the unobscured data on the magnetic medium, and terminating the obscuring upon reaching the physical position in the indicator.

Abstract: A microprocessor includes a memory interface to obtain data envelopes of a first length, and control logic to implement an instruction to load an initial data envelope of a stream of data values into a buffer, each data value having a second length shorter than the first length, the stream of data values being disposed across successive data envelopes at the memory interface. Another instruction merges current contents of the buffer and the memory interface such that each invocation loads one of the data values into a first register, and moves at least a remainder of the current contents of the memory interface into the buffer for use in a successive invocation. Another instruction loads a reversed representation of a set of data values obtained via the memory interface into a second register. Another instruction implements an FIR computation including a SIMD operation involving multiple data values of the stream and the reversed representation.

Abstract: An apparatus and method for improving synchronization between threads in a multi-core processor system are provided. An apparatus includes a memory, a first processor core, and a second processor core. The memory includes a shared ring buffer for storing data units, and stores a plurality of shared variables associated with accessing the shared ring buffer. The first processor core runs a first thread and has a first cache associated therewith. The first cache stores a first set of local variables associated with the first processor core. The first thread controls insertion of data items into the shared ring buffer using at least one of the shared variables and the first set of local variables. The second processor core runs a second thread and has a second cache associated therewith. The second cache stores a second set of local variables associated with the second processor core.

Abstract: An image forming apparatus includes a processor, and a storage controller that writes band data to a storage device and reads the band data. The processor: (a) generates a write-side process and a read-side process; (b) generates a write-side thread by the write-side process; (c) generates a read-side thread and a file read thread by the read-side process; (d) notifies the read-side process of an identifier within the storage device, and causes the storage controller to sequentially write the band data; and (e) requests the file read thread to cause the storage controller to sequentially read out the band data corresponding to the identifier and causes the storage controller to sequentially read out the band data and one or more subsequent band data.

Abstract: According to an embodiment, an information processing apparatus includes a plurality of cores, a shared resource that can be shared by the plurality of cores, and local registers that store configuration information peculiar to the respective cores. The shared resource is provided independently from the plurality of cores. The local registers are provided to the respective cores. This makes it possible to provide an information processing apparatus that can suppress increase in hardware resources even when the number of cores composing a multi-core system increases.