Abstract: Reduction of administrative overhead in maintaining network information, rapid convergence on an optimal routing path through the data network, and utilization of only required network resources are realized by a novel method for establishing a call path between network users. The method is based upon deployment of a network information server that stores network topology information and that is addressable by each end user. In this method, the network information server receives a request to establish a call path. The request identifies at least the calling party. In response to the request, the network information server determines a network traversal between the calling party and a root network wherein the network traversal includes call path information about the sub-networks between the calling party and the root network. The request for establishing a call path can also identify the called party.

Abstract: Provided is an information processing apparatus including a local memory for storing a control program, a flash memory for storing a boot program, a processor for controlling the overall controller, a chipset for relaying the transfer of data among the respective components, and a logical control circuit arranged between the chipset and the flash memory. The logical control circuit performs information conversion processing to accommodate the logical configuration of the chipset and the flash memory when sending and receiving information between the chipset and the flash memory. This information conversion processing includes the steps of translating a serial address signal output from the chipset into a parallel address signal, translating a serial data signal output from the chipset into a parallel data signal, and translating a parallel data signal output from the flash memory into a serial data signal.

Abstract: A method and system for accessing a non-volatile memory is disclosed. The method includes writing a first stream of data to a first block of a first region of a non-volatile memory and detecting a full condition of the first block of the first region. Further, the method includes identifying data to be copied from the first block of the first region and copying the identified data from the first block of the first region to a second block of the first region of the non-volatile memory. The method also includes writing a second stream of data to the second block of the first region and writing a third stream of data to a first block of a second region of the non-volatile memory. In addition, the method includes detecting a full condition of the first block of the second region, identifying data to be copied from the first block of the second region and copying the identified data from the first block of the second region to a second block of the second region of the non-volatile memory.

Abstract: A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of physical memory circuits and a system. The interface circuit is operable to interface the physical memory circuits and the system for simulating at least one virtual memory circuit with a first power behavior that is different from a second power behavior of the physical memory circuits.

Abstract: A method for accessing cells of a ring buffer by one or more writers, comprising: storing a current writer cell position value in each of a done writer index and a reserved writer index; storing a current reader cell position value in a done reader index; copying the current writer cell position value to an old writer variable of a writer of the one or more writers; assigning a trial next writer cell position value to a new writer variable of the writer; accepting the trial next writer cell position value if the trial next writer cell position value is not equal to the done reader index value; as a single operation, first, accepting the trial next writer cell position value as a next writer cell position value if the reserved writer index value is equal to the old writer variable value, and second, replacing the reserved writer index value with the new writer variable value; writing data by the writer to a cell of the ring buffer indicated by the next writer cell position value; and, when the done writer inde

Abstract: A single-wire communication bus couples a transmitting device to a UART in a receiving device. Flow control circuitry in the UART fills a transmit memory buffer with remote data. The UART supplies a remote start bit onto the single-wire bus for each byte of remote data written into the transmit memory buffer. After detecting a remote start bit on the single-wire bus, the transmitting device supplies initial data bits and a stop bit, which together form an RS232 character. Data flow is controlled when the UART supplies a subsequent remote start bit only after data has been read out of the UART freeing up bytes in a receive memory buffer. After the transmitting device detects the subsequent remote start bit, the transmitting device supplies subsequent data bits onto the single-wire bus. In another embodiment, flow control circuitry functionality is performed by flow control code in the receiving device operating system.

Abstract: A method and apparatus for implementing out-of-order memory transactions in a multithreaded, multicore processor. In the present invention, circular queue comprising a plurality of queue buffers is used to store load data returned by a memory unit in response to a request issued by a processing module, such as a stream processing unit, in a processing core. As requests are issued, a destination queue buffer ID tag is transmitted as part of the request. When the request is returned, that destination number is reflected back and is used to control which queue within the circular queue will be used to store the retuned load data. Separate pointers are used to indicate the order of the queues to be read and the order of the queues to be written. The method and apparatus implemented by the present invention allows out-of-order data to be processed efficiently, thereby improving the performance of a fine grain multithreaded, multi-core processor.

Abstract: A reset system for a buffer and a method thereof are disclosed. The reset system of the present invention includes a resettable flag in the buffer and a control unit. The reset method is to set the resettable flag and reset buffer so tat each exchanged processing unit can re-read data in the buffer for processing. Moreover, the buffer further includes an overwriteable flag so as to prevent the data in the buffer to be overwritten and get lost.

Abstract: Various techniques for manipulating data using access states of memory, access control fields of pointers and operations, and exception raising and exception trapping in a multithreaded computer system. In particular, the techniques include synchronization support for a thread blocked in a word, demand evaluation of values, parallel access of multiple threads to a list, synchronized and unsynchronized access to a data buffer, use of forwarding to avoid checking for an end of a buffer, use of sentinel word to detect access past a data structure, concurrent access to a word of memory using different synchronization access modes, and use of trapping to detect access to restricted memory.

Abstract: Techniques for mirroring circular buffer mapping are discussed. Mirroring mapping for buffered message data, such as streaming data which may permit rapid data access for message data is circularly buffered. A first map and a second map may be linearly arranged in virtual memory space such that a reading of the first and or second maps, beginning from a fixed position within one of the maps, may permit parsing of the message data as if, the message was linearly arranged in the buffer.

Abstract: A data processing apparatus comprising a register bank, a shadow register and an arithmetic operation unit is provided. The register bank comprises a number of registers for respectively storing a number of operands, respectively, wherein the registers are n-bit registers, and n is a nature number. The shadow register is for storing first backup operand for making a backup of a first operand, which is stored in a first register among the registers in response to first control signal. The arithmetic operation unit is for performing at least an arithmetic operation on the operands to obtain an operational data, and storing the operational data in the first register in response to an arithmetic operation command.

Abstract: Buffer management system. A ring buffer may be implemented. The ring buffer includes a number of zones. Each of the zones includes state fields. The state fields include a filled indicator indicating whether the zone is full. The state fields for the zone further include a committed indicator indicating whether data in the zone is readable. The state fields for the zone also include a recycling indicator indicating whether the zone can be recycled. The ring buffer includes entries in the zones. Each of the entries includes state information. The entry state information includes a zone offset indication indicating a memory offset into the zone. The entry state information further includes a size indicating the size of the entry.

Abstract: A data output apparatus includes a disk drive for driving a magneto-optical disk. Compressed image data recorded on the magneto-optical disk is transferred from the magneto-optical disk to an SDRAM according to a transfer instruction set in an instruction list and then output through an expansion process by a JPEG codec. A size of the compressed image data for which the transfer instruction is set in the instruction list and which has not yet been transferred to the SDRAM, and a size of the compressed image data for which the transfer instruction is set in the instruction list and which has not yet been expanded are detected by a CPU. The CPU suspends an output of an expansion instruction to the JPEG codec when a difference between the detected sizes is below a threshold value.

Abstract: The invention provides an asynchronous first in first out (FIFO) interface and operation method wherein a read-out clock and a write-in clock of the asynchronous FIFO interface is asynchronous. The asynchronous FIFO interface comprises a FIFO buffer, a clock controller and a variable integer divider. The FIFO buffer inputs at least one data with the write-in clock, and outputs the at least one data with the read-out clock. The clock controller outputs a clock control signal according to a number of data stored in the FIFO buffer. The variable integer divider divides a first signal to generate the read-out clock or the write-in clock by an integer divisor controlled by the clock control signal in order to adjust the number of data stored in the FIFO buffer.

Abstract: Embodiments may logic such as hardware and/or code within heterogeneous multi-core processor or the like to coordinate reading from and writing to buffers substantially simultaneously. Many embodiments include multi-buffering logic for implementing a procedure for a processing unit of a specialized processing element. The multi-buffering logic may instruct a direct memory access controller of the specialized processing element to read data from some memory location and store the data in a first buffer. The specialized processing element can then process data in the second buffer and, thereafter, the multi-buffering logic can block read access to the first buffer until the direct memory access controller indicates that the read from the memory location is complete. In such embodiments, the multi-buffering logic may then instruct the direct memory access controller to write the processed data to other memory.

Abstract: A method and apparatus is provided to enable provision of requested data within two clock cycles when performing a swap operation between an accessible memory cell and a background memory in a computer. In a first clock cycle, memory addresses to be used in the swap operation are decoded. In a high phase of a second clock cycle, requested data is restored from the background memory to an accessible memory cell. Because the data previously stored in the accessible memory cell is duplicated in a shadow memory cell, the restoration of data to the accessible memory cell is performed without data loss. In a low phase of the second clock cycle, the requested data is available for reading. During a third cycle, data is saved from the shadow memory cell to the background memory, and the shadow memory cell is made consistent with the accessible memory cell.

Abstract: Methods and apparatus are provided for performing circular buffer addressing. Upper boundaries, lower boundaries, circular buffer lengths, addresses, and offsets are set to allow circular buffer access efficiency. An addition/subtraction unit is provided to simplify implementation. Comparators are rearranged and in some instances replaced with combined adder/comparator logic units. The additional logic units and the rearrangement allow efficient implementation of circular buffer addressing, particularly on programmable chips.

Abstract: A storage system is provided with an ASIC having an interconnect selectively coupling a plurality of dedicated purpose function controllers in the ASIC to a policy processor, via a list manager in the ASIC communicating on a peripheral device bus to which the policy processor is connected, and an event ring buffer to which all transaction requests from each of the plurality of function controllers to the policy processor are collectively posted in real time.

Abstract: A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for communicating a first number of power management signals to at least a portion of the memory circuits that is different from a second number of power management signals received from the system.

Abstract: A data buffer with a mechanism to optimize the setup/hold timing at the second flip-flop (or data register) so as to reduce the propagation delay time. The data buffer has a data path with a data input for receiving a digital data input signal, a clock input for receiving a clock input signal and a data output providing a digital data output signal for application to a data destination device, e.g. a RAM module in a memory system. The data buffer further has a clock output for providing an output clock signal to the data destination device and a phase locked loop (PLL) with a phase aligner and a first and second data register with respective clock inputs. The data input of the first data register is selectively coupled to the data input of the buffer or to a reference data input through a multiplexer. A reference data path is provided in parallel with the data path including a third data register with a data input to which the reference data input is coupled and a reference data output.

Abstract: A system for determining a position of an element in memory comprising a memory queue with a plurality of separate entries and propagate and generate logic in communication with the memory queue such that the propagate and generate logic is operable to inspect each the separate entry in the memory queue and to output one or more vectors indicating the position of the element in the memory queue.

Abstract: A method and apparatus for enqueuing and dequeuing packets to and from a shared packet memory, while avoiding collisions. An enqueue process or state machine enqueues packets for a communication connection (e.g., channel, queue pair, flow). A dequeue process or state machine operating in parallel dequeues packets and forwards them (e.g., to an InfiniBand node). Packets are stored in the shared packet memory, and status/control information is stored in a control memory that is updated for each packet enqueue and packet dequeue. Prior to updating the packet and/or control memory, each process interfaces with the other to determine if the other process is active and/or to identify the other process' current communication connection. If the enqueue process detects a collision, it pauses (e.g., for a predetermined number of clock cycles). If the dequeue process detects a collision, it selects a different communication connection to dequeue.

Abstract: A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for autonomously performing a power management operation in association with at least a portion of the memory circuits.

Abstract: A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system.

Abstract: A pointer comparing unit determines whether a value of a writing pointer is identical to a value of a reading pointer. When it is determined that the value of the writing pointer is different from the value of the reading pointer, an inter-memory transfer unit reads data stored in a location where a data transfer apparatus reads transmission data from a transmission ring buffer, transfers the data to a reception memory, and writes the data in a location designated by the reading pointer of a reception ring buffer. When the inter-memory transfer unit completes writing of the data in the reception ring buffer, a reading-pointer updating unit updates the reading pointer.

Abstract: A system includes a processor and a size bounded first-in first-out (FIFO) memory that is connected to the processor and a display is connected to the processor. A managing process to run on the processor to manage the FIFO memory structure. The FIFO memory includes a counter portion and a value portion for each of a tail portion and a head portion, and the managing process is non-blocking. The counter portion is used as a timestamp to maintain FIFO order.

Abstract: A circular buffer having an active cache window can be configured to temporarily allocate one or more locations in the active cache as permanent memory locations to eliminate the possibility of overwriting the contents of the permanent memory locations. The cache window can be a subset of the entire circular buffer. If contents within the cache window are identified as persistent data, the locations corresponding to the persistent data can be identified as permanent memory locations. The position of the cache within the circular buffer can be frozen based on the permanent memory locations. A write mask can be used to maintain the contents of the permanent memory locations, while the remainder of the cache is configured as a temporary circular buffer. Operation of the cache returns to the entire circular buffer once the contents of the permanent memory locations no longer need to be maintained.

Abstract: Various embodiments of a method, apparatus and article of manufacture to manage an index are provided. A circular index, having an index size, is provided. The circular index stores information to reference data in a sequential list. Accesses to the index and the list are monitored to provide at least one performance indicator. The performance indicator represents an effect of the index on accessing items in the list. The index size is changed based on the at least one performance indicator. The monitoring of the accesses and the changing of the index size are repeated.

Abstract: A first-in, first-out (FIFO) memory apparatus, a device, and a method include a memory that can store a data packet. A length of the data packet and the data packet are stored in the memory and the length and the data packet are flushed from the memory when the data packet is invalid.

Abstract: A method to update a data structure is disclosed. The method receives a write thread, and sets a data structure indicator to indicate that the data structure is unusable. The method creates (N) thread indicators, and assigns each of said (N) indicators to a different one of said (N) threads. Upon return to the thread dispatcher, the (i)th thread sees the data structure indicator which shows that the data structure is unusable. The method then sets the (i)th thread indicator to indicate that upon subsequent dispatches the (i)th thread will see the data structure indicator that shows that the data structure is unusable. After each of the (N) threads has seen the data structure indicator marking the data structure as unusable, the method sets the data structure indicator to indicate that the data structure is invalid, updates the data structure, and sets the data structure indicator to indicate that the data structure is valid.

Abstract: A method, apparatus, and computer program product are provided for implementing an enhanced circular queue using loop counts for command processing. A circular queue includes a plurality of entries for storing commands. As command entries are added to the queue at the head of the queue, a head loop count is stored with each command entry. A head pointer is updated to the head of the queue. When the head pointer wraps from a last queue entry to a first queue entry, the head loop count is incremented. A tail pointer points to an oldest command entry, and is updated when the oldest command entry is executed. When the tail pointer advances and wraps from a last queue entry to a first queue entry, the tail pointer loop count is incremented.

Abstract: A method and system for externalizing conditional logic for an integrated programming architecture provides a static tree structure traversed by a dynamic object collector. The tree structure includes a plurality of conditional nodes and a plurality of branches for testing at least one conditional statement. Each conditional node associates with one conditional object for testing conditional statements and one or more aspect objects. The plurality of branches establishes sequential links between a first conditional node and later conditional nodes. Evaluation instructions evaluate conditional statements relative to the conditional object. An object collector is instantiated for a particular set of data, such as a business event. Upon instantiation, the object collector cache and collected objects set is empty. Object collector traverses tree structure according to the evaluation result of the condition objects of the encountered condition nodes. Object collector evaluates this condition.

Abstract: A method for storing a data set having an enabled probe identification component and an associated data component in a buffer, including storing the data set at a current offset if the buffer has sufficient space to store the data set between a current offset and a limit of the buffer and the buffer is not marked as wrapped, marking the buffer as wrapped, setting the current offset to zero and setting a wrapped offset to zero, if the buffer does not have sufficient space to store the data set between a current offset and a limit of the buffer, and incrementing the wrapped offset by a stored data set size until there is sufficient space between the current offset and the wrapped offset to store the data set if the buffer is marked as wrapped, wherein the stored data set size is determined using an enabled probe identification associated with the stored data set.

Abstract: One aspect of the present invention relates to an information appliance for handling streaming information for storage in a circular buffer having a plurality of partitions defined by boundaries. The information appliance includes receiving streaming information from a source of streaming information and forming data blocks wherein each data block includes a payload field capable of holding a portion of the streaming information and an identification field indicative of the source of the streaming information. At least one data block is written to the circular buffer to partially fill a partition and at least one padding block is generated having a field indicative of non-streaming information and having a size being a function of remaining space in the partition. The padding block is written to the circular buffer adjacent a boundary of the partition.

Abstract: A method is provided for handling streaming information encoded with a data structure having a data block format. The data block format includes a data block having a header portion and an end portion. The header portion includes a prefix field having a pointer to a succeeding data block and the end portion includes a suffix field having a pointer to a preceding data block. A first data block size field is included in the header portion and indicates the size of the data block and a second data block size field is included in the end portion and indicates the size of the data block. A payload field is bounded by the first data block size field and a second data block size field. The payload field includes streaming information to be rendered.

Abstract: An information appliance receives streaming information and includes a buffer, a writer module, a reader module and a synchronizer. The buffer has a plurality of storage locations, a logical head, a logical tail and a valid data area between the logical head and the logical tail. The logical head and the logical tail move sequentially through the plurality of storage locations in a first logical direction. The writer module has a write position at the logical head of the buffer. The writer module receives the streaming information and writes the streaming information to the buffer at the write position. The reader module is coupled to the buffer and has a first read position which is temporally movable with respect to the write position. The synchronizer is coupled to the writer module and the reader module and maintains the first read position within the valid data area.

Abstract: In summary, one aspect of the present invention is directed to a method for a shared memory queue to support communicating between computer processes, such as an enqueuing process and a dequeuing process. A buffer may be allocated including at least one element having a data field and a reserve field, a head pointer and a tail pointer. The enqueuing process may enqueue a communication into the buffer using mutual exclusive access to the element identified by the head pointer. The dequeuing process may dequeue a communication from the buffer using mutual exclusive access to the element identified by the tail pointer. Mutual exclusive access to said head pointer and tail pointer is not required. A system and computer program for a shared memory queue are also disclosed.

Abstract: A write hub is described. The write hub has a plurality of registers. Each one of the registers helps generate a write address to a different memory bank from amongst a plurality of memory banks. Each of the registers are arranged in a ring so that each register can pass a pointer value toward a next register within the ring. The ring of registers further comprise a multiplexer between each of the registers. Each multiplexer has an output path that flows toward a next register within the ring relative to the multiplexer. Each multiplexer can introduce a pointer value to the ring at a next register within the ring.

Abstract: A method and apparatus for storing and reading an entry having one of a plurality of entry types and storing order information about stored entries, using a single addressable storage array. An index pipe maintains first in, first out order of the entries stored in the addressable storage array. Stages in the index pipe store a value representing the address of the stored entry in the storage array, the type of the stored entry, and the validity of the stored entry. Additional control logic implements order rules between entry types.

Abstract: A mechanism that enables allocation and recovery of buffer resources in both burst access and single access modes of operation is presented.

Abstract: In one embodiment, an apparatus is disclosed for capturing data on a debug bus comprising N registers connected in a ring, wherein data is clocked from one register to the next in the ring in only one direction. The apparatus comprises a counter that increments by one each time data is clocked from one register to the next; and logic for comparing a value of the counter with a preselected register address on each count of the counter, wherein the logic for comparing comprises a comparator having an input connected to receive the preselected register address, an input connected to receive the value of the counter, and an output operable to drive a select signal of a multiplexer provided for capturing data from the debug bus at an extraction point when the counter value is equal to the preselected register address.

Abstract: A method, system, and program storage medium for adaptively managing pages in a cache memory included within a system having a variable workload, comprising arranging a cache memory included within a system into a circular buffer; maintaining a pointer that rotates around the circular buffer; maintaining a bit for each page in the circular buffer, wherein a bit value 0 indicates that the page was not accessed by the system since a last time that the pointer traversed over the page, and a hit value 1 indicates that the page has been accessed since the last time the pointer traversed over the page; and dynamically controlling a distribution of a number of pages in the cache memory that are marked with bit 0 in response to a variable workload in order to increase a hit ratio of the cache memory.

Abstract: A chipset is initialized in a secure environment for an isolated execution mode by an initialization storage. The secure environment has a plurality of executive entities and is associated with an isolated memory area accessible by at least one processor. The at least one processor has a plurality of threads and operates in one of a normal execution mode and the isolated execution mode. The executive entities include a processor executive (PE) handler. PE handler data corresponding to the PE handler are stored in a PE handler storage. The PE handler data include a PE handler image to be loaded into the isolated memory area after the chipset is initialized. The loaded PE handler image corresponds to the PE handler.

Abstract: A processor architecture and instruction set is provided that is particularly well suited for cryptographic processing. A variety of techniques are employed to minimize the complexity of the design and to minimize the complexity of the interconnections within the device, thereby reducing the surface area required, and associated costs. A variety of techniques are also employed to ease the task of programming the processor for cryptographic processes, and to optimize the efficiency of instructions that are expected to be commonly used in the programming of such processes. In a preferred low-cost embodiment, a single-port random-access memory (RAM) is used for operand storage, few data busses and registers are used in the data-path, and the instruction set is optimized for parallel operations within instructions.

Abstract: A shift register is provided to monitor the difference between the read and write pulses to an elasticity buffer. The shift register essentially eliminates the need for any math functions in the elasticity buffer management logic. The shift register is as wide as the elasticity buffer is deep. In other words, for every word in the elasticity buffer, the shift register has a corresponding bit. Each time a word is written into the elasticity buffer without a simultaneous corresponding read, a value of “1” is shifted from a first end into the shift register, indicating that a space has been taken in the elasticity buffer. For every word read out of the elasticity buffer without a simultaneous corresponding write, a value of “0” (zero) is shifted from a second end of the shift register, indicating that one more space is available.

Abstract: In one embodiment, the invention is an apparatus. The apparatus includes a FIFO array having a first plurality of memory elements, each memory element having a predetermined number of bits, the FIFO array having a read pointer. The apparatus also includes a FIFO control register array having a second plurality of memory elements, each memory element of the second plurality corresponding to a memory element of the first plurality of memory elements, the read pointer suitable for accessing the FIFO control register array. The apparatus further includes a control logic block coupled to the FIFO control register array and the FIFO array. The control logic block is to receive a data value of the memory element of the FIFO control register array pointed to by the read pointer. The control logic block is also to signal the read pointer to stall responsive to the data value having a first value.

Abstract: A first logical memory address identifies a first logical memory location that is outside of a logical buffer space. The first logical memory address is received and is translated into a second logical memory address that identifies a second logical memory location that is within the logical buffer space.

Abstract: Disclosed is a method and apparatus for emulating a fiber channel port. A controller is provided according to the invention that includes a fabric port and a virtual N port. The controller is adapted to buffer incoming data and convert an N port address provided with the data by a host computer to an instruction to the picker to couple the disk drive corresponding to the requested N port address to the virtual N port.

Abstract: A device for interfacing asynchronous data, and more particularly, a device for interfacing asynchronous data using a first-in-first-out (FIFO) for preventing cutoff in data transfer by transferring the asynchronous data in accordance with a data transfer information signal while best satisfying a transfer request from a host between two devices that transfer the bi-directional asynchronous data. The provided device prevents control problems caused by the asynchronous data, so that the selected data is precisely and stably transferred even if the transfer speed is increased to equal that of an inner system clock. In addition, the output speed of a flag signal is faster than that of an existing method in which read and write addresses are compared, so that the remaining amount of data in the FIFO is precisely measured. As a result, asynchronous data is stably interfaced at a high speed.

Abstract: The invention comprises a hardware constructed address generator for a circular buffer which can be of any size and be in any position in memory. The address generator calculates both an absolute value and a wrapped value and selects one in accordance with whether the wrapped value falls within the boundaries of the buffer.