Abstract: Mechanism of efficient intra-die collective processing across the nodelets with separate shared memory coherency domains is provided. An integrated circuit die may include a hardware collective unit implemented on the integrated circuit die. A plurality of cores on the integrated circuit die is grouped into a plurality of shared memory coherence domains. Each of the plurality of shared memory coherence domains is connected to the collective unit for performing collective operations between the plurality of shared memory coherence domains.

Abstract: Compute nodes of a parallel computer organized for collective operations via a network, each compute node having a receive buffer and establishing a topology for the network; selecting a schedule for a broadcast operation; depositing, by a root node of the topology, broadcast data in a target node's receive buffer, including performing a DMA operation with a well-known memory location for the target node's receive buffer; depositing, by the root node in a memory region designated for storing broadcast data length, a length of the broadcast data, including performing a DMA operation with a well-known memory location of the broadcast data length memory region; and triggering, by the root node, the target node to perform a next DMA operation, including depositing, in a memory region designated for receiving injection instructions for the target node, an instruction to inject the broadcast data into the receive buffer of a subsequent target node.

Abstract: Systems and methods for dissolving the bottleneck issue of management task requested from management client to the storage virtualizer which consolidates externally attached storage arrays while providing a single management point of the entire system to the management client. Specifically, by utilizing the storage virtualizer to distribute received management tasks to respective external attached arrays, it can off load tasks, thus reducing the workload on the storage virtualizer itself. Because of the task distribution, the storage virtualizer consequently does not need to copy and hold detailed information of each storage volume in the respective attached storage arrays, thereby avoiding any inconsistent information between the arrays and the virtualizer when the configuration change has been done on the external array.

Abstract: A data processing device is described with a memory and a first and a second data processing component. The first data processing component comprises a control memory comprising, for each memory region of a plurality of memory regions of the memory, an indication whether a data access to the memory region may be carried out by the first data processing component and a data access circuit configured to carry out a data access to a memory region of the plurality of memory regions if a data access to the memory region may be carried out by the first data processing component; and a setting circuit configured to set the indication for a memory region to indicate that a data access to the memory region may not be carried out by the first data processing component in response to the completion of a data access of the first data processing component to the memory region.

Abstract: Deadlock is avoided in a grid storage system having superior scalability. Provided is a storage subsystem connected to a host computer for receiving a write or read access from the host computer. This storage subsystem includes a plurality of modules respectively having a storage resource, a switch for connecting the plurality of modules, a controller for controlling the transfer of a packet based on the write or read access from the host computer to a target module among the plurality of modules via the switch, and a memory storing a transfer rule of the packet. The controller controls the transfer of the packet based on the transfer rule.

Abstract: A system and method of parallel processing includes a computer system including a first processor, the first processor being a control flow type processor, a second processor, the second processor being a data flow type processor. The second processor is coupled to a second memory system, the second memory system including instructions stored therein in an order of execution and corresponding events data stored therein in the order of execution. A first one of the instructions are stored at a predefined location in the second memory system. The system also includes a run time events insertion and control unit coupled to the first processor and the second processor. The first processor, the second processor and the run time events insertion and control unit are on a common integrated circuit.

Abstract: An information processor for executing multiple applications including an external application under a control of an operating system, includes: a executing section that executes the external application in an isolated environment based on user identification information that is under the control of the operating system and allocated to the external application.

Abstract: Methods and apparatus relating to home agent data and memory management are described. In one embodiment, a scrubber logic corrects an error at a location in a memory corresponding to a target address by writing back the corrected version of data to the target location. In an embodiment, a map out logic maps out an index or way of a directory cache in response to a number of errors, corresponding to the directory cache, exceeding a threshold value. Other embodiments are also disclosed.

Abstract: A system and method for efficient garbage collection. A general-purpose central processing unit (CPU) partitions an allocated heap according to a generational garbage collection technique. The generations are partitioned into fixed size cards. The CPU marks indications of qualified dirty cards during application execution since the last garbage collection. When the CPU detects a next garbage collection start condition is satisfied, the CPU sends a notification to a special processing unit (SPU) corresponding to a determination of one or more card root addresses, each card root address corresponding to one of said marked indications. The SPU has a single instruction multiple data (SIMD) parallel architecture and may be a graphics processing unit (GPU). The SPU may utilize the parallel architecture of its SIMD core to simultaneously compute multiple card root addresses. Following, the SPU sends these addresses to the CPU to be used in a garbage collection algorithm.

Abstract: Disclosed are various systems, methods, and other embodiments for the control of access to a mass storage system. In one example, a plurality of buckets are maintained in mass storage system, each of the buckets being employed to store at least one data file. In a server, a use of the buckets by a plurality of entities that use a plurality of clients is facilitated for the storage of a plurality of files over a public network. The use of one of the buckets by the one of the entities is restricted to a namespace.

Abstract: Computers and other computing machines and information appliances having a modified computer architecture and program structure which enables the operation of an application program concurrently or simultaneously on a plurality of computers interconnected via a communications link or network using a special distributed runtime (DRT), and that provides for a redundant array of independent computing systems that include computer code distribution using code-striping onto the plurality of the computers or computing machines. A redundant array of independent computing systems operating in concert and code-striping features.

Abstract: The present disclosure discloses a method of complete mutual access of multiple-processors. The method comprises: a separate boot memory and a separate address mapping module are allocated for each processor; the processors perform the mutual access in the multiple-processors through the address mapping module after the processors are booted. The present disclosure also discloses a system for enabling complete mutual access of the multiple-processors. The method and the system creates the advantage of allowing complete mutual access of the multiple-processors, thereby sharing address space in the multiple-processors, sharing the peripheral controller and memory, improving expansibility and performance of the system.

Abstract: An architecture, system, and method for managing a data storage system by contacting a single processor in a data storage system having more than one processor. The single processor contacts each other peer processor in the data storage system and merges selected data from the single processor with data from the peer processor to determine the state of the data storage system.

Abstract: A computing system has an amount of shared cache, and performs runtime automatic parallelization wherein when a parallelized loop is encountered, a main thread shares the workload with at least one other non-main thread. A method for providing interprocedural prefetching includes compiling source code to produce compiled code having a main thread including a parallelized loop. Prior to the parallelized loop in the main thread, the main thread includes prefetching instructions for the at least one other non-main thread that shares the workload of the parallelized loop. As a result, the main thread prefetches data into the shared cache for use by the at least one other non-main thread.

Abstract: Aspects of the invention pertain to deterministic packet routing systems and methods in multiprocessor computing architectures. Packets are analyzed to determine whether they are memory request packets or memory reply packets. Depending upon the packet, it is routed through nodes in the multiprocessor computer architecture in either an XY or YX path. Request and reply packets are sent in opposing routes according to a deterministic routing scheme. Multiport routers are placed at nodes in the architecture to pass the packets, using independent request and response virtual channels to avoid deadlock conditions.

Abstract: An interface for a multi-processor gateway apparatus and method for using the same. A user device communicates with a multi-processor gateway apparatus over a wired or wireless path. A first processor within the multi-processor gateway apparatus provides the user device a user interface. The user interface allows the user to select a function that is managed by one of the multiple processors. If the selected function is assigned to the first processor, the function is performed by the first. However, if the selected function is performed by one of the other processors, the first processor executes calls to an API layer associated with the processor assigned to perform the requested function. The requested function is performed by the processor to which it is assigned and the results reported to the first processor. The first processor then provides the results of the request to the user device via the path.

Abstract: Various embodiments of the present invention manage concurrent accesses to a resource in a parallel computing environment. A plurality of locks is assigned to manage concurrent access to a plurality of parts of a resource. A usage of at least one of the plurality of parts of the resource is monitored. The assignment of the plurality of locks to the plurality of parts of the resource is modified based on the usage that has been monitored.

Abstract: A method for implementing a high-availability system that includes a plurality of controllers that each includes a shared memory. The method includes storing in the shared memory, by each controller, status data related to each of a plurality of failure modes, and calculating, by each controller, an availability score based on the status data. The method also includes determining, by each controller, one of the plurality of controllers having a highest availability score, and identifying the one of the plurality of controllers having the highest availability score as a master controller.

Abstract: A storage system provides virtual ports, and is able to transfer the virtual ports among physical ports located on multiple storage control units making up the storage system. The storage system is able to manage logical volumes and/or virtual volumes and virtual ports as a group when considering whether to move logical/virtual volumes and/or virtual ports to another storage control unit in the storage system. When the storage system is instructed to transfer volumes, virtual ports, or a group of volumes and virtual ports among the storage control units, the storage system determines whether an inter-unit network will be required to be used following the transfer. When the storage system determines that the inter-unit network will be required if the transfer takes place, the storage system determines and presents an alternate storage control unit for the transfer to avoid use of the inter-unit network, thereby avoiding degraded performance.

Abstract: The storage control apparatus arranges, in microprocessor packages, management information relating to logical volumes managed by the microprocessor packages. In a predetermined case, each of the management information is rearranged in appropriate places. The management information can be moved, taking into account the difference in the technical properties between a mainframe and an open system host.

Abstract: Hypervisor page fault processing logic is provided for a shared memory partition data processing system. The logic, responsive to an executing virtual processor of the shared memory partition data processing system encountering a hypervisor page fault, allocates an input/output (I/O) paging request to the virtual processor from an I/O paging request pool and increments an outstanding I/O paging request count for the virtual processor. A determination is then made whether the outstanding I/O paging request count for the virtual processor is at a predefined threshold, and if not, the logic places the virtual processor in a wait state with interrupt wake-up reasons enabled based on the virtual processor's state, otherwise, it places the virtual processor in a wait state with interrupt wake-up reasons disabled.

Abstract: Disclosed herein is an apparatus which may comprise a plurality of nodes. In one example embodiment, each of the plurality of nodes may include one or more central processing units (CPUs), a random access memory device, and a parallel link input/output port. The random access memory device may include a local memory address space and a global memory address space. The local memory address space may be accessible to the one or more CPUs of the node that comprises the random access memory device. The global memory address space may be accessible to CPUs of all the nodes. The parallel link input/output port may be configured to send data frames to, and receive data frames from, the global memory address space comprised by the random access memory device(s) of the other nodes.

Abstract: A method and data processing system for tracking global shared memory (GSM) operations to and from a local node configured with a host fabric interface (HFI) coupled to a network fabric. During task/job initialization, the system OS assigns HFI window(s) to handle the GSM packet generation and GSM packet receipt and processing for each local task. HFI processing logic automatically tags each GSM packet generated by the HFI window with a global job identifier (ID) of the job to which the local task is affiliated. The job ID is embedded within each GSM packet placed on the network fabric. On receipt of a GSM packet from the network fabric, the HFI logic retrieves the embedded job ID and compares the embedded job ID with the ID within the HFI window(s). GSM packets are forwarded to an HFI window only when the embedded job ID matches the HFI window's job ID.

Abstract: The invention discloses a memory management system and a memory management method are disclosed. The memory management system includes a first memory, at least one secondary memory, and a memory management device. The first memory includes a normal access memory bank and at least one switching access memory bank. The secondary memory includes at least one secondary access memory bank corresponding to the switching access memory bank. The memory management device reads/writes the normal access memory bank or the secondary access memory bank.

Abstract: An embedded memory system is disclosed. A main interface is configured to communicate with an electronic system via a main bus. A memory-sharing auxiliary interface is configured to communicate with the electronic system via a memory-sharing auxiliary bus. An arbiter is configured to arbitrate among the main interface, the memory-sharing auxiliary interface, a primary memory, and a secondary memory. Accordingly, the electronic system is capable of sharing either the primary memory or the secondary memory via the memory-sharing auxiliary interface and the memory-sharing auxiliary bus, and the embedded memory system is capable of sharing a system memory of the electronic system via the memory-sharing auxiliary interface and the memory-sharing auxiliary bus.

Abstract: An information processing device according to the present invention includes an operation unit that outputs an access request, a storage unit including a plurality of connection ports and a plurality of memories capable of a simultaneous parallel process that has an access unit of a plurality of word lengths for the connection ports, and a memory access control unit that distributes a plurality access addresses corresponding to the access request received for each processing cycle from the operation unit, and generates an address in a port including a discontinuous word by one access unit for each of the connection ports.

Abstract: A multiprocessor arrangement is disclosed, in which a plurality of processors are able to communicate with each other by means of a plurality of time-sliced memory blocks. At least one, and up to all, of the processors may be able to access more than one time-sliced memories. A mesh arrangement of such processors and memories is disclosed, which may be a partial or complete mesh. The mesh may to two-dimensional, or higher dimensional. A method of communication between processors in a multiprocessor arrangement is also disclosed, in which one or more processors are able to each access a plurality of memories, in each case by time-slicing.

Abstract: Improved approaches to manage cache data for applications operating in a data center environment are disclosed. Data requests incoming over a network are able to be responded to by an application in a consistent and rapid manner through intelligent management of cache data. When like applications are being concurrently operated, such as at a data center, cache data established by one application can be made available for use by another like application. As a result, cache data available to a given application is more likely to be useful to the application, particularly when the application has just been started (or restarted).

Abstract: A cluster system comprises a plurality of nodes that provides data-access service to a shared storage, each node having at least one failover partner node for taking over services of a node if the node fails. Each node may produce write logs for the shared storage and periodically send write logs at predetermined time intervals to a global device which stores write logs from each node. The global device may detect failure of a node by monitoring time intervals of when write logs are received from each node. Upon detection of a node failure, the global device may provide the write logs of the failed node to one or more partner nodes for performing the write logs on the shared storage. Write logs may be transmitted only between nodes and the global device to reduce data exchanges between nodes and conserving I/O resources of the nodes.

Abstract: A system and method for memory sharing among computer programs is disclosed. A method for memory sharing among computer programs includes identifying memory units of a plurality of memory units having identical contents, collapsing the identified memory units into a single merged memory page, and mapping the single merged memory page into an associated shared physical memory location. The method further includes when a request to write to a memory unit merged into the single merged memory page is received: copying, by a computer system, contents in the associated shared physical memory location to a different memory location, and redirecting, by the computer system, the request to the different memory location.

Abstract: A virtual machine (VM) runs on system hardware, which includes a physical network interface device that enables transfer of packets between the VM and a destination over a network. A virtual machine monitor (VMM) exports a hardware interface to the VM and runs on a kernel, which forms a system software layer between the VMM and the system hardware. Pending packets (both transmit and receive) issued by the VM are stored in a memory region that is shared by, that is, addressable by, the VM, the VMM, and the kernel. Rather than always transferring each packet as it is issued, packets are clustered in the shared memory region until a trigger event occurs, whereupon the cluster of packets is passed as a group to the physical network interface device.

Abstract: Technologies are generally described for a system for sending a data block stored in a cache. In some examples described herein, a system may comprise a first processor in a first tile. The first processor is effective to generate a request for a data block, the request including a destination identifier identifying a destination tile for the data block, the destination tile being distinct from the first tile. Some example systems may further comprise a second tile effective to receive the request, the second tile effective to determine a data tile including the data block, the second tile further effective to send the request to the data tile. Some example systems may still further comprise a data tile effective to receive the request from the second tile, the data tile effective to send the data block to the destination tile.

Abstract: A data processing apparatus reduces the number of the buffer SRAMs to decrease chip area. The data processing apparatus includes an SDRAM address allocation register that holds information indicating which region of the SDRAM will be allocated to each of the IPs, and a buffer SRAM address allocation register that holds information indicating which region of the first and second buffer SRAMs will be allocated to each of the IPs. The bus I/F stores the data read from the SDRAM into the second buffer SRAM with reference to the SDRAM address allocation register and the buffer SRAM address allocation register. Therefore, it is not necessary to provide each of the IPs with a buffer SRAM, which allows integration into a small number of buffer SRAMs.

Abstract: A hypervisor receives a memory page checksum from a guest operating system, which corresponds to a page of memory utilized by the guest. Next, the hypervisor proceeds through a series of steps to detect that the memory page checksum matches a checksum value included in a checksum entry item, which includes an identifier of a different guest. In turn, the hypervisor shares the page of memory between the guest and the different guest in response to detecting that the memory page checksum matches the checksum value included the checksum entry item.

Abstract: Systems and a method for storing data are provided. The protected memory system includes a memory array including a plurality of memory modules each separately located with respect to each other and a memory controller configured to receive data to be stored from the data acquisition unit, store the received data in corresponding memory locations in each of the plurality of memory modules wherein the stored data including error checking information, read data from a first one of the plurality of memory modules until a data error is detected at a first memory location, read data from a second memory location of a second one of the plurality of memory modules wherein the data read from the second memory location corresponds to the data read from the first memory location, and replace the data read from the first memory location with the data read from the second memory location.

Abstract: A system and method for controlling access to a computer provides for loose security within a local network while retaining strong security against external access to the network. In one embodiment, a user has access to trusted nodes in a secured group within an unmanaged network, without being required to choose, enter and remember a login password. To establish such a secure blank password or one-click logon account for the user on a computer, a strong random password is generated and stored, and the account is designated as a blank password account. If the device is part of a secured network group, the strong random password is replicated to the other trusted nodes. When a user with a blank password account wishes to log in to a computer, the stored strong random password is retrieved and the user is authenticated.

Abstract: A method and apparatus are provided for sharing multipath-accessible memory between a plurality of processors, the method including connecting the plurality of processors in read/write communication to a same shared memory region; connecting the plurality of processors in read communication to a same semaphore area; selectably connecting one of the plurality of processors in write communication to the same semaphore area; exchanging shared memory access command messages between two processors for negotiating access to the same shared memory region; and storing protected variables indicative of the currently negotiated access to the same shared memory region in the same semaphore area, wherein the shared memory region has a channel relative to each processor, each channel having at least one buffer disposed for transferring a plurality of data packets in a burst mode.

Abstract: Methods, apparatus, and products are disclosed for performing an allreduce operation using shared memory that include: receiving, by at least one of a plurality of processing cores on a compute node, an instruction to perform an allreduce operation; establishing, by the core that received the instruction, a job status object for specifying a plurality of shared memory allreduce work units, the plurality of shared memory allreduce work units together performing the allreduce operation on the compute node; determining, by an available core on the compute node, a next shared memory allreduce work unit in the job status object; and performing, by that available core on the compute node, that next shared memory allreduce work unit.

Abstract: A memory device loops back control information from one interface to another interface to facilitate sharing of the memory device by multiple devices. In some aspects, a memory controller sends control and address information to one interface of a memory device when accessing the memory device. The memory device may then loop back this control and address information to another interface that is used by another memory controller to access the memory device. The other memory controller may then use this information to determine how to access the memory device. In some aspects a memory device loops back arbitration information from one interface to another interface thereby enabling controller devices that are coupled to the memory device to control (e.g., schedule) accesses of the memory device.

Abstract: A memory system connected to another apparatus via a data crossbar, has a first memory, a second memory that forms a dual configuration together with the first memory, a first memory controller that transmits or receives data to be written into the first memory or data read out from the first memory to or from the other apparatus, a second memory controller that transmits or receives data to be written into the second memory or data read out from the second memory to or from the other apparatus, and a system controller that instructs the first memory controller and the second memory controller to read out, from the first memory and the second memory, data requested to be read out by the other apparatus if the system controller detects that any one of the first data crossbar and the second data crossbar being not capable of transmitting or receiving data.

Abstract: A system for sharing data between computer processes. The system includes a processor configured to implement a method that includes executing a plurality of independent processes on an application server, the processes including a first process and a second process. A shared memory utilized by the plurality of independent processes is provided. A single copy of the data and metadata are stored in the shared memory. The metadata includes an address of the data. The first process initiates the storing of the data in the shared memory. An address of the metadata is transferred from the first process to the second process to notify the second process about the data. The second process determines the address of the shared memory by reading the metadata. The data in the shared memory is accessed by the second process.

Abstract: A method and system for distributing and accessing data over multiple storage controllers wherein data is broken down into one or more fragments over the multiple storage controllers, each storage controller owning a fragment of the data, receiving a request for data in a first storage controller from one of a plurality of hosts, responding to the host by the first storage controller with the request if the first storage controller contains the requested data, forwarding the request to the second storage controller from the first storage controller if the first storage controller does not contain the requested data, responding to the first storage controller from the second storage controller with the request, and responding to the host from the first storage controller with the request.

Abstract: A method and apparatus for avoiding live-lock during transaction execution is herein described. Counting logic is utilized to track successfully committed transactions for each processing element. When a data conflict is detected between transactions on multiple processing elements, priority is provided to the processing element with the lower counting logic value. Furthermore, if the values are the same, then the processing element with the lower identification value is given priority, i.e. allowed to continue while the other transaction is aborted. To avoid live-lock between processing elements that both have predetermined counting logic values, such as maximum counting values, when one processing element reaches the predetermined counting value all counters are reset. In addition, a failure at maximum value (FMV) counter may be provided to count a number of aborts of a transaction when counting logic is at a maximum value.

Abstract: A multiple computer environment is disclosed in which an application program executes simultaneously on a plurality of computers (M1, M2, . . . Mn) interconnected by a communications network and in which the local memory of each computer is not maintained substantially the same by updating in due course. An address table mechanism is provided to permit access to an asset, object, or structure (i.e., memory location) for the purpose of updating, for example. Not all computers have the same memory, so it is not necessary for all computers to be updated.

Abstract: Systems and methods for accessing common registers in a multi-core processor are disclosed. In an embodiment a method may comprise streaming at least one transaction from one of a plurality of processing cores in a core domain directly to a register domain. The method may also comprise reassembling the at least one streamed transaction in the register domain for data access operations at the common registers.

Abstract: The invention discloses a memory management system and a memory management method are disclosed. The memory management system includes a first memory, at least one secondary memory, and a memory management device. The first memory includes a normal access memory bank and at least one switching access memory bank. The secondary memory includes at least one secondary access memory bank corresponding to the switching access memory bank. The memory management device reads/writes the normal access memory bank or the secondary access memory bank.

Abstract: A method of validating a digital certificate comprises retrieving from a first data store a digital certificate, retrieving from a second data store a plurality of certificate revocation lists (CRLs), and selecting one of the plurality of CRLs to validate the digital certificate as of a date which is before the current date.

Abstract: An information processing system includes a plurality of PMM and data transmission paths for connection between the PMM and transmitting a value of a PMM to another PMM. A memory of each PMM holds a list of values of first items arranged in the ascending order or descending order without overlap and/or a list of values of the second item to be shared. A memory module of each PMM transmits a value contained in the value list to another PMM, receives a value contained in the value list from the another PMM, references the value list of the first item and the value list of the second item of the another PMM, and generates a list of common values considering the values contained in the value lists of the first item and the second item of all the other PMM.

Abstract: Disclosed are computer systems, a plurality of methods and a computer program for preventing a delay in execution time of one or more instructions. The computer system includes: a lock unit for executing an instruction to acquire exclusive-use of the external resource and an instruction to release the exclusive-use of the external resource in the one or more threads; a counter unit for increasing or decreasing a value of a corresponding one of counters respectively associated with the threads; and a controller for controlling an execution order of the instructions to be executed by exclusively using the external resource and instructions that causes a delay in the execution time of the instructions to be executed by exclusively using the external resource.

Abstract: A method of transmitting data from a first module to addressable storage devices in a second module. The method comprises: transmitting from the first module to a second module in a first transmission cycle an address identifying a storage device in the second module for a data item; at the second module, determining the status of a storage location in the device identified by the address for holding a data item and dispatching in a second transmission cycle a pre-emptive acknowledgement signal, the state of which depends on the status of that storage location; transmitting in the second transmission cycle the data item from the first module to the second module; transmitting the address in a later transmission cycle from the first module to the second module; and selectively transmitting one of the data item and a next data item depending on the state of the pre-emptive acknowledgement signal.