Abstract: A system and method for providing roaming access on a network are disclosed. The network includes a plurality of wireless and/or wired access points. A user may access the network by using client software on a client computer (e.g., a portable computing device) to initiate an access procedure. In response, a network management device operated by a network provider may return an activation response message to the client. The client may send the user's username and password to the network provider. The network provider may rely on a roaming partner, another network provider with whom the user subscribes for internet access, for authentication of the user. Industry-standard methods such as RADIUS, CHAP, or EAP may be used for authentication. The providers may exchange pricing and service information and account information for the authentication session. A customer may select a pricing and service option from a list of available options.

Abstract: Methods, systems, and computer program products for controlling information read/write processing. The method includes assigning a plurality of division areas to a shared storage area for storing a shared object: specifying a division area used for read/write processing in accordance with user identification information for identifying a user; and executing the read processing for reading information from a specified division area and the write processing for writing information to the specified division area. The shared object is shared among a plurality of processes.

Abstract: In a semiconductor memory device, an update data control circuit is provided, which selectively couples a physical address input data line or an effective address input data line to a common input data line coupled to a physical address cell that stores a physical address page number. A control terminal of an update circuit of the physical address cell is coupled to a page size cell that stores page size information via an update control circuit, to control a write port of the physical address cell with the page size cell.

Abstract: Various methods and apparatus are described for a memory scheduler. The memory scheduler has a pipelined arbiter to determine which request will access the target memory core. Pipelining occurs in stages within the arbiter over a period of more than one clock cycle. The pipelined arbiter uses two or more weighting factors affecting an arbitration decision that are processed in parallel. A predictive scheduler in the memory scheduler uses data from a previous cycle to make the arbitration decision about a request during a current clock cycle in which the arbitration decision is made in order to increase overall system efficiency of requests being serviced in the integrated circuit.

Abstract: Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a plurality of logic elements, programmably configurable to implement user-defined combinatorial or registered logic functions, and an embedded processor portion coupled to the programmable logic portion. The embedded processor portion includes a processor, and a memory block coupled to the processor. The memory block includes a first plurality of memory cells for storing data, a second plurality of memory cells for storing data, a first port coupled to the first and second pluralities of memory cells, a second port coupled to the first and second pluralities of memory cells, and an arbiter coupled to the first port and the second port.

Abstract: A physical memory location among multiple programs is shared among multiple programs. In one embodiment, multiple memory units are scanned to detect duplicated contents in the memory units. The memory units are used by programs running on a computer system. A data structure is used to identify memory units of identical contents. To improve performance, an additional data structure can be used to identify memory units of identical contents. Memory units that are identified to have identical contents can share the same physical memory space.

Abstract: Reducing remote reads of memory in a hybrid computing environment by maintaining remote memory values locally, the hybrid computing environment including a host computer and a plurality of accelerators, the host computer and the accelerators each having local memory shared remotely with the other, including writing to the shared memory of the host computer packets of data representing changes in accelerator memory values, incrementing, in local memory and in remote shared memory on the host computer, a counter value representing the total number of packets written to the host computer, reading by the host computer from the shared memory in the host computer the written data packets, moving the read data to application memory, and incrementing, in both local memory and in remote shared memory on the accelerator, a counter value representing the total number of packets read by the host computer.

Abstract: Shared storage systems and methods are provided. A particular shared storage system is a system including multiple instances of shared storage. Each of the instances of shared storage includes data and file system metadata separated from the data. The file system metadata includes location data specifying storage location information related to the data. A persistent common view is provided of local and remote files, file systems, and services in the shared storage.

Abstract: A system and method determines when the entries of a reply cache, organized into microcaches each of which is allocated to a client connection, may be retired or released, thereby freeing up memory structures. A plurality of connection statistics are defined and tracked for each microcache and for the entries of the microcache. The connection statistics indicate the value of the microcache and its entries to the client. The connection statistics include a measure of the time since the last idempotent or non-idempotent request (TOLR) was received, and a count of the number of idempotent requests that have been received since the last non-idempotent request (RISLR). A microcache with a TOLR time and a RISLR count that exceed respective thresholds may be expired and removed from the reply cache.

Abstract: A computer implemented method provides remote access to a plurality of sessions at a computer. The method includes initiating a master process in a context independent from the sessions, establishing a first slave process in a context of a first session, and maintaining communication between the master process and the first slave process. The master process provides access to the computer's display while the display is under control of the first session, detects a second session, having a respective second slave process, communicates with the second slave process, and provides access to the computer's display while the display is under control of the second user session.

Abstract: Hypervisor page fault processing logic is provided for a shared memory partition data processing system. The logic, responsive to an executing virtual processor of the shared memory partition data processing system encountering a hypervisor page fault, allocates an input/output (I/O) paging request to the virtual processor from an I/O paging request pool and increments an outstanding I/O paging request count for the virtual processor. A determination is then made whether the outstanding I/O paging request count for the virtual processor is at a predefined threshold, and if not, the logic places the virtual processor in a wait state with interrupt wake-up reasons enabled based on the virtual processor's state, otherwise, it places the virtual processor in a wait state with interrupt wake-up reasons disabled.

Abstract: A method and apparatus for managing coherence between two processors of a two processor node of a multi-processor computer system. Generally the present invention relates to a software algorithm that simplifies and significantly speeds the management of cache coherence in a message passing parallel computer, and to hardware apparatus that assists this cache coherence algorithm. The software algorithm uses the opening and closing of put/get windows to coordinate the activated required to achieve cache coherence. The hardware apparatus may be an extension to the hardware address decode, that creates, in the physical memory address space of the node, an area of virtual memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements.

Abstract: A system and method for writing, by a sender, a message into blocks of a memory space, the memory space being shared by the sender of the message and a receiver of the message, and sending, by the sender, an interrupt corresponding to the message.

Abstract: Various embodiments of the present invention provide a system for caching information in a multi-process environment. The system includes a processor. A shared memory is communicatively coupled to the processor. The shared memory includes a set of data. A writer process is communicatively coupled to the shared memory. The write process reads and updates the set of data. A plurality of reader processes is communicatively coupled to the shared memory. Each reader process reads at least part of the set of data directly from the shared memory and sends a set of update information to the writer process. The writer process then updates the set of data stored in the shared memory based on the set of update information.

Abstract: Some embodiments of the invention pertain to a memory system containing multiple memory devices, in which one or multiple ones of the memory devices may flexibly be selected at one time for a common operation to be performed by all the selected devices concurrently.

Abstract: The updating of only some memory locations in a multiple computer environment in which at least one applications program (50) executes simultaneously on a plurality of computers M1, M2 . . . Mn each of which has a local memory, is disclosed. Memory locations (A, B, D, E, X) in said local memory are categorized into two groups. The first group of memory locations (X1, X2, . . . Xn, A1, A2 . . . An) are each accessible by other computers. The second group of memory locations (B, E) are each accessible only by the computer having the local memory including the memory location. Changes to the values of memory locations in the first group only are transmitted to all other computers. A promotion mechanism is disclosed to promote memory locations in the second group into the first group in the event that application program execution means that a memory location in said second group is referred to by a memory location in the first group (ie the first group location now points to the second group location).

Abstract: In a communication system, data is selectively transmitted using single-ended or differential signaling. The data is transmitted in relation to a plurality of clock signals having different relative phases. When the data is transmitted using single-ended signaling, data on adjacent signal lines undergo logic transitions at different times in relation to the plurality of clock signals.

Abstract: The invention proposes a method and a control apparatus for storing a first data block containing data for controlling a technical process in a first memory area of an automation apparatus. In this case, a second data block containing data for controlling the technical process is stored in a second memory area of the automation apparatus. The first data block and the second data block are subdivided into a plurality of data areas. At least one data area which is part of the first data block is supplied to the automation apparatus and stored in the first memory area. Furthermore, at least one data area which is both part of the first data block and art of the second data block is copied from the second memory area into the first memory area. A corresponding automation apparatus is also proposed.

Abstract: The invention provides, in one aspect, a virtual processor that includes one or more virtual processing units. These virtual processing units execute on one or more processors, and each virtual processing unit executes one or more processes or threads (collectively, “threads”). While the threads may be constrained to executing throughout their respective lifetimes on the same virtual processing units, they need not be. An event delivery mechanism associates events with respective threads and notifies those threads when the events occur, regardless of which virtual processing unit and/or processor the threads happen to be executing on at the time. The invention provides, in other aspects, virtual and/or digital data processors with improved dataflow-based synchronization. A process or thread (collectively, again, “thread”) executing within such processor can execute a memory instruction (e.g.

Abstract: To share a memory pool that includes at least one physical memory in at least one of plural computing nodes of a system, firmware in management infrastructure of the system is used to partition the memory pool into memory spaces allocated to corresponding ones of at least some of the computing nodes. The firmware maps portions of the at least one physical memory to the memory spaces, where at least one of the memory spaces includes a physical memory portion from another one of the computing nodes.

Abstract: A system, method, and computer program for caching a plurality of file fragments to improve file transfer performance, comprising the steps of exposing at least one file fragment of a computer file as a primary object to an application; caching said at least one file fragment at a plurality of points in a network system, wherein said at least one file fragment remains unchanged; and managing said at least one non-changing file fragment throughout said network system at a plurality of cache points and appropriate means and computer-readable instructions.

Abstract: A cluster system comprises a plurality of nodes that provides data-access service to a shared storage, each node having at least one failover partner node for taking over services of a node if the node fails. Each node may produce write logs for the shared storage and periodically send write logs at predetermined time intervals to a global device which stores write logs from each node. The global device may detect failure of a node by monitoring time intervals of when write logs are received from each node. Upon detection of a node failure, the global device may provide the write logs of the failed node to one or more partner nodes for performing the write logs on the shared storage. Write logs may be transmitted only between nodes and the global device to reduce data exchanges between nodes and conserving I/O resources of the nodes.

Abstract: Large-scale table data stored in a shared memory are sorted by a plurality of processors in parallel. According to the present invention, the records subjected to processing are first divided for allocation to the plurality of processors. Then, each processor counts the numbers of local occurrences of the field value sequence numbers associated with the records to be processed. The numbers of local occurrences of the field value sequence numbers counted by each processor is then converted into global cumulative numbers, i.e., the cumulative numbers used in common by the plurality of processors. Finally, each processor utilizes the global cumulative numbers as pointers to rearrange the order of the allocated records.

Abstract: A system and method for adjusting pictures minimizes the impact on graphics processing performance of a discrete processor. A hybrid system configuration includes the discrete processor and an integrated processor, where the discrete processor typically consumes more power and provides greater processing performance compared with the integrated processor. A picture is produced by a video or graphics engine of a discrete processor within a hybrid system. Each picture is then transferred to a back buffer in the host processing memory. The picture is analyzed to produce picture analysis results that are used to generate adjustment settings. The back buffer is swapped to become the front buffer and the adjustment settings are applied to the picture by an integrated processor to display an adjusted picture. The adjustment may be used in conjunction with power saving techniques to maintain the image quality when display backlighting is reduced.

Abstract: A data processing system in the form of an integrated circuit includes a general purpose programmable processor and a hardware accelerator. A shared memory management unit provides memory management operations on behalf of both of the processor core and the hardware accelerator. The processor and the hardware accelerator share a memory system. A first communication channel between the processor and the hardware accelerator communicates at least control signals therebetween. A second communication channel coupling the hardware accelerator and the memory system allows the hardware accelerator to perform its own data access operations upon the memory system.

Abstract: Atomic data are stored in blocks on a hard disk. The blocks are grouped into a committed block aggregate P1, which exists only on the hard disk, a next-generation committed block aggregate C1, which is converted into a committed block aggregate at predetermined times, and an atomic block aggregate S3, which is created for every user based on the committed block aggregate C1. User A makes desired data changes to S3. When user A terminates the data processing, the block aggregate storing the data is merged, like from the atomic block aggregate S4 to committed block aggregate C2, and stored on the hard disk as a committed block aggregate P3.

Abstract: An embodiment of a method of cooperative caching for a distributed storage system begins with a step of requesting data from storage devices which hold the data. The method continues with a step of receiving any cached blocks and expected response times for providing non-cached blocks from the storage devices. The method concludes with a step of requesting a sufficient number of the non-cached blocks from one or more particular storage devices which provides an expectation of optimal performance.

Abstract: Mechanisms are disclosed for detecting protocols independently of the ports used by streams associated with the protocols or applications that may send out such streams. The detecting may entail using a content filter that is hosted on a networking stack, where the content filter may be composed of a stream buffer and handlers for detecting the protocols. The handlers may be further used to modify streams incoming to a port or streams outgoing from an application. The handlers can modify the streams in a variety of ways, including reading, inserting, replacing, deleting, and completing data in the streams according to some policy criteria, such as those set by parental controls. Individual handlers may be selected from a plurality or set of handlers so that they can be matched up to the appropriate streams.

Abstract: A device, including a first storage unit configured to store a first plurality of files and a first management data corresponding to the first files; a connector configured to connect to an external storage device, the external storage being configured to store a second plurality of files and second management data corresponding to the second files; a controller configured to generate new management data by merging the first management data and the second management data, and to store the new management data in a memory; and a display unit configured to display contents of the first and second plurality of files based on the new management data without indicating to the user where the respective files are stored.

Abstract: A system, method and computer program product for anti-malware processing of data stream that includes a plurality of logical data streams formed from a primary data stream; and a plurality of stream buffers, each buffering data of a corresponding logical data stream. A plurality of processing handlers each associated with one of the data streams, where the handlers are processing the data of the logical data stream buffered by its stream buffer. Each processing handler is associated with a particular functionality and at least one processing handler scans its logical data stream for malware presence. Each stream buffer has a configurable buffering policy. At least one of the processing handlers decompresses the data into one or more secondary streams. At least one of the processing handlers parses its logical data stream, creating one or more instances of secondary data streams. The scanning can be based on a signature search.

Abstract: According to one embodiment, a memory system includes a memory that includes a plurality of parallel operation elements, each of which stores therein write data from a host device and on each of which read/write is individually performed, a control unit that performs the read/write to the parallel operation elements simultaneously, and a required-performance measuring unit that measures a required performance from the host device are included. The control unit changes the number of simultaneous executions of the read/write of the parallel operation elements based on the required performance measured by the required-performance measuring unit.

Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

Abstract: A distributed computing system includes a plurality of processors and shared memory service entities executable on the processors. Each of the shared memory service entities is associated with a local shared memory buffer. A producer is associated with a particular shared memory service entity, and the producer provides data that is stored in the local shared memory buffer associated with the particular shared memory service entity. The shared memory service entities propagate content of the local shared memory buffers into a global shared memory, wherein propagation of content of the local shared memory buffers to the global shared memory is performed using a procedure that relaxes guarantees of consistency between the global shared memory and the local shared memory buffers.

Abstract: An ascending ordered list without duplication is generated based on a value list divided and held by multiple memory modules. An information processing system has multiple PMMs (Processor Memory Modules), and the PMMs are interconnected via a data transmission path. The memory in the PMM has a list of values, which are ordered in ascending or descending order without duplication. The PMM determines, for a storage value in the value list (LOCAL_LIST) held by the PMM, whether or not the memory module is a representative module representing one or more memory modules holding the storage value based on rankings determined for the individual PMMs and the value lists received from the other PMMs, and if the memory module is determined to be the representative module (RV-0 . . . RV-7), associates to the storage value and stores information indicating that the memory module is the representative module.

Abstract: A data center system includes a memory cache coupled to a data center controller. The memory cache includes volatile memory and stores data that is persisted in a database in a different data center system that is located remotely from the data center system rather than in the first data center system. The data center controller reads data from the memory cache and writes data to the memory cache.

Abstract: An embodiment of the invention provides an apparatus and a method of dynamically controlling the number of busy waiters in for a synchronization object. The apparatus and method perform the steps of increasing a number of allowed busy waiters if there is a waiter in a sleep state and there are no current busy waiters when a requester releases the synchronization object, and decreasing the number of allowed busy waiters if a busy waiter moves from a busy waiting state to the sleep state.

Abstract: In one embodiment, the present invention includes a method for receiving an indication of a pending capacity eviction from a caching agent, determining whether an invalidating writeback transaction from the caching agent is likely for a cache line associated with the pending capacity eviction, and if so moving a snoop filter entry associated with the cache line from a snoop filter to a staging area. Other embodiments are described and claimed.

Abstract: Systems, methods, and computer program products for providing operating system (O/S) redundancy in a computing system are provided. One system includes a host computing device, a plurality of memory devices, and a sub-loader coupled between the host computing device and the plurality of memory devices. Each memory device stores a respective O/S and the sub-loader is configured such that the plurality of memory devices appear transparent to the host computing device. One method includes designating, a first logical unit device as a primary logical unit device and subsequently determining that the first logical unit device is unresponsive. The designation is removed from the first logical unit device and a second logical unit device is designated as a new primary logical unit device. One computer program product includes instructions for performing the above method.

Abstract: A data storage system is provided. The data storage system includes a first storage module for storing a first data, a second storage module for storing a second data, a control module and a processing module. The control module generates a first control signal and a second control signal, and accesses the first data and the second data according to the first control signal and the second control signal. The processing module is coupled to the first storage module, the second storage module and the control module, and controls the first storage module and the second storage module to transmit the first data and the second data to the control module according to the first control signal and the second control signal respectively, wherein the processing module bypasses the second storage module when receiving the first control signal.

Abstract: A portable electronic device includes a system chip, an enabling switch, a signal conversion circuit, a power switching circuit, a storage medium and a synchronous processing module. The enabling switch is triggered to issue an analog signal. The signal conversion circuit converts the analog signal into a digital control signal. The power switching circuit selects one of multiple power sources to be outputted as a voltage signal. The storage medium receives the voltage signal. The synchronous processing module is electrically connected to the system chip, the storage medium, the signal conversion circuit, the power switching circuit and the transmission line. In response to the digital control signal, the storage medium is communicated with an external electronic device through a transmission line, so that the storage medium of the portable electronic device is used as an external storage medium of the external electronic device.

Abstract: A protocol engine (PE) for processing data within a protocol stack in a wireless transmit/receive unit (WTRU) is disclosed. The protocol stack executes decision and control operations. The data processing and re-formatting which was performed in a conventional protocol stack is removed from the protocol stack and performed by the PE. The protocol stack issues a control word for processing data and the PE processes the data based on the control word. Preferably, the WTRU includes a shared memory and a second memory. The shared memory is used as a data block place holder to transfer the data amongst processing entities. For transmit processing, the PE retrieves source data from the second memory and processes the data while moving the data to the shared memory based on the control word. For receive processing, the PE retrieves received data from the shared memory and processes it while moving the data to the second memory.

Abstract: Data store access circuitry is disclosed that comprises: a data store for storing values; comparator circuitry coupled to said data store and responsive to receipt of a data access request comprising an address to compare at least a portion of said address with at least a portion of one or more of said values stored in said data store so as to identify a stored value matching said address; a base value register coupled to said comparator circuitry and storing a base value corresponding to at least a portion of at least one of said stored values; and comparator control circuitry coupled to said comparator circuitry to control: (i) which portion of said address is processed as a non-shared portion and compared by said comparator circuitry with non-shared portions of said one or more stored values stored in said data store; and (ii) which portion of said address is processed as a shared portion and compared by said comparator circuitry with a shared portion of said base value stored in said base value register;

Abstract: A method for interfacing an out-of-order bus and multiple ordered buses and a bus bridge. The bus bridge includes multiple ordered bus interfaces, where each ordered bus interface is coupled to an ordered bus. A flow control logic circuit is coupled to the out-of-order bus and to the multiple ordered bus interfaces. The flow control logic circuit controls a flow of transaction requests between the out-of-order bus and each of the ordered buses interfaces. The flow control logic circuit includes an updating circuit for updating dependency resolution attributes and data readiness attributes associated with transaction requests, and a shared memory unit for storing the dependency resolution attributes, the data readiness attributes and the transaction requests where the transaction requests are destined to the ordered buses.

Abstract: The processor circuit (1) has a Harvard architecture. This processor circuit includes a calculation unit (2), a first memory element (3a) for data storage and a second memory element (4a) for instruction storage. Said first and second memory elements (3a, 4a) are connected by at least one communication bus (5, 6) to the calculation unit. The processor circuit includes management means (8), placed between the first and second memory elements and the calculation unit and capable of saving several data items or instructions to save time during successive data reading.

Abstract: A computer server system and a method for operating the system are described. An address and a status of each computer device of a plurality of computer devices accessible to a switch is written into a memory in the switch. The status of a first computer device which is off line is set to indicate that the first computer device is off line. The status information is read from the memory in the switch by a second computer device so that the second computer device knows that the first computer device is off line. Embodiments are described where the status of a data storage device and the status of a server are written to the memory in the switch.

Abstract: Methods, apparatus, and products are disclosed for paging memory contents between a plurality of compute nodes in a parallel computer that includes: identifying, by a master node, a memory allocation request for an application executing on the master node, the memory allocation request requesting additional computer memory for use by the application during execution; requesting, by the master node from a slave node, an available memory notification specifying to the master node the computer memory available for allocation on the slave node; allocating, by the master node, at least a portion of the computer memory available for allocation on the slave node in dependence upon the memory allocation request and the available memory notification; and transferring, by the master node, contents of a portion of the computer memory on the master node to the allocated portion of the computer memory on the slave node.

Abstract: An object storage system comprises one or more computer processors or threads that can concurrently access a shared memory, the shared memory comprising an array of equally-sized cells. In one embodiment, each cell is of the size used by the processors to represent a pointer, e.g., 64 bits. Using an algorithm performing only one memory write, and using a hardware-provided transactional operation, such as a compare-and-swap instruction, to implement the memory write, concurrent access is safely accommodated in a lock-free manner.

Abstract: A device, including a first storage unit configured to store a first plurality of files and a first management data corresponding to the first files; a connector configured to connect to an external storage device, the external storage being configured to store a second plurality of files and second management data corresponding to the second files; a controller configured to generate new management data by merging the first management data and the second management data, and to store the new management data in a memory; and a display unit configured to display contents of the first and second plurality of files based on the new management data without indicating to the user where the respective files are stored.

Abstract: A computer cluster for providing hosting services includes a plurality of nodes, and a control center coordinating activity of the nodes. Each node includes a plurality of virtual servers such that each virtual server responds to user requests and appears to the user as having its own operating system. Multiple virtual servers running on the same node share the same host operating system and root application software of the node.

Abstract: Client computers are decoupled from file servers in a computer network, by placing a network node, also termed a file switch or file switch computer, between the client computers and the file servers. To the client computers, the file switch appears to be a file server having enormous storage capabilities and high throughput. To the file servers, the file switch appears to be a client as it delegates a single transaction received from a client computer to multiple file servers. The file switch aggregates the file servers' responses to the client computer's request and presents a single response back to the client computer. The file switch performs this transaction aggregation function in a manner that is transparent to both the client computers and the file servers.