Abstract: A memory is provided. The memory includes: a control chip; and a plurality of storage chips, in which the plurality of storage chips are electrically connected with the control chip via a common communication channel, the plurality of storage chips are configured to perform information interaction with the control chip by adopting different clock edges of a first clock signal, the first clock signal has a first clock cycle, the different clock edges include two consecutive rising edges and/or two consecutive falling edges, the plurality of storage chips are further configured to receive a second clock signal and distinguish the different clock edges based on the second clock signal, and a second clock cycle of the second clock signal is greater than the first clock cycle.

Abstract: A wait optimizer circuit can be coupled to a processor to monitor an entry of a virtual CPU (vCPU) into a wait mode to acquire a ticket lock. The wait optimizer can introduce an amount of delay, while the vCPU is in the wait mode, with an assumption that the spinlock may be resolved before sending a wake up signal to the processor for rescheduling. The wait optimizer can also record a time stamp only for a first entry of the vCPU from a plurality of entries into the wait mode within a window of time. The time stamps for vCPUs contending for the same ticket lock can be used by a hypervisor executing on the processor for rescheduling the vCPUs.

Abstract: A data storage system includes a first storage layer, a second storage layer, an I/O manager, and a data organizer. The first storage layer utilizes a first type of data storage device. The first storage layer includes (i) a first data bucket that includes first data having a first data attribute, the first data bucket including a first data limit, and (ii) a second data bucket. The second storage layer utilizes a second type of data storage device. The I/O manager receives a data write request from the user and directs the data write request to the first storage layer. The data organizer (a) determines whether data in the data write request has the first data attribute; and (b) stores the data in the data write request in at least one of the first data bucket and the second data bucket if the data in the data write request has the first data attribute.

Abstract: Disclosed in some examples are methods, systems, memory controllers, devices, and machine-readable mediums which minimize this stall time by returning a memory write acknowledgement once a write command has been selected by the memory controller input multiplexor rather than when the memory write command has been performed. Because the memory controller enforces an ordering to memory once the packet has been selected at an input multiplexor, ordering of prior and subsequent requests to the same address location are preserved and providing the response early allows the processor to continue its operations earlier without any harmful effects.

Abstract: An apparatus for processing data and a method of data processing are provided. A processor core in the apparatus performs data processing operations in response to a sequence of instructions, including write operations which write data items to a non-volatile memory. A write-back cache stores local copies of the data items retrieved from the memory and written to the memory by the processor core. A storage unit is provided which stores indications of the write operations initiated by the processor core and the processor core is configured to respond to an end instruction by causing the local copies of data items which are the subject of the write operations by the processor core, and for which an indication is stored in the storage unit, to be cleaned from the write-back cache to the memory. The indications of the write operations stored in the storage unit are then cleared.

Abstract: A memory interface may include: a transceiver module configured to exchange signals with a plurality of dies; and an input/output (I/O) rate controller configured to calculate per-signal-interval ratios of each of the dies by monitoring signals transmitted to, and received from, each of the dies, select a first die whose operating time is relatively slow and a second die whose operating time is relatively fast, among the plurality of dies, using the calculated per-signal-interval ratios, and provide the transceiver module with information for adjusting data interval ratios for each of the first and second dies.

Abstract: A device can include a plurality of processing sources; a multiplexer (MUX) configured to assign read requests from the processing sources to predetermined time division multiplexer (TDM) command slots. A memory controller can generate nonvolatile memory (NVM) command and address data from read requests received from the MUX during the TDM command slots assigned to the read requests on a unidirectional command-address bus. The address data can include at least a bank address. The device can also receive read data on a unidirectional parallel data bus in synchronism with rising and falling edges of a received data clock. The read data can be received in TDM read slots having a predetermined order. A demultiplexer can provide the read data of each TDM read slot to one of the processing sources based on the TDM read slot position in the predetermined order. Related methods and systems are also disclosed.

Abstract: In a method of controlling on-die termination (ODT) in a memory system including a plurality of memory units that shares a data bus to transfer data, ODT circuits of the plurality of memory units are enabled into an initial state, a resistance value of the ODT circuit is set to a first resistance value, of at least one write non-target memory unit among the plurality of memory units during a write operation on a write target memory unit among the plurality of memory units, and a resistance value of the ODT circuit is set to a second resistance value, of at least one read non-target memory unit among the plurality of memory units during a read operation on a read target memory unit among the plurality of memory units.

Abstract: Systems, apparatuses, and methods related to memory systems and operation are described. A memory system may be communicative coupled to a processor via one or more data buses. Additionally, the memory system may include one or more memory devices that store data to be used by processing circuitry implemented in the processor to perform an operation. Furthermore, the memory system may include a memory controller that receives a memory access request that requests return of the data via the one or more data buses and, in response, determines a storage location of the data in the one or more memory devices based at least in part on the memory access request and instructs the memory system to store the data directly into a processor-side cache integrated with the processing circuitry to enable the processing circuitry implemented in the processor to perform the operation based on the data.

Abstract: A method of controlling read and write access to a memory structure involves initiating a read lock by obtaining a reader pool ID for a thread from a fixed pool of readers, waiting for a writer to finish by entering a wait-loop and querying a scheduler to reschedule the thread if current wait time exceeds a threshold value, declaring a resource to be read, checking for an active write lock and returning the reader pool ID for the thread. Initiating a write-lock involves checking for an active write lock flag and an active read lock flag and entering a wait-loop if the active write lock flag or the active read lock flag is present, and querying a scheduler to reschedule the thread if the wait time exceeds the threshold value.

Abstract: In some examples, a memory module includes an error status indicator, an error address register, and error tracking circuitry. The error tracking circuitry may detect that memory data stored at a memory address for the memory module includes an error. In response, and without overwriting the memory data stored at the memory address, the error tracking circuitry may set the error status indicator and store the memory address in the error address register.

Abstract: The disclosure relates to a processor including an N-bit data bus configured to access a memory; a central processing unit CPU connected to the data bus; a coprocessor coupled to the CPU, including a register file with N-bit registers; an instruction processing unit in the CPU, configured to, in response to a load-scatter machine instruction received by the CPU, read accessing a memory address and delegating to the coprocessor the processing of the corresponding N-bit word presented on the data bus; and a register control unit in the coprocessor, configured by the CPU in response to the load-scatter instruction, to divide the word presented on the data bus into K segments and writing the K segments at the same position in K respective registers, the position and the registers being designated by the load-scatter instruction.

Abstract: A technique to name data is disclosed to allow preservation of storage efficiency over a link between a source and a destination in a replication relationship as well as in storage at the destination. The technique allows the source to send named data to the destination once and refer to it by name multiple times in the future, without having to resend the data. The technique also allows the transmission of data extents to be decoupled from the logical containers that refer to the data extents. Additionally, the technique allows a replication system to accommodate different extent sizes between replication source and destination while preserving storage efficiency.

Abstract: A processing system includes a memory controller coupleable to a RAM, and a ROM configured to store boot information that includes default values for a set of one or more memory timing parameters. At least one processor is configured to, during initialization, configure the memory controller to utilize the default values for the set of one or more memory timing parameters. The at least one processor further is configured to, during operation of the processing system following initialization, receive user input representing one or more updated values for one or more corresponding memory timing parameters of the set, and to dynamically reconfigure the memory controller to utilize one or more updated values for the set of one or more memory timing parameters for the signaling. The processing system further is configured to conduct one or more memory access operations for the RAM using the reconfigured memory controller.

Abstract: Atomic instructions, including a Compare And Swap Register, a Load and AND Register, and a Load and OR Register instruction, use registers instead of storage to communicate and share information in a multi-threaded processor. The registers are accessible to multiple threads of the multi-threaded processor, and the instructions operate on these shared registers. Access to the shared registers is controlled by the instructions via interlocking.

Abstract: Atomic instructions, including a Compare And Swap Register, a Load and AND Register, and a Load and OR Register instruction, use registers instead of storage to communicate and share information in a multi-threaded processor. The registers are accessible to multiple threads of the multi-threaded processor, and the instructions operate on these shared registers. Access to the shared registers is controlled by the instructions via interlocking.

Abstract: A method includes receiving an indication of an operational mode for a memory system including a set of memory devices. A first memory device of the set of memory devices includes a first media having a first media type and a second memory device of the et of memory devices includes a second media having a second media type that is different than the first media type. The method also includes allocating, by a processing device, a first portion and a second portion of the first memory device based on the operational mode for the memory system. The method also includes storing data at the first portion of the first memory device, the second portion of the first memory device, or the second memory device based on the operational mode for the memory system.

Abstract: Systems for distributed data storage. A method embodiment commences upon capturing a history of storage I/O activity over a recent time period. A predictive model is derived from the captured storage I/O activity, and the predictive model is then used for predicting future storage I/O activity. A set of snapshot planning parameters comprising objectives (e.g., to minimize costs or to maximize likelihood completing a snapshot activity by a prescribed time) and/or constraints (e.g., don't wait more than one day to start a snapshot) are applied to the predicted storage I/O characteristics to generate a set of feasible snapshot plans. One of the feasible snapshot plans is selected for scheduling so as to begin the planned snapshot activity at a prescribed time. The snapshot planning parameters are normalized based on the predicted storage I/O characteristics.

Abstract: Provided are a frame processing method and device for use in image processing. The method includes: receiving a first frame by a first processing unit; sending, by the first processing unit and before receiving a second frame processed with a third processing unit, the first frame to a second processing unit, followed by processing the first frame with the second processing unit or processing the first frame with the second processing unit and another processing unit; and receiving a third frame by the first processing unit before the first processing unit receives the first frame processed with the second processing unit or the first frame processed with the second processing unit and the other processing unit. The method precludes frame hysteresis, at a fixed frame rate and with invariable frame processability of each frame.

Abstract: Methods and systems for secure storage protection for memory operations are provided. Aspects include providing a drawer comprising a plurality of clusters, each of the plurality of clusters comprising a plurality of processors, wherein each of the plurality of clusters share a first cache memory, providing a cluster shared cache integrated circuit to manage a second cache memory shared among the plurality of clusters, providing a system memory associated with each of the plurality of clusters, receiving, by a memory controller, a memory operation request from one of the plurality of processors, wherein the memory operation includes a store command, and wherein the memory controller is configured to perform the memory operation and atomically write a secure storage key for the memory operation with the store command of the memory operation.

Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.

Abstract: A microprocessor includes: a first memory bus; a second memory bus; a fetch part configured to fetch an instruction from a first memory connected to the first memory bus; a bus controller configured to control the second memory bus; a determination part configured to determine whether or not an address output from the bus controller is in an area of the first memory; and a first logic circuit part configured to use an output of the determination part to set an access destination of the first memory as the bus controller when the address output from the bus controller is in the area of the first memory.

Abstract: An arrangement for securing a memory device of a computing system in which a memory access command is compared to each command in a list of commands. The command, with specified attributes, is authenticated when the command and its attributes match an entry in the list of commands. Following authentication, the command is evaluated according to usage and behavior metrics in order to identify and prevent unauthorized or malicious access of the memory device. If no violation of usage or behavior metrics is detected, the command may be issued to the memory device for execution.

Abstract: In one aspect, IO recovery mechanisms in active/active replication for storage clusters provide, for each write IO request: determining an extent of pages to be modified; acquiring a lock by a cluster local to the request and locally persisting data; atomically creating an entry in a local journal; and sending, by the local cluster, a data write request to a peer cluster. Upon receiving acknowledgement from the peer cluster of successful transmission, the replication journal entry is cleared, the extent is unlocked, and a notification is returned to the peer. In response to a failure event at the peer cluster after persisting the data at the local cluster and creating the journal entry at the local cluster, an aspect includes sending, to the peer cluster upon recovery of the peer cluster, the journal entry with respect to an extent corresponding to a time of the failure event.

Abstract: Embodiments for implementing a communicating memory between a plurality of computing components are provided. In one embodiment, an apparatus comprises a plurality of memory components residing on a processing chip, the plurality of memory components interconnected between a plurality of processing elements of at least one processing core of the processing chip and at least one external memory component external to the processing chip. The apparatus further comprises a plurality of load agents and a plurality of store agents on the processing chip, each interfacing with the plurality of memory components. Each of the plurality of load agents and the plurality of store agents execute an independent program specifying a destination of data transacted between the plurality of memory components, the at least one external memory component, and the plurality of processing elements.

Abstract: A system and method are presented for the facilitation of threaded download of software record identifiers and software records. Software record identifiers and software records are stored in separate one-dimensional stacks, which stacks feed a plurality of download threads in a first-in, first-out method. Software records and/or software record identifiers may optionally be written in parallel, or in an asynchronous manner. The total number of threads allowed to a user may optionally be limited to a pre-set number. The speed and efficiency of downloading records is increased through use of all of the cores of multi-cored computing systems to substantively concurrently download several threads. The method further allows a failed download thread to restart from the point at which it failed, rather than beginning again from the origin of the thread, thus ensuring that no software records are duplicated, and that no software records are skipped within a download thread.

Abstract: A method of emulating nested page table (NPT) mode-based execute control in a virtualized computing system includes: providing NPT mode-based execute control from a hypervisor to a virtual machine (VM) executing in the virtualized computing system; generating a plurality of shadow NPT hierarchies at the hypervisor based on an NPT mode-based execute policy obtained from the VM; configuring a processor of the virtualized computing system to exit from the VM to the hypervisor in response to an escalation from a user privilege level to a supervisor privilege level caused by guest code of the VM; and exposing a first shadow NPT hierarchy of the plurality of shadow NPT hierarchies to the processor in response to an exit from the VM to the hypervisor due to the escalation from the user privilege level to the supervisor privilege level.

Abstract: A shared cache line is concurrently modified by multiple processors of a computing environment. The concurrent modification is performed based, at least, on receiving one or more architected instructions (Fetch due to Non-Coherent Store instructions) that permit multiple processors to concurrently update the shared cache line absent obtaining a lock or having exclusive ownership of the data.

Abstract: A transactional memory system determines whether a hardware transaction can be salvaged. A processor of the transactional memory system begins execution of a transaction in a transactional memory environment. Based on detection that an amount of available resource for transactional execution is below a predetermined threshold level, the processor determines whether the transaction can be salvaged. Based on determining that the transaction can not be salvaged, the processor aborts the transaction. Based on determining the transaction can be salvaged, the processor performs a salvage operation, wherein the salvage operation comprises one or more of: determining that the transaction can be brought to a stable state without exceeding the amount of available resource for transactional execution, and bringing the transaction to a stable state; and determining that a resource can be made available, and making the resource available.

Abstract: When a radio bearer for sending packets to a UE is split between master and secondary network nodes, then based on relative network conditions (such as relative link quality in view of latency targets or other conditions that reflect user-plane loading) between that master and secondary network nodes a redundancy retransmission mode may be selected from among multiple redundancy retransmission modes. Each of these redundancy retransmission modes define a different protocol for retransmitting multiple copies of selected ones of the packets to the UE over the split radio bearer. These multiple copies are then wirelessly retransmitted to the UE over the split radio bearer according to the selected redundancy retransmission mode. In one example there are 4 possible modes and different modes retransmit PDCP PDUs versus RLC PDUs; in one mode the master and secondary network nodes both perform retransmissions of the identical selected packets.

Abstract: A system is provided for allocating memory for data of a program for execution by a computer system with a multi-tier memory that includes LBM and HBM. The system accesses a data structure map that maps data structures of the program to the memory addresses within an address space of the program to which the data structures are initially allocated. The system executes the program to collect statistics relating to memory requests and memory bandwidth utilization of the program. The system determines an extent to which each data structure is used by a high memory utilization portion of the program based on the data structure map and the collected statistics. The system generates a memory allocation plan that favors allocating data structures in HBM based on the extent to which the data structures are used by a high memory utilization portion of the program.

Abstract: A method of operating a host includes defining transaction identifications for each one of multiple transactions in a multi-transaction, thereafter communicating atomic write data related to each transaction to a data storage device using the transaction ID, and storing the atomic write data in the data storage device using the transaction ID and an identifier.

Abstract: Provided herein are methods and systems for improved storage strategies for use of collections of storage resources, such as solid state drives, including in connection with a converged networking and storage node that may be used for virtualization of a collection of physically attached and/or network-connected storage resources.

Abstract: According to one embodiment, a memory controller is configured so that when the memory controller controls a writing/erasing process for a flash memory performed by a first or second master, the memory controller can prohibit, while the first master is performing the writing/erasing process for the flash memory, an interruption of the writing/erasing process in execution, the interruption resulting from access to the flash memory by the second master.

Abstract: Disclosed is a main memory capable of speeding up a hardware accelerator and saving memory space. The main memory according to the present disclosure is at least temporarily implemented by a computer and includes a memory, and an accelerator responsible for performing an operation for hardware acceleration while sharing the storage space of a host processor and the memory.

Abstract: A system and method include receiving, by an object store virtual machine of a virtual object storage system, a user request for updating an element of an object store. The user request includes a first compare and swap value. The system and method also include updating the first compare and swap value from the second user request for obtaining an updated compare and swap value, comparing the updated compare and swap value with a current compare and swap value of the element, and updating the element upon determining that the updated compare and swap value is greater than the current swap and compare value. Updating the element comprises one of creating a new version of the element and overwriting a previous version of the element. The system and method further include replacing the current compare and swap value with the updated compare and swap value.

Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.

Abstract: Techniques are provided herein for processing a query using in-memory cursor duration temporary tables. The techniques involve storing a part of the temporary table in memory of nodes in a database cluster. A part of the temporary table may be stored in disk segments of nodes in the database cluster. Writer threads running on a particular node writes data for the temporary table to the memory of the particular node. Excess data may be written to the disk segment of the particular node. Reader threads running on the particular node reads data for the temporary table from the memory of the particular node and the disk segment of the particular node.

Abstract: Cache logic for generating a cache address from a binary memory address comprising a first binary sequence of a first predefined length and a second binary sequence of a second predefined length, the cache logic comprising: a plurality of substitution units each configured to receive a respective allocation of bits of the first binary sequence and to replace its allocated bits with a corresponding substitute bit string selected in dependence on the received allocation of bits; a mapping unit configured to combine the substitute bit strings output by the substitution units so as to form one or more binary strings of the second predefined length; and combination logic arranged to combine the one or more binary strings with the second binary sequence by a reversible operation so as to form a binary output string for use as at least part of a cache address in a cache memory.

Abstract: A method includes determining, by a processor, whether a program check condition exists. The method further includes determining, by the processor, whether a lock descriptor of a lock in a file lock table satisfies an unlocking condition. The method further includes releasing, by the processor, the lock by setting the lock descriptor's host identifier as zero. The method further includes determining, by the processor, whether any lock in the file lock table satisfies a lock conflict condition. The method further includes determining, by the processor, whether the file lock table includes any lock descriptor that satisfies a locking condition. The method further includes creating, by the processor, a new lock using the lock descriptor that satisfies the locking condition.

Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.

Abstract: Systems and methods are disclosed for backing up data in a computing system including a controller configured to backup a file in the non-volatile memory at least in part by receiving the file from a host, the file including a plurality of chunks of data and storing the plurality of chunks of data in a browsable partition of the non-volatile memory in response to said receiving the file. The controller further determines that one or more of the plurality of chunks has been modified, determine a new chunk associated with each of the one or more modified chunks, store the one or more new chunks in the browsable partition of the non-volatile memory using the communication interface in response to said determination of the one or more new chunks and store the one or more modified chunks in a container partition of the non-volatile memory using the communication interface.

Abstract: A system includes a processor configured to route a telematics message to all networks not pre-identified as backbone networks in response to a directionality bit, included in a CAN identifier, indicating non-backbone routing. The processor is also configured to route the telematics message to any pre-identified backbone networks in response to the directionality bit indicating backbone routing.

Abstract: A method, system, and computer program product is disclosed for interacting with a client supported by a client-side cache. Embodiments of a method, a system, and a computer program product are disclosed that retrieve a first snapshot, indicating a state of the database after a last database request by the client, associated with the client, determine any number of invalid cached results for the client based on the first snapshot, and transmit the any number of invalid cached results and a second snapshot, an update for the first snapshot.

Abstract: Methods and systems are disclosed for asymmetric memory access to memory banks within integrated circuit (IC) systems. Disclosed embodiments include a memory and a memory controller within an integrated circuit. The memory includes a number of different memory banks, and the memory controller includes a number of different access ports coupled to the memory banks. The memory controller is also configured to provide asymmetric memory access for access requests to memory banks based upon access ports used for memory access requests. Additional disclosed embodiments further use asymmetric access times or asymmetric access bandwidths to provide this asymmetric access to memory banks within system memories for integrated circuit (IC) systems. By providing asymmetric access times or bandwidths for multiple access ports within a memory controller to multiple different memory banks within a system memory, overall access latency or system cost is reduced for the IC systems.

Abstract: A method of managing a memory system is described, the memory system having a processor with a client interface, a buffer memory, and a storage memory. A LUN (logical unit) is exposed to the client, the LUN having a memory size, and QoS specification. When the processor receives a command from the client to write data to the LUN, determining if the QoS specification includes deduplication and: if the QoS does not include deduplication, processing the command by storing the data in the storage memory and creating metadata uniquely referencing a storage location of the data that is written; or if the QoS includes deduplication, determine if deduplication is possible while meeting a latency value as specified in the QoS specification and performing deduplication.

Abstract: A computer-implemented method for encoding an application memory that a program, executed on a computer, has access to, using a shadow memory corresponding to the application memory, the method comprises: creating and initializing a shadow memory divided into segments, each segment in the application memory being mapped to a corresponding segment in the shadow memory, for each memory block in the application memory that the program allocates, encoding a corresponding shadow memory block, in the shadow memory, by: defining a meta segment preceding the first segment of the memory block in the application memory, and a corresponding shadow meta segment in the shadow memory block, writing in the shadow meta segment a first value indicative of the size of the memory block, writing, in each subsequent segment of the shadow memory block, a second value indicative of the offset between the segment and the first segment of the shadow memory block.

Abstract: A computer coupled to an external apparatus via an I/O device comprising, a control unit configured to assign a command identifier to a command issued to the external apparatus, wherein the I/O device includes a collision detection unit defined a partial command identifier space which is a subspace of a command identifier space that is a set of a plurality of command identifiers, and wherein the collision detection unit is configured to: shift an arrangement of the partial command identifier space within the command identifier space; and determine whether or not the assigned command identifier collides with another command identifier that is in use.

Abstract: A method and apparatus are provided for controlling multiple processors in order to reduce current consumption in electronic device. An electronic device includes an application processor (AP) configured to control a plurality of functions; a communication processor (CP) electronically connected to the AP; and a sensor module or a communication module electronically connected to the CP. When the AP enters a sleep state, the CP is configured to control at least one function among the plurality of functions based on information collected from the sensor module or the communication module according to a discontinuous reception (DRX) operating period.

Abstract: In one embodiment, a method includes intercepting a write command to write to a volume at a production site, saving data from the write command to a cache, sending metadata from the write command to a data protection appliance (DPA), writing the data to the volume, receiving a request for the data in the cache, sending the data from cache to a data protection appliance (DPA) at the production site and sending the data from the DPA to the replication site.