Abstract: Technology for configuring a software job is described. An aspect of the technology involves receiving a software job including a plurality of events, each event including a request for processing, assigning the events to respective executors by matching the events with executor profiles, so that for each event the assigned executor is designated to perform the processing for the event, and selecting automatically an alternative executor to perform the processing for an event when the executor originally designated to perform the processing does not complete the processing.

Abstract: Disclosed herein are systems, methods, and software for enhancing error detection in data synchronization operations. In an implementation, log data reported by a device is received and incorporated into an event database indicating interleaved events related to data synchronization threads on the device. The event database is queried to extract a listing of events in the event database, the listing of events comprising events potentially associated with at least one error condition in the data synchronization threads. The listing of events is processed to identify one or more patterns from among the interleaved events that indicate the at least one error condition in the data synchronization threads. Responsive to identifying the one or more patterns, an indication of the at least one error condition in the data synchronization threads is communicated.

Abstract: A method for performing cache flushing operations in a data storage system can include maintaining a plurality of SSDs as a cache medium for a data storage medium, controlling a region of the SSDs in a write-back cache mode, and monitoring a status of the SSDs to detect a low-performance condition. In the write-back cache mode, data is mirrored across the SSDs. The method can also include performing normal purge operations on the data stored in the region under a condition that the low-performance condition is not detected, and performing aggressive purge operations on the data stored in the region in response to detecting the low-performance condition. The normal purge operations can include flushing the data stored in the region to the data storage medium. The aggressive purge operations can include sequentially mirroring the data stored in the region to one or more special territories of the data storage medium.

Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.

Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.

Abstract: Threads using hardware transactions and executing instrumented critical sections that do not perform any writes may complete as long as the thread holding the lock has not yet executed its first write operation. If the thread executing the instrumented critical section performs any writes, or if the thread holding the lock performs any writes during its critical section, the hardware transaction may be aborted. A write flag may be used to determine whether the thread holding the lock performs any writes. The thread holding the lock may set the flag before performing any write operation. The thread executing the hardware transaction may subscribe to that flag and abort the transaction if the flag is set to true, indicating that the thread holding the lock performed a write operation.

Abstract: A system and method are presented for the facilitation of threaded download of software record identifiers and software records. Software record identifiers and software records are stored in separate one-dimensional stacks, which stacks feed a plurality of download threads in a first-in, first-out method. Software records and/or software record identifiers may optionally be written in parallel, or in an asynchronous manner. The total number of threads allowed to a user may optionally be limited to a pre-set number. The speed and efficiency of downloading records is increased through use of all of the cores of multi-cored computing systems to substantively concurrently download several threads. The method further allows a failed download thread to restart from the point at which it failed, rather than beginning again from the origin of the thread, thus ensuring that no software records are duplicated, and that no software records are skipped within a download thread.

Abstract: A kernel receives a request to execute a first process instance from an agent. The first process instance is an instance of a first program. The kernel obtains one or more access control rules related to the agent. The kernel permits execution of the first process instances based on the access control rules. The kernel detects the first process instance attempting to access a second process instance during execution of the first process instance. The second process instance is an instance of a second program currently being executed. The kernel determines whether to grant the first process instance permission to access the second process instances based on the access control rules.

Abstract: A kernel receives a request to execute a first process instance from an agent. The first process instance is an instance of a first program. The kernel obtains one or more access control rules related to the agent. The kernel permits execution of the first process instances based on the access control rules. The kernel detects the first process instance attempting to access a second process instance during execution of the first process instance. The second process instance is an instance of a second program currently being executed. The kernel determines whether to grant the first process instance permission to access the second process instances based on the access control rules.

Abstract: An electronic device includes a memory protection unit configured to protect an access to a register of a device arranged in an address space. An operating system sets an access right to the register by using the memory protection unit. A process requests the operating system to operate the device when the process operates the device, and the operating system makes an access to the corresponding register in accordance with the request for the operation to operate the device.

Abstract: In an approach for managing data transfer across a bus shared by processors, a request for a first set of data is received from a first processor. A request for a second set of data is received from a second processor. First portions of the first set of data and the second set of data are written to a buffer. Additional portions of each set of data are written to the buffer as portions are received. It is determined that a portion of the first set of data has a higher priority to the bus than a portion of the second set of data based on a priority scheme, wherein the priority scheme is based on return progress of each respective set of data having at least a portion of data in the buffer. The portion of the first set of data is granted access to the bus.

Abstract: Various aspects provide for detecting ordering violations in a memory system. A system includes a prediction component and an execution component. The prediction component predicts whether a load instruction in the system is associated with an instruction pipeline hazard. The execution component allocates the load instruction to a queue buffer in the system in response to a prediction that the load instruction is not associated with the instruction pipeline hazard.

Abstract: A storage system includes a memory controller connected to a solid state memory device and a read status table that tracks a pending read from the solid state memory device and a physical address of the solid state memory device that is associated with the pending read. The memory controller releases the physical address for reassignment when the read status table indicates that no pending reads are associated with the physical address. In certain embodiments, the read status table may be included within the memory controller. In certain embodiments, subsequent to the release of the physical address, erase operations may erase data at the physical address and the physical address may be reassigned to a new logical address by ensuing host write operations.

Abstract: A Lock register can be associated with a mailbox. The Lock register can store a claim ID of a process that has allocated the mailbox. The Lock register can include a Lock port and a Lock Clear port, used to claim and release the Lock register. The Lock register only permits data to be written to the Lock Register when the Lock register is not currently allocated, and the Lock Clear port only permits the process that has allocated the Lock register to write a value.

Abstract: A method of managing a memory system is described, the memory system having a processor with a client interface, a buffer memory, and a storage memory. A LUN (logical unit) is exposed to the client, the LUN having a memory size, and QoS specification. When the processor receives a command from the client to write data to the LUN, determining if the QoS specification includes deduplication and: if the QoS does not include deduplication, processing the command by storing the data in the storage memory and creating metadata uniquely referencing a storage location of the data that is written; or if the QoS includes deduplication, determine if deduplication is possible while meeting a latency value as specified in the QoS specification and performing deduplication.

Abstract: Preventing request conflicts within microprocessors and/or computer systems. More particularly, embodiments of the invention relate to a technique to manage request conflicts within a processor and/or computer system in which a number of accesses may be made to a particular cache or group of caches shared amongst a set of cores or processors or agents.

Abstract: A unique file-system node identification (ID) is created for each newly created node in a file system repository by combining a grid identification (ID), a repository identification (ID), and a node identification (ID) to form the unique file-system node ID. The unique file-system node ID is associated with a unique association identification (ID) thereby linking the node from a source repository to a target repository to form an association when performing a replication operation between the source repository and the target repository. Upon removing the association, the unique association ID is unlinked from a replication policy in a source repository, where an initiated replication operation is disabled.

Abstract: In an approach to adaptively pipeline a MapReduce job, a processor receives one or more data records from a storage and inserts the one or more data records into a map queue, wherein a size of the map queue is adaptive to one or more utilizations of one or more resources in the processor. One or more processors apply a map function to the one or more data records in the first buffer and sort the records that are output from the map function and store the sorted records. One or more processors receive and insert the sorted records into a reduce queue, wherein a size of the reduce queue is adaptive to one or more utilizations of resources in the one or more processors. One or more processors apply a reduce function to the sorted records in the reduce queue and store a result in a storage.

Abstract: Disclosed is a system and method for updating IOMMU (Input Output Memory Management Unit) tables for remapping DMA (Direct Memory Access) range for a requested bus device when the device is active.

Abstract: Various embodiments for storage initialization and data destage in a computing storage environment are provided. At least a portion of data on a storage device is initialized using a background process, while one of simultaneously and subsequently destaging the at least the portion of the data to the storage device using a foreground process is performed. A persistent metadata bitmap, adapted to indicate whether the at least the portion of the data has been initialized, is staged to cache, the cache operable in the computing storage environment. The background process maintains a volatile bitmap indicating a status of the initialization of the at least the portion of the data in direct correspondence to the metadata bitmap. As the background process initializes the at least the portion of the data, an applicable bit on the persistent metadata bitmap is cleared and a corresponding bit is set on the volatile bitmap.

Abstract: Access to a shareable resource between threads is controlled by a lock having shared, optimistic and exclusive modes and maintaining a list of threads requesting ownership of said lock. A shared optimistic mode is provided. A lock state descriptor is provided for each desired change of mode comprising a current mode in which a thread has already acquired the lock. When a thread acquires the lock in shared optimistic mode, other threads are allowed to acquire the lock in shared or optimistic mode. When a thread which acquired the lock in shared optimistic mode wants to acquire the lock in exclusive mode, other threads which have acquired the lock in shared or optimistic mode are prevented from acquiring the lock in exclusive mode until the thread which acquired the lock in shared optimistic mode and requested to acquire the lock in exclusive mode releases the lock.

Abstract: Various mechanisms and approaches identify multiple cells in an electronic design and multiple sets of stall prevention requirements or multiple sets of transactions for the multiple cells and determine dependencies between stall prevention requirements. A graph is constructed to represent the dependencies and the stall prevention requirements or the transactions involved in the dependencies by using the stall prevention requirements or the transactions as the nodes and the dependencies as the arcs connecting the nodes in the graph. One or more loop analyses are performed on the graph to identify one or more loops as one or more potential deadlocks. False deadlocks may be eliminated from further processing. The analyses and deadlock detection may be independently performed for each cell in sequence or in parallel to divide and conquer a complex electronic system design.

Abstract: Aspects of the present invention provide high-performance indexing for data-intensive systems in which “slicing” is used to organize indexing data on an SSD such that related entries are located together. Slicing enables combining multiple reads into a single “slice read” of related items, offering high read performance. Small in-memory indexes, such as hash tables, bloom filters or LSH tables, may be used as buffers for insert operations to resolve slow random writes on the SSD. When full, these buffers are written to the SSD. The internal architecture of the SSD may also be leveraged to achieve higher performance via parallelism. Such parallelism may occur at the channel-level, the package-level, the die-level and/or the plane-level. Consequently, memory and compute resources are freed for use by higher layer applications, and better performance may be achieved.

Abstract: An information processing device includes a plurality of processors including an Acquire side processor and a Release side processor, and a shared memory. The Acquire side processor and the Release side processor includes a cache, a memory access control unit in the Release side processor configured to issue a StoreFence instruction for requesting a guarantee of completing the cache invalidation by the Acquire side processor, a memory access control unit in the Acquire side processor configured to issue a LoadFence instruction in response to the StoreFence instruction for guaranteeing completion of the cache invalidation in accordance with the invalidation request from the shared memory after completing a process for the cache invalidation, and an invalidation request control unit configured to perform a process for invalidating the cache in accordance with the invalidation request from the shared memory.

Abstract: The circuit monitors operation of an optoelectronic transceiver that includes a laser transmitter and a photodiode receiver. The circuit includes analog to digital conversion circuitry configured to convert a first analog signal corresponding to a first operating condition of said optoelectronic transceiver into a first digital value, and convert a second analog signal corresponding to a second operating condition of said optoelectronic transceiver into a second digital value corresponding to a second operating condition. The circuit also includes a memory configured to store the first digital value in a first memory location that is mapped to a predefined and unique first address and to store the second digital value in a second memory location that is mapped to a predefined and unique second address.

Abstract: A vector processor includes a plurality of execution units arranged in parallel, a register file, and a plurality of load units. The register file includes a plurality of registers coupled to the execution units. Each of the load units is configured to load, in a single transaction, a plurality of the registers with data retrieved from memory. The loaded registers corresponding to different execution units. Each of the load units is configured to distribute the data to the registers in accordance with an instruction selectable distribution. The instruction selectable distribution specifies one of plurality of distributions. Each of the distributions specifies a data sequence that differs from the sequence in which the data is stored in memory.

Abstract: Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and an address control circuit. The local buffer circuit may be associated with the memory bank. The address control circuit may be coupled to the memory bank and configured to receive a command and an address associated with the command. The address control circuit may include a global buffer circuit configured to store the address. The address control circuit may further be configured to delay the command using one of a plurality of command paths based, at least in part, on a write latency and to provide the address stored in the global buffer circuit to the local buffer circuit to be stored therein.

Abstract: Method and apparatus for performing volume replication using a unified architecture are provided. Each volume has an exclusive volume log table (VLT) and an exclusive volume block update table (VBUT). The VLT is mainly used for recording the relationship between two volumes of a mirroring pair, and the VBUT is used for tracking the state of each data block of the volume itself. By means of the cross operations and applications between the VLT and the VBUT, various volume replication processes such as volume copying and volume mirroring can be enabled under a unified architecture. For each volume, different replication relationships with other volumes can be handled merely by administering its two exclusive tables. The method and the apparatus provided by the present invention can simplify the architecture for synchronization replication and reduce the burdens of administrating tables, thereby making the operation of a storage system more efficient.

Abstract: A method includes identifying a first value of a lock word corresponding to a data structure, by a process in a plurality of processes that each have access to the data structure. The method also includes copying the data structure to a corresponding shadow record. The method additionally includes modifying the shadow record with a desired update for the data structure, and atomically updating the data structure and the lock word, by the process, using a hardware built-in function. The updating includes identifying a second value of the lock word and determining whether the first value of the lock word and the second value of the lock word are equivalent. The method additionally includes, in response to determining that the first value of the lock word and the second value of the lock word are equivalent, replacing the data structure with the shadow record and incrementing the lock word.

Abstract: Access to a shareable resource between threads is controlled by a lock having shared, optimistic and exclusive modes and maintaining a list of threads requesting ownership of said lock. A shared optimistic mode is provided. A lock state descriptor is provided for each desired change of mode comprising a current mode in which a thread has already acquired the lock. When a thread acquires the lock in shared optimistic mode, other threads are allowed to acquire the lock in shared or optimistic mode. When a thread which acquired the lock in shared optimistic mode wants to acquire the lock in exclusive mode, other threads which have acquired the lock in shared or optimistic mode are prevented from acquiring the lock in exclusive mode until the thread which acquired the lock in shared optimistic mode and requested to acquire the lock in exclusive mode releases the lock.

Abstract: A compact optical transceiver is provided by using a serial communication bus as a communication bus connecting a logic device and a microcomputer. This optical transceiver is connected through an MDIO bus to an external upper layer and is provided with a microcomputer, a logic device, the MDIO bus, a serial communication bus, and a first dedicated signal line. The microcomputer has an MDIO register. The logic device receives a command code, address information, and a single data block from the upper layer through the MDIO bus, transmits the address information and the single data block to the microcomputer through the serial communication bus, and transmits the OP code to the microcomputer through the first dedicated signal line.

Abstract: A transactional memory system salvages a hardware lock elision (HLE) transaction. A processor of the transactional memory system executes a lock-acquire instruction in an HLE environment and records information about a lock elided to begin HLE transactional execution of a code region. The processor detects a pending point of failure in the code region during the HLE transactional execution. The processor stops HLE transactional execution at the point of failure in the code region. The processor acquires the lock using the information, and based on acquiring the lock, commits the speculative state of the stopped HLE transactional execution. The processor starts non-transactional execution at the point of failure in the code region.

Abstract: The present invention provides a computer system including a CPU and a memory subsystem connected via a system bus to communicate with each other. The computer system 100 includes a bus monitor 50 connected to the system bus 10 to monitor the frequency of access requests from the CPU 20 to the memory subsystem 30, and a latency changing means 60 for sending a control signal to the memory subsystem to change the latency of the access requests in response to the frequency of the access requests received from the bus monitor.

Abstract: A transactional memory system salvages a hardware lock elision (HLE) transaction. A processor of the transactional memory system executes a lock-acquire instruction in an HLE environment and records information about a lock elided to begin HLE transactional execution of a code region. The processor detects a pending point of failure in the code region during the HLE transactional execution. The processor stops HLE transactional execution at the point of failure in the code region. The processor acquires the lock using the information, and based on acquiring the lock, commits the speculative state of the stopped HLE transactional execution. The processor starts non-transactional execution at the point of failure in the code region.

Abstract: A transactional memory system salvages a hardware transaction. A processor of the transactional memory system records information about an about-to-fail handler for transactional execution of a code region, and records information about a lock elided to begin transactional execution of the code region. The processor detects a pending point of failure in the code region during the transactional execution, and based on the detecting, stops transactional execution at a first instruction in the code region and executes the about-to-fail handler using the information about the about-to-fail handler. The processor, executing the about-to-fail handler, acquires the lock using the information about the lock, commits speculative state of the stopped transactional execution, and starts non-transactional execution at a second instruction following the first instruction in the code region.

Abstract: Subject matter disclosed herein relates to read and write processes of a memory device.

Abstract: A transactional memory system salvages a hardware transaction. A processor of the transactional memory system records information about an about-to-fail handler for transactional execution of a code region, and records information about a lock elided to begin transactional execution of the code region. The processor detects a pending point of failure in the code region during the transactional execution, and based on the detecting, stops transactional execution at a first instruction in the code region and executes the about-to-fail handler using the information about the about-to-fail handler. The processor, executing the about-to-fail handler, acquires the lock using the information about the lock, commits speculative state of the stopped transactional execution, and starts non-transactional execution at a second instruction following the first instruction in the code region.

Abstract: In a processor, an instruction sequence including, in order, a load-and-reserve instruction specifying a read access to a target memory block, an instruction delimiting transactional memory access instructions belonging to a memory transaction, and a store-conditional instruction specifying a conditional write access to the target memory block is detected. In response to detecting the instruction sequence, the processor causes the conditional write access to the target memory block to fail.

Abstract: The disclosure provides systems and methods for maintaining cache coherency in a multi-threaded processing environment. For each location in a data cache, a global state is maintained specifying the coherency of the cache location relative to other data caches and/or to a shared memory resource backing the data cache. For each cache location, thread state information associated with a plurality of threads is maintained. The thread state information is specified separately and in addition to the global state, and is used to individually control read and write permissions for each thread for the cache location. The thread state information is also used, for example by a cache controller, to control whether uncommitted transactions of threads relating to the cache location are to be rolled back.

Abstract: A method and system for testing and logging execution events of software delivered to a user. The user can launch and run the software product while having the support and a necessary input from the product developer. A software product is provided from a first remote server and executed on a user computer, while execution statistics are collected and analyzed by a second remote server. The software product is used in a virtual execution environment. The software product is executed on a Guest Operating System (GOS) also installed on the user computer. A hypervisor-level monitoring of tested software products and GOSs is implemented.

Abstract: A server device includes a processor; and a memory communicatively coupled to the processor. The memory includes executable code that causes the processor, upon execution of the executable code, to: maintain a database comprising a virtual object; maintain a database of users that subscribe to the virtual object; and in response to receiving a request from a non-subscriber user to perform a first action on the virtual object, send a message to at least one of the users that subscribe to the virtual object.

Abstract: Technologies for detecting unauthorized memory accesses include a computing device having transactional memory support. The computing device executes a code segment identified as suspicious and detects a transactional abort during execution of the code segment. The computing device may execute a security support thread concurrently with the code segment that reads one or more monitored memory locations. A transactional abort may be caused by a read of the security support thread conflicting with a write from the code segment. The computing device may set a breakpoint within the code segment, and a transactional abort may be caused by execution of the code segment reaching the breakpoint. An abort handler determines whether a security event has occurred and reports the security event. The abort handler may determine whether the security event has occurred based on the cause of the transactional abort. Other embodiments are described and claimed.

Abstract: Embodiments relate to intra-instructional transaction abort handling. An aspect includes using an emulation routine to execute an instruction within a transaction. The instruction includes at least one unit of operation. The transaction effectively delays committing stores to memory until the transaction has completed successfully. After receiving an abort indication, emulation of the instruction is terminated prior to completing the execution of the instruction. The instruction is terminated after the emulation routine completes any previously initiated unit of operation of the instruction.

Abstract: Embodiments relate to intra-instructional transaction abort handling. An aspect includes using an emulation routine to execute an instruction within a transaction. The instruction includes at least one unit of operation. The transaction effectively delays committing stores to memory until the transaction has completed successfully. After receiving an abort indication, emulation of the instruction is terminated prior to completing the execution of the instruction. The instruction is terminated after the emulation routine completes any previously initiated unit of operation of the instruction.

Abstract: Under control of the consumer, it is determined that a first buffer is empty and that a second buffer contains data; a first compare-double-and-swap operation within a spin loop is executed to swap a double pointer of the first buffer and a double pointer of the second buffer, wherein responsive to the executing of the operation the consumer drains the second buffer, and wherein the executing of the operation directs the at least one producer to fill the first buffer; and it is determined that the first buffer and the second buffer are empty and the consumer waits for a notification from one of i) the at least one producer and ii) a timer. Under control of the at least one producer, a second compare-double-and-swap operation within a spin loop is executed to atomically locate the first buffer and update the double pointer of the first buffer.

Abstract: A system for parallel processing tasks by allocating the use of exclusive locks to process critical sections of a task. The system includes storing update information that is updated in response to acquisition and release of an exclusive lock. When processing a task which includes a critical section containing code affecting execution of the other task, an exclusive execution unit acquires an exclusive lock prior to processing the critical section. When the section has been processed successfully, the lock is released and update information updated. Meanwhile a second task, whose critical section does not contain code affecting execution of the other task may run in parallel, without acquiring an exclusive lock, via a nonexclusive execution unit. The nonexclusive execution unit determines that the second critical section has successfully completed if the update information has not changed during processing of the second critical section.

Abstract: Under control of the consumer, it is determined that a first buffer is empty and that a second buffer contains data; a first compare-double-and-swap operation within a spin loop is executed to swap a double pointer of the first buffer and a double pointer of the second buffer, wherein responsive to the executing of the operation the consumer drains the second buffer, and wherein the executing of the operation directs the at least one producer to fill the first buffer; and it is determined that the first buffer and the second buffer are empty and the consumer waits for a notification from one of i) the at least one producer and ii) a timer. Under control of the at least one producer, a second compare-double-and-swap operation within a spin loop is executed to atomically locate the first buffer and update the double pointer of the first buffer.

Abstract: According to one embodiment, a semiconductor memory device includes a memory and a controller. The controller controls the memory, communicates with a host device via a first signal line and a second signal line, and receives data items to be written in the memory from the host device on the first and second signal lines in a first period. The same group number is assigned to two data items which flow in parallel on the first and second signal lines. The controller transmits to the host device a response packet including an indication of a group number assigned to an unsuccessfully received one of the data items.

Abstract: Disclosed is a scratch pad memory management device and a method thereof. The scratch pad memory management device divides a scratch pad memory into a plurality of unit blocks, maintains a memory allocation table corresponding to indices of the plurality of unit blocks in a main memory, and manages the scratch pad memory.

Abstract: The use of X's in RTL design is widely common for improving synthesis results and, in some cases, verification effectiveness. However, it has certain implications on verification completeness. Human design error or flawed synthesis may lead to undesirable non-determinism on design outputs, not always detected consistently by simulators. This disclosure presents a framework for formalizing observable behavior on digital design output, and a proof methodology for detecting non-determinism or proving correctness with respect to observable X, using a model checker.