Abstract: Embodiments include methods, apparatus, and systems for data transfer in storage systems. One embodiment includes a method that transmits a state of cached write data and mapping metadata associated with a disk group from a first array to a second array and then transfers access to the disk group from the first array to the second array while host applications continue to access data in the disk group.

Abstract: Techniques for utilizing processor cores include sequestering processor cores for use independently from an operating system. In at least one embodiment of the invention, a method includes executing an operating system on a first subset of cores including one or more cores of a plurality of cores of a computer system. The operating system executes as a guest under control of a virtual machine monitor. The method includes executing work for an application on a second subset of cores including one or more cores of the plurality of cores. The first and second subsets of cores are mutually exclusive and the second subset of cores is not visible to the operating system. In at least one embodiment, the method includes sequestering the second subset of cores from the operating system.

Abstract: Systems, mediums, and methods are provided for scheduling input/output requests to a storage system. The input output requests may be received, categorized based on their priority, and scheduled for retrieval from the storage system. Lower priority requests may be divided into smaller sub-requests, and the sub-requests may be scheduled for retrieval only when there are no pending higher priority requests, and/or when higher priority requests are not predicted to arrive for a certain period of time. By servicing the small sub-requests rather than the entire lower priority request, the retrieval of the lower priority request may be paused in the event that a high priority request arrives while the lower priority request is being serviced.

Abstract: A memory includes a plurality of areas corresponding to a plurality of segments of a storage device. An operation unit stores each of generated access instructions in an area corresponding to a segment of an access destination of the access instruction among the plurality of areas. The operation unit loads data of a segment corresponding to at least one area selected from the plurality of areas from the storage device to another area which is different from the plurality of areas on the memory, and executes an access instruction stored in the selected area, for the loaded segment data.

Abstract: Computer readable media, methods and apparatuses are disclosed that may be configured for sequentially reading data of a file stored on a storage medium. The disclosure also provides for alternating writing, in a sequential order, portions of the file data to a first buffer and a second buffer. The disclosure also provides for writing from a first buffer and a second buffer to a first track until the first track is filled.

Abstract: A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.

Abstract: A hardware data prefetcher includes a queue of indexed storage elements into which are queued strides associated with a stream of temporally adjacent load requests. Each stride is a difference between cache line offsets of memory addresses of respective adjacent load requests. Hardware logic calculates a current stride between a current load request and a newest previous load request. The hardware logic compares the current stride and a stride M in the queue and compares the newest of the queued strides with a queued stride M+1, which is older than and adjacent to stride M. When the comparisons match, the hardware logic prefetches a cache line whose offset is the sum of the offset of the current load request and a stride M?1. Stride M?1 is newer than and adjacent to stride M in the queue.

Abstract: A method of storage access scheduling for a memory device for a workload of different priority access requests including access requests having a real-time priority. The method includes characterizing the memory device including determining a balanced number (N) of concurrent access requests associated with a concurrent access maximum throughput associated with the memory device. The method also includes characterizing the workload. The method also includes receiving a real-time access request associated with an access request storage location value. The method also includes processing the real-time access request, utilizing a processor, based on the access request storage location value and the values obtained from characterizing the memory device and the workload.

Abstract: Embodiments provide a device and method for processing messages according to a priority order and for reducing a message processing time when a response event occurs, in a PLC communication module.

Abstract: A method for controlling memory refresh operations in dynamic random access memories. The method includes determining a count of deferred memory refresh operations for a first memory rank. Responsive to the count approaching a high priority threshold, issuing an early high priority refresh notification for the first memory rank, which indicates the pre-determined time for performing a high priority memory refresh operation at the first memory rank. Responsive to the early high priority refresh notification, the behavior of a read reorder queue is dynamically modified to give priority scheduling to at least one read command targeting the first memory rank, and one or more of the at least one read command is executed on the first memory rank according to the priority scheduling. Priority scheduling removes these commands from the re-order queue before the refresh operation is initiated at the first memory rank.

Abstract: An integrated circuit (IC) may include a cache memory, and a cache memory controller coupled to the cache memory. The cache memory controller may be configured to receive a cache miss associated with a memory location, issue pre-fetch requests, each pre-fetch request having a quality of service (QoS), and determine if a pre-fetch request has issued for the memory location associated with the cache miss.

Abstract: A multi-chip memory device and a method of controlling the same are provided. The multi-chip memory device includes a first memory chip; and a second memory chip sharing an input/output signal line with the first memory chip, wherein each of the first memory chip and the second memory chip determines whether to execute a command unaccompanied by an address, by referring to a history of commands.

Abstract: In one embodiment, the present invention is directed to a system with multiple computing hosts each having a hypervisor to provide a virtual environment for the host and one or more containers each including a database instance and at least one database. These databases, and the database instance can be provided as a service to a user of a multi-tenant environment.

Abstract: Methods and apparatus to improve throughput and efficiency in memory devices are described. In one embodiment, a memory controller may include scheduler logic to issue read or write requests to a memory device in an optimal fashion, e.g., to maximize bandwidth and/or reduce latency. Other embodiments are also disclosed and claimed.

Abstract: According to one embodiment, according to one embodiment, a memory system includes a first memory, a second memory, an interface, a managing unit, and a control unit. The second memory stores data read out from the first memory. The interface receives a read command. The managing unit manages a corresponding relationship of a first address included in the read command and a second address. The second address is an address indicating a position in the first memory where data designated by the first address is stored. The control unit acquires a plurality of second addresses corresponding to a sequential first address range including the first address in a case where the read command is received, and determine an amount of data to be read out from the first memory to the second memory based on whether the plurality of second addresses is sequential or not.

Abstract: Provided are a computer program product, system, and method for assigning device adaptors and background tasks to use to copy source extents to target extents in a copy relationship. A relation is provided of a plurality of source extents in source ranks to copy to a plurality of target extents in target ranks in the storage system. One target rank in the relation is used to determine an order in which the target ranks in the relation are selected to register for copying. For each selected target rank in the relation selected according to the determined order, an iteration of a registration operation is performed to register the selected target rank and a selected source rank copied to the selected target rank in the relation.

Abstract: A method, apparatus, and system in which an integrated circuit comprises an initiator Intellectual Property (IP) core, a target IP core, an interconnect, and a tag and thread logic. The target IP core may include a memory coupled to the initiator IP core. Additionally, the interconnect can allow the integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect. A tag and thread logic can be configured to concurrently perform per-thread and per-tag memory access scheduling within a thread and across multiple threads such that the tag and thread logic manages tags and threads to allow for per-tag and per-thread scheduling of memory accesses requests from the initiator IP core out of order from an initial issue order of the memory accesses requests from the initiator IP core.

Abstract: For handling multiple backup processes, computer-readable program code is described for receiving one or more instructions initiating a plurality of backup processes from a single source storage volume to a plurality of target storage volumes, adding each target storage volume to a cascade of target storage volumes from the source storage volume, the target storage volumes added to the cascade in an order inversely proportional to the copy rate of the respective backup process, and starting each backup process in turn, the backup processes started in an order from the most recent target storage volume added to cascade to the first target storage volume added to cascade.

Abstract: A system, method, and computer program product are provided for coalescing memory access requests. A plurality of memory access requests is received in a thread execution order and a portion of the memory access requests are coalesced into memory order, where memory access requests included in the portion are generated by threads in a thread block. A memory operation is generated that is transmitted to a memory system, where the memory operation represents the coalesced portion of memory access requests.

Abstract: A communication apparatus comprises a general-purpose memory, and a high-speed memory that allows higher-speed access than the general-purpose memory. Protocol processing is executed to packetize transmission data using a general-purpose buffer allocated to the general-purpose memory and/or a high-speed buffer allocated to the high-speed memory as network buffers.

Abstract: Systems, mediums, and methods are provided for scheduling input/output requests to a storage system. The input output requests may be received, categorized based on their priority, and scheduled for retrieval from the storage system. Lower priority requests may be divided into smaller sub-requests, and the sub-requests may be scheduled for retrieval only when there are no pending higher priority requests, and/or when higher priority requests are not predicted to arrive for a certain period of time. By servicing the small sub-requests rather than the entire lower priority request, the retrieval of the lower priority request may be paused in the event that a high priority request arrives while the lower priority request is being serviced.

Abstract: A control apparatus which controls an access to a memory acquires, for the access to the memory, a predetermined address corresponding to the order of addresses at which the memory is accessed, and determines whether the predetermined address is identical to the target address of the access. In a case where the predetermined address is identical to the target address, the control apparatus controls the access to the memory so as to perform page close after the end of the access to the target address.

Abstract: A data storage system includes a plurality of non-volatile memory devices arranged in one or more sets, a main controller and one or more processors. The main controller is configured to accept commands from a host and to convert the commands into recipes. Each recipe includes a list of multiple memory operations to be performed sequentially in the non-volatile memory devices belonging to one of the sets. Each of the processors is associated with a respective set of the non-volatile memory devices, and is configured to receive one or more of the recipes from the main controller and to execute the memory operations specified in the received recipes in the non-volatile memory devices belonging to the respective set.

Abstract: Incoming files are examined to detect abnormal files. The incoming files may be examined for a weak file structure, such as a weak file format structure or a weak file data structure, to detect abnormal files. A weak file structure includes file structures that do not conform to the file format of the file yet still loadable by a file loader of the file format. The incoming files may also be examined for suspicious loading in memory to detect abnormal files.

Abstract: An apparatus and method is described herein for providing speculative escape instructions. Specifically, an explicit non-transactional load operation is described herein. During execution of a speculative code region (e.g. a transaction or critical section) loads are normally tracked in a read set. However, a programmer or compiler may utilize the explicit non-transactional read to load from a memory address into a destination register, while not adding the read/load to the transactional read set. Similarly, a non-transactional store is also provided. Here, a transactional store is performed and not added to a write set during speculative code execution. And the store may be immediately globally visible and/or persistent (even after an abort of the speculative code region). In other words, speculative escape operations are provided to ‘escape’ a speculative code region to perform non-transactional memory accesses without causing the speculative code region to abort or fail.

Abstract: The systems and methods described herein may be used to implement scalable statistics counters suitable for use in systems that employ a NUMA style memory architecture. The counters may be implemented as data structures that include a count value portion and a node identifier portion. The counters may be accessible within transactions. The node identifier portion may identify a node on which a thread that most recently incremented the counter was executing or one on which a thread that has requested priority to increment the shared counter was executing. Threads executing on identified nodes may have higher priority to increment the counter than other threads. Threads executing on other nodes may delay their attempts to increment the counter, thus encouraging consecutive updates from threads on a single node. Impatient threads may attempt to update the node identifier portion or may update an anti-starvation variable to indicate a request for priority.

Abstract: A memory controller receives memory access requests from a host terminal, the memory access requests from the host terminal including one or both of host read requests and host write requests. The memory controller generates memory access requests. Priorities are assigned to the memory access requests. The memory access requests are segregated to memory unit queues of at least one set of memory unit queues, the set of memory unit queues associated with a memory unit. Each memory access request is sent to the memory unit according to a priority and an assigned memory unit queue of the memory access request.

Abstract: A memory accessing agent includes a memory access generating circuit and a memory controller. The memory access generating circuit is adapted to generate multiple memory accesses in a first ordered arrangement. The memory controller is coupled to the memory access generating circuit and has an output port, for providing the multiple memory accesses to the output port in a second ordered arrangement based on the memory accesses and characteristics of an external memory. The memory controller determines the second ordered arrangement by calculating an efficient row burst value and interrupting multiple row-hit requests to schedule a row-miss request based on the efficient row burst value.

Abstract: A method for managing concurrent system dumps of address spaces of memory of a computing system. The method comprises analyzing address space of memory to determine high priority areas and low priority areas of the address space. The method further comprises stopping all application threads of memory. In addition, the method further comprises performing a system dump of all the high priority areas of the address space. Moreover, the method further comprises initiating a background thread that performs a system dump of the low priority areas in background of the address space, and allowing, by the one or more computer processors, all of the application threads of memory to restart.

Abstract: According to one embodiment, a data storage apparatus includes a write command module, a read command module, and a controller. The write command module is configured to process a write command for writing data to the nonvolatile memories for a plurality of channels, respectively. The read command module is configured to process a read command usually and to process a read command for read modify write (RMW) operation. The controller is configured to control the read command module, causing to execute the read command for the RMW operation, prior to the normal read command, thereby to execute a flush command, and to control the write command module, causing to execute a write flush process that includes the processing of a write command for the RMW operation after the read command for the RMW operation has been executed.

Abstract: A data access method for accessing a rewritable non-volatile memory module via a data bus through a first and a second thread module, and a memory controller and a memory storage apparatus using the same are provided. In the present method, an access executing right is assigned to the second thread module to write page data. Whether an access command to be executed by the first thread module is received is determined when the second thread module writes a predetermined amount of page data into a predetermined number of physical pages. The access executing right is assigned to the first thread module when the access command is received, so that the first thread module executes the access command in a foreground mode and the second thread module executes an ongoing task in a background mode. Thereby, timeout caused by delayed response of the first thread module is effectively avoided.

Abstract: A method and apparatus for controlling traffic of multiprocessor system or multi-core system is provided. The traffic control apparatus of a multiprocessor system according to the present invention includes a request handler for processing a traffic request of a first processor, and a Quality of Service (QoS) manager for receiving a QoS guaranty start instruction for a second processor from the multiprocessor system, and for transmitting, when traffic of the second processor is detected, a traffic adjustment signal to the request handler. The request handler adjusts the traffic of the first processor according to the received traffic adjustment signal. The traffic control method and apparatus of the present invention is capable of adjusting the required bandwidths of individual technologies and guaranteeing the real-timeness in the multiprocessor system or multi-core system.

Abstract: A memory system and data processing system for controlling memory refresh operations in dynamic random access memories. The memory controller comprises logic that: tracks a time remaining before a scheduled time for performing a high priority, high latency operation a first memory rank of the memory system; responsive to the time remaining reaching a pre-established early notification time before the schedule time for performing the high priority, high latency operation, biases the re-order queue containing memory access operations targeting the plurality of ranks to prioritize scheduling of any first memory access operations that target the first memory rank. The logic further: schedules the first memory access operations to the first memory rank for early completion relative to other memory access operations in the re-order queue that target other memory ranks; and performs the high priority, high latency operation at the first memory rank at the scheduled time.

Abstract: Parallel pipelines are used to access a shared memory. The shared memory is accessed via a first pipeline by a processor to access cached data from the shared memory. The shared memory is accessed via a second pipeline by a memory access unit to access the shared memory. A first set of tags is maintained for use by the first pipeline to control access to the cache memory, while a second set of tags is maintained for use by the second pipeline to access the shared memory. Arbitrating for access to the cache memory for a transaction request in the first pipeline and for a transaction request in the second pipeline is performed after each pipeline has checked its respective set of tags.

Abstract: One embodiment sets forth a method for guiding the order in which a parallel processing subsystem executes memory copies. A driver creates semaphores for all but the lowest priority included in a plurality of priorities and associates one priority with each copy hardware channel included in the parallel processing subsystem. The driver then aliases prioritized streams to the copy hardware channels based on the priorities. Upon receiving a request to execute a memory copy within one of the streams, the driver inserts commands into the aliased copy hardware channel. These commands use the semaphores to direct the parallel processing subsystem to execute the memory copy based on the priority of the copy hardware channel. Advantageously, by assigning priorities to streams and, subsequently, strategically requesting memory copies within the prioritized streams, an application developer may fine-tune their software application to increase the overall processing efficiency of the software application.

Abstract: A method of applying scheduling policies is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a single chassis coupling the storage nodes as a cluster. The method includes receiving operations relating to a non-volatile memory of one of the plurality of storage nodes into a plurality of operation queues. The method includes evaluating each of the operations in the plurality of operation queues as to benefit to the non-volatile solid-state storage according to a plurality of policies. For each channel of a plurality of channels coupling the operation queues to the non-volatile memory, the method includes iterating a selection and an execution of a next operation from the plurality of operation queues, with each next operation having a greater benefit than at least a subset of operations remaining in the operation queues.

Abstract: Described herein are method and apparatus for scheduling access requests for a multi-bank low-latency random read memory (LLRRM) device within a storage system. The LLRRM device comprising a plurality of memory banks, each bank being simultaneously and independently accessible. A queuing layer residing in storage system may allocate a plurality of request-queuing data structures (“queues”), each queue being assigned to a memory bank. The queuing layer may receive access requests for memory banks in the LLRRM device and store each received access request in the queue assigned to the requested memory bank. The queuing layer may then send, to the LLRRM device for processing, an access request from each request-queuing data structure in successive order. As such, requests sent to the LLRRM device will comprise requests that will be applied to each memory bank in successive order as well, thereby reducing access latencies of the LLRRM device.

Abstract: Example embodiments of the present invention include a method, system and computer program product for managing spinlocks in a multi-core computer system. The method comprises providing a spinlock per core in the multi-core computer system and storing each spinlock in a respective memory location configured to be access independently by respective cores of the multi-core computer system. A request is then received at a core in the multi-core computer system to perform an operation on a spinlock in the multi-core computer system. A multi-reader/single writer spinlock is obtained in response to the request.

Abstract: In an information recording apparatus, when it is determined to perform a copy process, a copy processor copies content data cached in a first storage section to an information recording medium as copy destination. A process-result sender sends, to a copy-count management server, a result of the copy process. A cached-data abandoning unit abandons the content data cached in the first storage section if information regarding an allowable number of copies on which the result of the copy process has been reflected represents that a next copy process is disallowed.

Abstract: Systems, methods, and computer program products for mirroring dual writeable storage arrays are provided. Various embodiments provide configurations including two or more mirrored storage arrays that are each capable of being written to by different hosts. When commands to write data to corresponding mirrored data blocks within the respective storage arrays are received from different hosts at substantially the same time, write priority for writing data to the mirrored data blocks is given to one of the storage arrays based on a predetermined criterion or multiple predetermined criteria.

Abstract: A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified.

Abstract: A method for selectively storing data identified by a software application in higher performance media may include executing control programming for an operating system and a software application hosted by the operating system. The software application assigns a first importance level to a first portion of data and a second importance level to a second portion of data. A first portion of data having the first importance level assigned by the software application is stored in a first storage medium at the instruction of the operating system. A second portion of data having the second importance level assigned by the software application is stored in a second storage medium at the instruction of the operating system. The second storage medium has at least one performance, reliability, or security characteristic different from the first storage medium.

Abstract: A method and apparatus for utilizing a matrix to store numerical comparisons is disclosed. In one embodiment, an apparatus includes an array in which results of comparisons are stored. The comparisons are performed between numbers associated with agents (or functional units) that have access to a shared resource. The numbers may be a value to indicate a priority for their corresponding agents. The comparison results stored in an array may be generated based on comparisons between two different numbers associated with two different agents, and may indicate the priority of each relative to the other. When two different agents concurrently assert requests for access to the shared resource, a control circuit may access the array to determine which of the two has the higher priority. The agent having the higher priority may then be granted access to the shared resource.

Abstract: A method includes scheduling a memory request requested by a thread executing on a processing system. The scheduling is based on at least one of a number of critical sections being executed on the processing system by the thread and a number of other threads executing on the processing system being blocked from execution on the processing system by execution of the thread. In at least one embodiment of the invention, the thread is associated with a first application of a plurality of applications executing on the processing system and the scheduling is further based on an indicator of application priority.

Abstract: Systems, methods, and apparatus to identify and prioritize application processes in one or more subsystems. Some embodiments identifying applications and processes associated with each application executing on a system, apply one or more priority rules to the identified applications and processes to generate priority information, and transmit the priority information to a subsystem. The subsystem then matches received requests with the priority information and services the processes according to the priority information.

Abstract: Disclosed is a data processing and/or storage system. The data processing and/or storage system may include at least two interfaces, wherein each of the at least two interfaces includes a non-dedicated communication port for communicating data to and form external data systems or clients based on a rule base.

Abstract: A NAND flash memory logical unit. The NAND flash memory logical unit includes a control circuit that responds to commands and permits program and/or erase commands to be interruptible by read commands. The control circuit includes a set of internal registers for performing the current command, and a set of external registers for receiving commands. The control circuit also includes a set of supplemental registers that allow the NAND flash memory logical unit to have redundancy to properly hold state of an interrupted program or erase command. When the interrupted program or erase command is to resume, the NAND flash memory logical unit thus can quickly resume the paused program or erase operation. This provides significant improvement to read response times in the context of a NAND flash memory logical unit.

Abstract: A method and device for maintaining data in a data storage system, comprising a plurality of data storage nodes, the method being employed in a storage node in the data storage system and comprising: monitoring and detecting, conditions in the data storage system that imply the need for replication of data between the nodes in the data storage system; initiating replication processes in case such a condition is detected, wherein the replication processes include sending multicast and unicast requests to other storage nodes, said requests including priority flags, receiving multicast and unicast requests from other storage nodes, wherein the received requests include priority flags, ordering the received requests in different queues depending on their priority flags, and dealing with requests in higher priority queues with higher frequency than requests in lower priority queues.

Abstract: In accordance with the disclosed subject matter there is provided a method for segregating threads running in a computer system, and executing the threads according to this categorization.

Abstract: Embodiments of the invention operate within the context of a system with a processor providing memory-monitoring functionality. The lower-privileged code of a first process, such as user application code, communicates directly with higher-privileged code of a second process, such as interrupt-handling code of the operating system kernel, without using a software interrupt or other gate mechanism. This enhances overall system performance by eliminating the saving of state and processing inherent in interrupt handling, and also avoids missing events that may occur while other interrupts are masked during event handling. Specifically, the second process initializes a monitored memory area that is directly accessible by processes having at least the privilege level of the first process. The second process further initializes memory-monitoring hardware of the processor to monitor writes to the monitored memory area, such that the second process will resume execution from a dormant state when a write takes place.