Abstract: Methods and devices are provided for adapting an I/O pattern, with respect to a processing device using a non-volatile block storage device based on feedback from the non-volatile block storage device. The feedback may include information indicating a status of the non-volatile block storage device. In response to receiving the feedback, a storage subsystem, included in an operating system executing on processing device, may change a behavior with respect to the non-volatile block storage device in order to avoid, or reduce, a negative impact to the non-volatile block storage device or to enhance an aspect of the non-volatile block storage device. The feedback may include performance information and/or operating environmental information of the non-volatile block storage device. When the non-volatile block storage device is not capable of providing the feedback, the processing device may request information about the non-volatile block storage device from a database service.

Abstract: Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits.

Abstract: The invention relates to a memory controller for use in a System-on-Chip, wherein the System-on-Chip comprises a plurality of agents and an off-chip volatile memory. The memory controller comprises a first port (CBP) for receiving low-priority requests (CBR) for access to the volatile memory from a first-subset of the plurality of agents and a second port (LLP) for receiving high-priority requests (LLR) for access to the volatile memory from a second-subset of the plurality of agents, wherein the memory controller is configured for arbitrating between the high-priority requests (LLR) and the low-priority requests (CBR), wherein the memory controller is configured for receiving refresh requests (RFR) for the volatile memory via the first port (CBP), wherein the refresh requests (RFR) are time-multiplexed with the low-priority requests (CBR), wherein the memory controller is configured for treating the low-priority requests (CBR) and the refresh requests (RFR) the same.

Abstract: Subject matter disclosed herein relates to an apparatus comprising memory and a controller, such as a controller which determines block locking states in association with operative transitions between two or more interfaces that share at least one block of memory. The apparatus may support single channel or multi-channel memory access, write protection state logic, or various interface priority schemes.

Abstract: Various embodiments of the invention relate to an apparatus and a method of managing a snapshot storage pool (SSP) associated with a storage unit of a distributed data storage system. One apparatus includes a logic module and a processor. The logic module is adapted to provide a threshold corresponding to a ratio between a current amount of storage resources used for storing snapshots in the SSP and a total storage capacity defined for the SSP. The processor is adapted to trigger an action that may be effective for managing the SSP in response to the amount of storage resources used for storing snapshots in the SSP crossing the threshold.

Abstract: In one implementation, data values having an order are stored at a memory having a plurality of memory locations. Data values are periodically moved between memory locations according to a movement pattern. A selector is synchronized with the movement of the data values according to the movement pattern to select an output.

Abstract: The invention generally relates to rapid reading of data from multi-level cell (MLC) memory devices. Information is stored in a way that allows all of the bit-space to be used but that also allows single-read-per-cell retrieval. Data is triaged into high priority data and low priority data. The high priority data is then stored in an MLC memory device with one bit per cell. This data can them be read from the MLC cells by one comparison operation on each cell, accomplishing all of the required read operations in parallel in the time it takes to perform a single comparison. Low priority data is stored in the remaining bit-space of the cells, to take full advantage of all of the available bit-space of the cells.

Abstract: A multiprocessor data processing system includes a plurality of cache memories including a cache memory. In response to the cache memory detecting a storage-modifying operation specifying a same target address as that of a first read-type operation being processed by the cache memory, the cache memory provides a retry response to the storage-modifying operation. In response to completion of the read-type operation, the cache memory enters a referee mode. While in the referee mode, the cache memory temporarily dynamically increases priority of any storage-modifying operation targeting the target address in relation to any second read-type operation targeting the target address.

Abstract: An embodiment of the invention provides an apparatus and method for controlling access by a read-write spinlock with no mutual exclusion among readers. The apparatus and method perform the steps of using values in a data structure in the read-write spinlock to control read access to a shared object and using values in the data structure and a guard lock to control write access to the shared object.

Abstract: The present disclosure generally describes systems, methods and devices for operating a computer system with memory based scheduling. The computer system may include one or more of an application program and a memory controller in communication with memory banks. The memory controller may include a scheduler for scheduling requests. The application program may select a scheduling algorithm for scheduling requests from a plurality of scheduling algorithms. The application program may instruct the scheduler to schedule requests using the selected scheduling algorithm.

Abstract: Embodiments of the present invention are directed to a method, computer-readable medium and system for deskewing data. More specifically, skewed data is accessed and written into a plurality of memories in an aligned manner. Each memory may be associated with a respective lane of a multiple lane distribution (MLD) system and may receive a respective initial portion of data associated with a frame. The memory or lane that is the last to receive an initial portion of data associated with the frame may be determined. The address at which the initial portion of data is written into the memory may be determined using a write pointer associated with the memory. At least one read pointer associated with the memories may be set to the address to allow the initial portions of data to be contemporaneously read from the memories.

Abstract: The present patent document relates to a method and apparatus for maintaining coherency in a memory subsystem of an electronic system modeled in dual abstractions. The portions of the memory subsystem shared between the first abstraction and the second abstraction are shadowed in both abstractions, allowing either abstraction to coherently access memory written by the other. The memory subsystem can also reside solely in a first abstraction, where the second abstraction will synchronize to the first abstraction to access the memory subsystem. Flags associated with memory pages of the memory subsystem are set to indicate which abstraction has most recently updated the memory page. Prior to accessing a memory page, the system will check the flags, copying the contents of the memory in the other abstraction as needed to maintain coherency. The abstractions can operate either synchronously or asynchronously.

Abstract: File system disaster recovery techniques provide automated monitoring, failure detection and multi-step failover from a primary designated target to one of a designated group of secondary designated targets. Secondary designated targets may be prioritized so that failover occurs in a prescribed sequence. Replication of information between the primary designated target and the secondary designated targets allows failover in a manner that maximizes continuity of operation. In addition, user-specified actions may be initiated on failure detection and/or on failover operations and/or on failback operations.

Abstract: In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.

Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.

Abstract: In a NUMA-topology computer system that includes multiple nodes and multiple logical partitions, some of which may be dedicated and others of which are shared, NUMA optimizations are enabled in shared logical partitions. This is done by specifying a home node parameter in each virtual processor assigned to a logical partition. When a task is created by an operating system in a shared logical partition, a home node is assigned to the task, and the operating system attempts to assign the task to a virtual processor that has a home node that matches the home node for the task. The partition manager then attempts to assign virtual processors to their corresponding home nodes. If this can be done, NUMA optimizations may be performed without the risk of reducing the performance of the shared logical partition.

Abstract: According to one embodiment, a method for traffic prioritization in a memory device includes sending a memory access request including a priority value from a processing element in the memory device to a crossbar interconnect in the memory device. The memory access request is routed through the crossbar interconnect to a memory controller in the memory device associated with the memory access request. The memory access request is received at the memory controller. The priority value of the memory access request is compared to priority values of a plurality of memory access requests stored in a queue of the memory controller to determine a highest priority memory access request. A next memory access request is performed by the memory controller based on the highest priority memory access request.

Abstract: According to one embodiment, a memory device is provided. The memory device includes a processing element coupled to a crossbar interconnect. The processing element is configured to send a memory access request, including a priority value, to the crossbar interconnect. The crossbar interconnect is configured to route the memory access request to a memory controller associated with the memory access request. The memory controller is coupled to memory and to the crossbar interconnect. The memory controller includes a queue and is configured to compare the priority value of the memory access request to priority values of a plurality of memory access requests stored in the queue of the memory controller to determine a highest priority memory access request and perform a next memory access request based on the highest priority memory access request.

Abstract: A non-volatile semiconductor memory module is disclosed comprising a memory device and memory controller operably coupled to the memory device, wherein the memory controller is operable to receive a host command, split the host command into one or more chunks comprising a first chunk comprising at least one logical block address (LBA), and check the first chunk against an active chunk coherency list comprising one or more active chunks to determine whether the first chunk is an independent chunk, and ready to be submitted for access to the memory device, or a dependent chunk, and deferred access to the memory device until an associated dependency is cleared.

Abstract: A modular system for acquiring biometric data includes a plurality of data acquisition modules configured to sample biometric data from at least one respective input channel at a data acquisition rate. A representation of the sampled biometric data is stored in memory of each of the plurality of data acquisition modules. A central control system is in communication with each of the plurality of data acquisition modules through a bus. The central control system is configured to collect data asynchronously, via the bus, from the memory of the plurality of data acquisition modules according to a relative fullness of the memory of the plurality of data acquisition modules.

Abstract: A semiconductor memory system may include a plurality of memory devices each configured to have multiple planes, and an access controller configured to access each of the multiple planes corresponding to each of the plurality of memory devices as a unit memory.

Abstract: The systems and methods described herein may be used to implement scalable statistics counters suitable for use in systems that employ a NUMA style memory architecture. The counters may be implemented as data structures that include a count value portion and a node identifier portion. The counters may be accessible within transactions. The node identifier portion may identify a node on which a thread that most recently incremented the counter was executing or one on which a thread that has requested priority to increment the shared counter was executing. Threads executing on identified nodes may have higher priority to increment the counter than other threads. Threads executing on other nodes may delay their attempts to increment the counter, thus encouraging consecutive updates from threads on a single node. Impatient threads may attempt to update the node identifier portion or may update an anti-starvation variable to indicate a request for priority.

Abstract: In a computer system supporting execution of virtualization software and at least one instance of virtual system hardware, an interface is provided into the virtualization software to allow a program to directly define the access characteristics of its program data stored in physical memory. The technique includes providing data identifying memory pages and their access characteristics to the virtualization software which then derives the memory access characteristics from the specified data. Optionally, the program may also specify a pre-defined function to be performed upon the occurrence of a fault associated with access to an identified memory page. In this manner, programs operating both internal and external to the virtualization software can protect his memory pages, without intermediation by the operating system software.

Abstract: Memory arbiter with latency guarantees for multiple ports. A method of controlling access to an electronic memory includes measuring a latency value indicative of a time difference between origination of an access request from a port of a plurality of ports and a response from the electronic memory. The method also includes calculating a difference between the latency value for the port and a target value associated with the port. The method further includes calculating a running sum of differences for the port covering each of a plurality of access requests. Further, the method includes determining a delta of a priority value for the port based on the running sum of differences. Moreover, the method includes prioritizing the access by the plurality of ports according to associated priority values.

Abstract: Unsecure system software and secure system software on the same computer system is switched between. A computer system includes one or more processors, which may not have any built-in security features, memory, and firmware. The memory stores secure system software and unsecure system software. In response to receiving a user signal, the firmware switches from the unsecure system software running on the processors to the secure system software running on the processors (and back again). While the unsecure system software is running, the secure system software is protected from tampering by the unsecure system software.

Abstract: An apparatus and method is provided for coupling additional memory to a plurality of processors. The method may include determining the memory requirements of the plurality of processors in a system, comparing the memory requirements of the plurality of processors to an available memory assigned to each of the plurality of processors, and selecting a processor from the plurality of processors that requires additional memory capacity. The apparatus may include a plurality of processors, where the plurality of processors is coupled to a logic element. In addition, the apparatus may include an additional memory coupled to the logic element, where the logic element is adapted to select a processor from the plurality of processors to couple with the additional memory.

Abstract: A method, system, and apparatus for improving performance when retrieving data from one or more storage media. Files to be stored on the one or more storage media are classified into a ranking of different sets. Differences in retrieval value of different regions of the one or more storage media are exploited by selecting which files to store in which regions. For example, files that have a higher classification are stored in regions with faster retrieval values. The files can be classified based on frequency of access. Thus, files that are more frequently accessed are stored in regions that have a faster retrieval value. The files can be classified by another measure such as priority. For example, the classification for some or all of the files can be based on user-assigned priority. The classification may be based on events or data grouping.

Abstract: A printing apparatus to perform a printing operation by driving hardware provided thereto according to a printing command received from a user, including a firmware unit to store function information of a plurality of models of the printing apparatus, and selectively perform the function of one of the plurality of models which corresponds to a model index designated as the printing apparatus is initialized.

Abstract: Some embodiments of the present invention provide a system that avoids deadlock while attempting to acquire store-marks on cache lines. During operation, the system keeps track of store-mark requests that arise during execution of a thread, wherein a store-mark on a cache line indicates that one or more associated store buffer entries are waiting to be committed to the cache line. In this system, store-mark requests are processed in a pipelined manner, which allows a store-mark request to be initiated before preceding store-mark requests for the same thread complete. Next, if a store-mark request fails, within a bounded amount of time, the system removes or prevents store-marks associated with younger store-mark requests for the same thread, thereby avoiding a potential deadlock that can arise when one or more other threads attempt to store-mark the same cache lines.

Abstract: In one embodiment, a method receives current latency values from a plurality of host computers where a current latency value is calculated by a respective host computer based on an amount of time spent in the respective host computer's issue queue by an IO request most recently removed from the issue queue of the respective host computer. The issue queue of the respective host computer is used to transmit IO requests from the respective host computer to a storage system. The method then calculates a combined average latency value based on the current latency values and sends the combined average latency value to the plurality of host computers. Each respective host computer adjusts a size of the respective host computer's issue queue based on the combined average latency value, and the size controls a number of IO requests that are added to the respective host computer's issue queue.

Abstract: A device and methods are provided for accessing memory. In one embodiment, a method includes receiving a request for data stored in a device, checking a local memory for data based on the request to determine if one or more blocks of data associated with the request are stored in the local memory, and generating a memory access request for one or more blocks of data stored in a memory of the device based when one or more blocks of data are not stored in the local memory. In one embodiment, data stored in memory of the device may be arranged in a configuration to include a plurality of memory access units each having adjacent lines of pixel data to define a single line of memory within the memory access units. Memory access units may be configured based on memory type and may reduce the number of undesired pixels read.

Abstract: A programming and debugging system identifies one or more statically-allocated symbols in a symbol table for an inferior process. The statically-allocated symbols pertain to one or more structures for the inferior process. The inferior process has dynamic memory allocations in an inferior process memory space. The symbol table comprises data used to categorize the statically-allocated area of memory. The system locates the structures in the inferior process memory space and determines whether an address of the structures in the inferior process memory space matches an address of a block of the dynamically allocated area of memory. The system categorizes the block of dynamically allocated memory based on the determination of whether an address of the structures matches an address of a block of the dynamically allocated area of memory.

Abstract: A processor includes a CPU core which executes a user program, and a data transfer apparatus. The CPU core stores a transfer request from a user program in a specific area of a main memory, in which the transfer request specifies the virtual addresses of a transfer source and a transfer destination in a memory space allocated to the user program. The data transfer apparatus refers to the specific area of the main memory and acquires a transfer request asynchronously to processing performed by the CPU core. The data transfer apparatus then identifies physical addresses corresponding to virtual addresses specified in the transfer request. After that, the data transfer apparatus transcribes original data stored in a storage area indicated by the physical address of the transfer source, to a storage area in a cache memory related to the virtual address or physical address of the transfer destination.

Abstract: A programming and debugging system determines a block of dynamically allocated memory in an inferior process memory space corresponds to a structure and casts the block of memory as an instance of the structure. The programming and debugging system determines a field type of a field in the instance of the structure and determines whether memory data pertaining to the block of dynamically allocated memory satisfies one or more criteria in heuristics data associated with the field type. The programming and debugging system categorizes the block of dynamically allocated memory based on the determination of whether the memory data satisfies the one or more criteria of the field type.

Abstract: One embodiment of the present invention sets forth a technique for synchronization between two or more processors. The technique implements a spinlock acquire function and a spinlock release function. A processor executing the spinlock acquire function advantageously operates in a low power state while waiting for an opportunity to acquire spinlock. The spinlock acquire function configures a memory monitor to wake up the processor when spinlock is released by a different processor. The spinlock release function releases spinlock by clearing a lock variable and may clear a wait variable.

Abstract: Requests from a plurality of different agents (10) are passed to a request handler via a request concentrator. In front of the request concentrator the requests are queued in a plurality of queues (12). A first one of the agents is configured to issue a priority changing command with a defined position relative to pending requests issued by the first one of the agents (10) to the first one of the queues (12). An arbiter (16), makes successive selections selecting queues (12) from which the request concentrator (14) will pass requests to the request handler (18), based on relative priorities assigned to the queues (12). The arbiter (16) responds to the priority changing command by changing the priority of the first one of the queues (12), selectively for a duration while the pending requests up to the defined position are in the first one of the queues (12). Different queues may be provided for read and write requests from the first one of the agents.

Abstract: This invention is an integrated memory controller/interconnect that provides very high bandwidth access to both on-chip memory and externally connected off-chip memory. This invention includes an arbitration for all memory endpoints including priority, fairness, and starvation bounds; virtualization; and error detection and correction hardware to protect the on-chip SRAM banks including automated scrubbing.

Abstract: The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters. The two consecutive slots assigned per cache line access are always in the same direction for maximum access rate.

Abstract: A hard disk controller (HDC) of a hard disk drive (HDD) includes an encoder module, a buffer manager module, N first-in first-out (FIFO) modules, and N read channel modules, where N is an integer greater than 1. The encoder module is configured to encode data received from a host and to generate P units of encoded data, where P is an integer greater than 1. The buffer manager module is configured to store the P units of encoded data in a buffer, retrieve N of the P units from the buffer, and output the N units in parallel. The N FIFO modules are configured to receive the N units in parallel from the buffer manager. The N read channel modules are configured to receive the N units from the N FIFO modules in parallel, respectively, and to output the N units to a magnetic medium of the HDD.

Abstract: A method and device for maintaining data in a data storage system, comprising a plurality of data storage nodes, the method being employed in a storage node in the data storage system and comprising: monitoring and detecting, conditions in the data storage system that imply the need for replication of data between the nodes in the data storage system; initiating replication processes in case such a condition is detected, wherein the replication processes include sending multicast and unicast requests to other storage nodes, said requests including priority flags, receiving multicast and unicast requests from other storage nodes, wherein the received requests include priority flags, ordering the received requests in different queues depending on their priority flags, and dealing with requests in higher priority queues with higher frequency than requests in lower priority queues.

Abstract: A system and method in one embodiment includes modules for detecting an access attempt to a critical address space (CAS) of a guest operating system (OS) that has implemented address space layout randomization in a hypervisor environment, identifying a process attempting the access, and taking an action if the process is not permitted to access the CAS. The action can be selected from: reporting the access to a management console of the hypervisor, providing a recommendation to the guest OS, and automatically taking an action within the guest OS. Other embodiments include identifying a machine address corresponding to the CAS by forcing a page fault in the guest OS, resolving a guest physical address from a guest virtual address corresponding to the CAS, and mapping the machine address to the guest physical address.

Abstract: An embodiment provides for operating an information processing system. An aspect of the invention includes allocating an execution interval to a first logical processor of a plurality of logical processors of the information processing system. The execution interval is allocated for use by the first logical processor in executing instructions on a physical processor of the information processing system. The first logical processor determines that a resource required for execution by the first logical processor is locked by another one of the other logical processors. An instruction is issued by the first logical processor to determine whether a lock-holding logical processor is currently running. The lock-holding logical processor waits to release the lock if it is currently running. A command is issued by the first logical processor to a super-privileged process for relinquishing the allocated execution interval by the first logical processor if the locking holding processor is not running.

Abstract: Apparatuses, methods, and systems for reconfiguring a secure system are disclosed. In one embodiment, an apparatus includes a configuration storage location, a lock, and lock override logic. The configuration storage location is to store information to configure the apparatus. The lock is to prevent writes to the configuration storage location. The lock override logic is to allow instructions executed from sub-operating mode code to override the lock.

Abstract: A method for more effectively distributing the I/O workload in a data replication system is disclosed herein. In selected embodiments, such a method may include generating an I/O request and identifying a storage resource group associated with the I/O request. In the event the I/O request is associated with a first storage resource group, the I/O request may be directed to a first storage device and a copy of the I/O request may be mirrored from the first storage device to a second storage device. Alternatively, in the event the I/O request is associated with a second storage resource group, the I/O request may be directed to a second storage device and a copy of the I/O request may be mirrored from the second storage device to the first storage device.

Abstract: A method, computer program product, and computing system for maintaining a queue of cache operations to be performed within a cache memory system. The cache operations include one or more of cache write operations and cache read operations. The cache operations within the queue are reordered based, at least in part, upon a maximum acceptable write operation latency.

Abstract: In some embodiments, a method for generating financial reports, includes selecting a first request from a plurality of pending requests. The first request requests a report on information regarding one or more accounts with a financial institution. The first request is separated into a plurality of content requests. The plurality of content requests represent requests for information to be incorporated into the requested report. A plurality of subreports are received in response to each of the plurality of content requests. The requested report is generated in response to the first request by binding each of the plurality of subreports.

Abstract: According to an aspect of the embodiment, an FP includes a plurality of entries which holds requests to be processed, and each of the plurality of entries includes a requested flag indicating that data transfer is once requested. An FP-TOQ holds information indicating an entry holding the oldest request. A data transfer request prevention determination circuit checks the requested flag of a request to be processed and the FP-TOQ, and when a transfer request of data as a target of the request to be processed has already been issued and the entry holding the request to be processed is not the entry indicated by the FP-TOQ, transmits a signal which prevents the transfer request of the data to a data transfer request control circuit. Even when a cache miss occurs in a primary cache RAM, the data transfer request control circuit does not issue a data transfer request when the signal which prevents the transfer request is received.

Abstract: A method of communicating over a bus is disclosed. The bus includes a write address channel, a write channel, and a read address channel. The method includes sending an address from a sending device to a receiving device via the write address channel. The method further includes concurrently sending a portion of a payload to the receiving device via the write channel and another portion of the payload to the receiving device via the read address channel. When sending multiple sequential portions of the payload via the bus concurrently, the sending device is configured to give data ordering preference to the write channel over the read address channel by sending a first sequential portion of the multiple sequential portions via the write channel and sending a subsequent sequential portion of the multiple sequential portions via the read address channel.

Abstract: An apparatus including a first memory, a second memory, and a memory interface. The first memory may be configured to store an entire image. The second memory may be configured to store a portion of the image during an image processing operation. The memory interface may be configured to transfer the portion of the image (i) from a source area of the first memory to the second memory prior to the image processing operation and (ii) from the second memory to a destination area of the first memory following the image processing operation. The memory interface may be further configured to select from among four modes of transferring image data from the source area of the first memory and to the destination area of the first memory based upon how the source area and the destination area overlap in the first memory.

Abstract: The invention provides a data access method of a memory device. In one embodiment, the memory device comprises a plurality of memories. First, a plurality of commands sequentially received from a host is stored in a command queue. A target command is then retrieved from the command queue. A target memory accessed by the target command is then determined. Whether the target memory is in a busy state is then determined. When the target memory is not in a busy state, access operations requested by the target command are then performed. When the target memory is in a busy state, a substitute command is selected from a plurality of subsequent commands stored in the command queue and access operations requested by the substitute command are performed, wherein the sequence of the subsequent commands in the command queue is subsequent to the target command.