Abstract: Embodiments of the present disclosure include a digital circuit and method for multi-stage compression. Digital data values are compressed using a multi-stage compression algorithm and stored in a memory. A decompression circuit receives the values and performs a partial decompression. The partially compressed values are provided to a processor, which performs the final decompression. In one embodiment, a vector of N length compressed values are decompressed using a first bit mask into two N length sets having non-zero values. The two N length sets are further decompressed using two M length bit masks into M length sparse vectors, each having non-zero values.

Abstract: A data storage device, in one implementation, includes a memory device having Single Level Cell (SLC) blocks and Multi-Level Cell (MLC) blocks, such as Triple Level Cell (TLC) blocks. If a SLC block is determined to have errors, the SLC block is reallocated as a TLC block. In some implementations, the TLC block is used to store TLC cold data.

Abstract: A memory system identifies, in a logical to physical (L2P) journal associated with a memory device, a first journal entry reflecting a two pass programming operation, where the two pass programming operation includes a first pass to program data to a second memory location identified by a second physical address and a second pass to program a same data to a same second memory location identified by a same second physical address. The system determines whether the second pass of the two pass programming operation is complete. Responsive to determining that the second pass of the two pass programming operation is complete, the system causes a second journal entry of the L2P journal to reference from a first physical address to the second physical address. The system reconstructs the L2P table based on the second journal entry.

Abstract: A memory sub-system configured to dynamically determine input/output sizes of write commands based on a media physical layout of a memory sub-system. The memory sub-system can identify, dynamically in response to write commands being selected for execution in media units of the memory sub-system, a portion of a media layout that maps from logical addresses identified by the write commands in the logical address space to physical addresses of memory units in the media units. Based on the media layout, an input/output size for a next write command is identified and transmitted to the host system in a response. The host system generates the next write command and configures the amount of data to be written through the next write command based on based on the input/output size identified in the response.

Abstract: A storage system includes a NAND storage media and a nonvolatile storage media as a write buffer for the NAND storage media. The write buffer is partitioned, where the partitions are to buffer write data based on a classification of a received write request. Write requests are placed in the write buffer partition with other write requests of the same classification. The partitions have a size at least equal to the size of an erase unit of the NAND storage media. The write buffer flushes a partition once it has an amount of write data equal to the size of the erase unit.

Abstract: Systems and methods are disclosed including a memory device and a processing device, operatively coupled with the memory device, to perform operations comprising: receiving a write data request to store write data to the memory device; determining a physical block address associated with the write data request; performing a bitwise operation on each bit of the physical block address to generate a seed value; generating an output sequence based on the seed value; performing another bitwise operation on the output sequence and the write data to generate a randomized sequence; and storing, on the memory device, the randomized sequence.

Abstract: Systems and methods are provided for managing data partitions in a distributed storage system and, in particular, the routing data used by the distributed storage system to route requests to the proper caching layers, persistent storage nodes, etc. Data items may be managed in a multi-tier configuration in which they are grouped into different partitions based on their key prefixes, and partitions are grouped into different cells based on key ranges. When partitions are moved from cell-to-cell, or when cells are split, the routing data is changed accordingly. In order to ensure that the correct routing data is used throughout the distributed storage system, a change to routing data may be accompanied by a special barrier record being written to the transaction log of affected partitions.

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to identify a set of embedded servo cells stored on the memory device; determine a read voltage offset by performing read level calibration based on the set of embedded servo cells; and apply the read voltage offset for reading a memory page associated with the set of embedded servo cells.

Abstract: A memory system includes a plurality of memory groups capable of performing a data input/output operation, and a controller configured to divide an operation subject to a data input/output command into at least one unit operation corresponding to the plurality of memory groups, and assign the at least one unit operation to plural queues corresponding to the respective memory groups, based on first information regarding operation statuses of the plurality of memory groups and second information regarding available resources.

Abstract: Latency in a node-based compute-near-memory system can be problematic. A solution to the problem can include or use a dedicated software-based cache at each node. The cache can be configured to store information received from each of the other nodes in the system. In an example, the cache can be populated during a breadth first search algorithm to store frontier information from each of the other nodes.

Abstract: Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.

Abstract: The present disclosure includes apparatuses and methods related to a data buffer in a non-volatile dual in-line memory module (NVDIMM). An example apparatus can include a data buffer couplable to a host, a first memory device (e.g., volatile memory), wherein the first memory device is coupled to the data buffer via a first bus, a second memory device (e.g., non-volatile memory), and a controller, wherein the controller is coupled to the data buffer via a second bus and wherein the controller is configured to cause a data transfer from first memory device to the second memory device via the data buffer and the second bus.

Abstract: The present invention provides a microcontroller, wherein the microcontroller includes a processor, a first memory and a cache controller. The first memory includes at least a working space. The cache controller is coupled to the first memory, and is arranged for managing the working space of the first memory, and dynamically loading at least one object from a second memory to the working space of the first memory in an object-oriented manner.

Abstract: A storage device includes a first memory device, a second memory device and a storage controller. The first memory device buffers a plurality of unit time interval data. The plurality of unit time interval data are received in each of a plurality of monitoring time intervals. The second memory device stores at least one of the plurality of unit time interval data. The storage controller controls an amount of data flushed from the first memory device to the second memory device based on one of first and second flush commands. The storage controller compares a shock measurement value representing a magnitude of an external shock with a shock reference value. When the shock measurement value is less than or equal to the shock reference value, the storage controller provides the first flush command to the first memory device to flush first unit time interval data.

Abstract: A data storage system can connect a data storage controller to a host and a data storage device. A first reference state corresponding to a first zone of the data storage device can be incremented in response to a first version of data being assigned to the first zone by the data storage controller. A second version of the data may be written to a second zone of the data storage device prior to populating a recently freed list with the first zone having an incorrect reference state. The first zone can be allocated by the data storage controller for new data without altering the incorrect reference state that is subsequently written to the first zone as directed by the data storage controller.

Abstract: An electronic device includes a memory, a processor, and functional hardware. The memory includes a queue. The processor is configured to write a processing instruction into a target area of the queue. The functional hardware is configured to read the processing instruction from the target area and reserve the target area. The functional hardware generates a completion message according to the processing instruction, and writes the completion message into the target area after the processing instruction is executed. The completion message corresponds to the processing instruction.

Abstract: A memory system may include a memory device suitable for storing data and a controller suitable for generating and managing map data comprising a logical address of an external device and a physical address of the memory device corresponding to the logical address. The controller uploads at least some of the map data to the external device and uploading a latest version of the uploaded map data to the external device again based on dirty information or access information. The dirty information indicates whether a physical address corresponding to a logical address included in the uploaded map data has been changed. The access information indicates whether an access request for the logical address included in the uploaded map data from the external device has been made.

Abstract: A memory system may include a storage medium including a buffer region and a main region; and a controller configured to, when performing a flush operation, move normal data from the buffer region to the main region and maintain pinned data in the buffer region, wherein the pinned data is data which is determined by a host device to be maintained in the buffer region irrespective of the flush operation.

Abstract: A multi-channel memory storage device, a memory control circuit unit, and a data reading method are provided. The method includes: determining whether a storage space of a buffer memory is insufficient when a multi-channel access is performed; issuing a data read command corresponding to each of a plurality of multi-channels to a rewritable non-volatile memory module according to a logical address in a host read command in response to insufficient storage space of the buffer memory to read data corresponding to each of the plurality of multi-channels from a data storage area to a data cache area via the plurality of multi-channels; and allocating the storage space of the buffer memory to the rewritable non-volatile memory module after the storage space of the buffer memory is released and issuing a cache read command to move first data in data temporarily stored in the data cache area to the buffer memory.

Abstract: Methods, systems, and apparatuses for graph streaming processing system are disclosed. One system includes a plurality of graph streaming processors operative to process a plurality of threads, wherein the plurality of threads is organized as nodes. The system further includes a scheduler that includes a plurality of stages. Each stage includes a command parser operative to interpret commands within a corresponding input command buffer, an alternate command buffer, and a thread generator coupled to the command parser. The thread generator is operative to generate the plurality of threads, and dispatch the plurality of threads, where the processing of the plurality of thread for each stage includes storing write commands in the corresponding output command buffer or in the alternate command buffer.

Abstract: A computing system having memory components of different tiers. The computing system further includes a controller, operatively coupled between a processing device and the memory components, to: receive from the processing device first data access requests that cause first data movements across the tiers in the memory components; service the first data access requests after the first data movements; predict, by applying data usage information received from the processing device in a prediction model trained via machine learning, second data movements across the tiers in the memory components; and perform the second data movements before receiving second data access requests, where the second data movements reduce third data movements across the tiers caused by the second data access requests.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, a memory system writes, when performing the sudden power-off recovery operation, a plurality of target segments which are segments most recently written to each of the plurality of open memory blocks among the plurality of memory blocks to a target memory block among the plurality of memory blocks.

Abstract: Methods and systems for increasing reliability of a data storage device are disclosed. During fabrication runs of a non-volatile memory (NVM) die, such as a NAND, there may be a number of memory cells designated as erase cells. When one or more erase cells are physically adjacent to programmed memory cell, electrical effects of the erase cell may cause a bit to flip in the adjacent good memory cell. To mitigate this effect, an LDPC engine is used to generate additional parity bits for the erased bit/cells. When a host requests data from the NVM, the parity bits may be used to correct additional errors because of the erased state to programmed state bit flips.

Abstract: A memory system includes a memory device including memory blocks, and a controller configured to in response to a program request or a read request for a selected memory block among the memory blocks being received from a host, store first data to which a first logical address is allocated in a cache group, generate a first entry for the first data stored in the cache group, and in response to second data to which the first logical address is allocated being stored in the cache group after the first data is stored in the cache group, generate a second entry for the second data.

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.

Abstract: Memory systems, memory controllers, and operation methods of the memory systems are disclosed. In one example aspect, the memory system may suspend a target operation, such as a program operation or an erase operation, based on whether or not to execute a first operation of resetting a reference read bias when a failure occurs in a read operation executed after the target operation is suspended, and a number of times the target operation is suspended. In this way, the memory system may reduce a delay associated with the suspension of program operations and erasure operations.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may repeatedly execute, when entering a low power mode, iterations of a target operation according to a temperature of the memory system until a stop condition is satisfied. In this case, the target operation may be a garbage collection operation for the plurality of memory blocks or a migration operation of moving data stored in a first area including at least one of the plurality of memory blocks to a second area including at least one of the plurality of memory blocks. The operation speed of the memory block included in the first area may be higher than the operation speed of the memory block included in the second area.

Abstract: Various implementations described herein relate to systems and methods for managing metadata using an in-memory journal, including determining metadata for data, storing the metadata in an in-memory journal, detecting an imminent interruption to operations of the storage device, in response to detecting the imminent interruption, program the in-memory journal to a non-volatile memory device of the storage device, detect that the operations of the storage device are being restored, and in response to detecting that the operations of the storage device are being restored, performing metadata update. The first data is read from first original areas of a non-volatile memory. The first metadata includes a first physical address for each of first new areas of the non-volatile memory. The metadata is programmed in a metadata area of the non-volatile memory device.

Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The controller manages memory area sets. The controller distributes a first memory area set into a first group. The controller distributes a second memory area set into a second group. The controller comprises first to fourth circuits. The first circuit processes a first read request from a host to the first memory area set. The second circuit processes a first write request from the host to the first memory area set. The third circuit processes a second read request from the host to the second memory area set. The fourth circuit processes a second write request from the host to the second memory area set.

Abstract: The present disclosure provides a method for storing data, including: storing data in a first node, the first node being selected from a first node set including a first edge node and child nodes thereof; selecting, from a second node set including a second edge node and child nodes thereof, a second node for storing the data, the first edge node being a child node of the second edge node; and storing the data in the second node. The present disclosure further provides a method for searching for data. The present disclosure can reduce the time for searching for data in a distributed storage system.

Abstract: One example method includes file specific compression selection. Compression metrics are generated for a chunk of a file using a reference compressor. Compression metrics for other compressors are determined from the metrics of the reference compressor. A compressor is then selected to compress the file.

Abstract: Embodiments of the present invention relate to a centralized network analytic device, the centralized network analytic device efficiently uses on-chip memory to flexibly perform counting, traffic rate monitoring and flow sampling. The device includes a pool of memory that is shared by all cores and packet processing stages of each core. The counting, the monitoring and the sampling are all defined through software allowing for greater flexibility and efficient analytics in the device. In some embodiments, the device is a network switch.

Abstract: In at least one embodiment, processing can include receiving a metadata (MD) structure including MD pages; and performing a MD split operation with respect to a first of the MD pages, wherein said performing the MD split operation includes: generating a first ALI (abstract logical index) representing a new MD page that is unallocated and is a child of the first MD page; and storing an entry in a bucket of an in-memory MD log for the first ALI, wherein the entry denotes a mapping between the first ALI and a corresponding LI (logical index), wherein the entry indicates that the corresponding LI associated with the first ALI is invalid since the first ALI represents a new MD page which is unallocated and not associated with physical storage; and destaging the in-memory MD log, wherein said destaging includes allocating first physical storage for the new MD page.

Abstract: A storage device includes: a nonvolatile memory including power loss protector (PLP) memory blocks configured to store at least one of meta data or user data for data backup; a buffer memory configured to store at least one of the meta data or the user data stored in the PLP memory blocks; a charging circuit configured to generate electric power for data backup in response to a sudden power off (SPO) occurrence, and transmit a first charging complete signal or a second charging complete signal to a processor according to a level of the electric power, and; and the processor configured to control at least one of the nonvolatile memory and the buffer memory to execute a first request from a host related to the meta data with priority in response to the first charging complete signal, and execute a second request from the host related to the meta data or the user data in response to the second charging complete signal.

Abstract: Devices and techniques for communicating a programmable atomic operator to a memory controller are described herein. A memory controller can receive a memory request and extract a command indicator that indicates a programmable atomic operator (PAO) command from the memory request. The memory controller can then extract a PAO index from the request and invoke the PAO based on the PAO index.

Abstract: A memory system may write, when operating in a force unit access mode, first write data requested by the host to a buffer for temporarily storing data to be written the memory device and a first memory block among the plurality of memory blocks, and may write, when the size of the data accumulatively stored in the buffer is greater than or equal to A which is a unit of a size in which data is written to a second memory block among the plurality of memory blocks, second write data of size A among the data stored in the buffer to the second memory block. The operation speed of the first memory block may be set faster than the operation speed of the second memory block and the storage capacity of the first memory block may be set smaller than the storage capacity of the second memory block.

Abstract: A non-volatile storage device according to an embodiment of the present technology includes a storage section and a calculation section. The storage section includes a plurality of block sections each including a plurality of page sections into which data can be written independent of each other, the plurality of block sections being capable of collectively deleting the data written in the plurality of page sections. The calculation section calculates, on the basis of information about write conditions of the plurality of page sections included in the storage section, candidate addresses that are candidates of logical addresses of the data to be written into the plurality of page sections.

Abstract: Embodiments of the present disclosure provide a memory detection method and detection apparatus, for detecting a current-leakage bitline. The method includes: a memory including a plurality of memory cells, a plurality of sense amplifiers, and the sense amplifier including a power line providing a low potential voltage and a power line providing a high potential voltage; writing first memory data to each of the memory cells; performing a reading operation after the first memory data is written; acquiring a first test result based on a difference between first real data and the first memory data; performing the reading operation again to read second real data in each of the memory cells; acquiring a second test result based on a difference between the second real data and second memory data; and acquiring a specific position of the current-leakage bitline based on the second test result and the first test result.

Abstract: A memory sub-system to, in response to a power up, initiate a first loading process associated with a set of trim values, wherein the first loading process includes loading a sequence of the set of trim values to one or more registers of the memory sub-system. An operation associated with a memory unit of the memory sub-system is identified. A portion of the set of trim values corresponding to the operation associated with the memory unit is identified. The memory sub-system executes a second loading process comprising loading the portion of the set of trim values corresponding to the operation associated with the memory unit. The operation is executed using the portion of the set of trim values loaded into the one or more registers associated with the memory unit.

Abstract: A quantum computing service includes connections to one or more quantum hardware providers that are configured to execute quantum circuits using quantum computers based on one or more quantum technologies. The quantum computing service also includes at least one edge computing device located adjacent to a quantum computer at one of the quantum hardware provider facilities. The edge computing device is configured to execute classical computing portions of a hybrid algorithm in coordination with the quantum computer, which executes quantum computing portions of the hybrid algorithm. Results of the execution of the hybrid algorithm are automatically stored to a data storage service accessible to the customer.

Abstract: Embodiments of the present application provide an online program updating method, including: receiving an external command, acquiring an updated program file, and storing the updated program file into the backup area through a program in the application area, where the external command includes the updated program file, and running the updated program file when a program counter jumps to the backup area. This solution, after the program counter jumps to the backup area, runs the updated program file, thereby providing power continuously while updating the online program and improving the reliability of the power supply system.

Abstract: Methods, systems, and devices for stacked memory dice and combined access operations are described. A device may include multiple memory dice. One die may be configured as a master, and another may be configured as a slave. The master may communicate with a host device. A slave may be coupled with the master but not the host device. The device may include a first die (e.g., master) and a second die (e.g., slave). The first die may be coupled with a host device and configured to output a set of data in response to a read command. The first die may supply a first subset of the data and obtain a second subset of the data from the second die. In some cases, the first die may select, based on a data rate, a modulation scheme (e.g., PAM4, NRZ, etc.) and output the data using the selected modulation scheme.

Abstract: Systems and methods for storing data are described. A system can comprise a controller, one or more physical non-volatile memory devices, a bus comprising a plurality of input/output (I/O) lines. The controller configured to receive data, encode the received data into a codeword, and transfer, in parallel, different portions of the codeword to different physical non-volatile memory devices among the plurality of physical non-volatile memory devices.

Abstract: A request node is provided comprising request circuitry to issue write requests to write data to storage circuitry. The write requests are issued to the storage circuitry via a coherency node. Status receiving circuitry receives a write status regarding write operations at the storage circuitry from the coherency node and throttle circuitry throttles a rate at which the write requests are issued to the storage circuitry in dependence on the write status. A coherency node is also provided, comprising access circuitry to receive a write request from a request node to write data to storage circuitry and to access the storage circuitry to write the data to the storage circuitry. Receive circuitry receives, from the storage circuitry, an incoming write status regarding write operations at the storage circuitry and transmit circuitry transmits an outgoing write status to the request node based on the incoming write status.

Abstract: An electronic device comprising a nonvolatile memory, a memory controller configured to control the nonvolatile memory, and a host connected to the memory controller. In response to a first write signal received from the host, the memory controller is configured to provide the first write signal to the nonvolatile memory, the nonvolatile memory is configured to perform a write operation based on the provided first write signal, generate first metadata based on a result of performing the write operation, and provide the generated first metadata to the host. The host is configured to determine whether to perform garbage collection for the nonvolatile memory using a neural network model trained based on the provided first metadata or the first write signal, provide a garbage collection request signal to the memory controller in response to determining to perform garbage collection.

Abstract: The present technology relates to an electronic device. A memory device having improved memory block management performance according to the present technology includes a memory block, a peripheral circuit, and a control logic. The peripheral circuit performs a read operation and a program operation on a selected physical page among a plurality of physical pages. The control logic controls the peripheral circuit to read first logical page data stored in a first physical page and second logical page data stored in a second physical page among the plurality of physical pages, and additionally program the second logical page data into the first physical page using the read first and second logical page data.

Abstract: A method for execution by a dispersed storage network (DSN) managing unit includes receiving access information from a plurality of distributed storage and task (DST) processing units via a network. Cache memory utilization data is generated based on the access information. Configuration instructions are generated for transmission via the network to the plurality of DST processing units based on the cache memory utilization data.

Abstract: In some examples, fabric driven NVMe subsystem zoning may include receiving, from a non-volatile memory express (NVMe) Name Server (NNS), a zoning specification that includes an indication of a host that is to communicate with a given NVMe subsystem of an NVMe storage domain. Based on the zoning specification, the host may be designated as being permitted to connect to the given NVMe subsystem of the NVMe storage domain. An NVMe connect command may be received from the host. Based on the designation and an analysis of the NVMe connect command, a connection may be established between the given NVMe subsystem of the NVMe storage domain and the host.

Abstract: An approach is provided for providing optimized identification of duplicate data in a networked computing environment. An aggregate feature vector is created that is specific to an attribute of the data (e.g., a field that holds specific informational content). The aggregate feature vector has a set of dimensions that each define a specific comparison function used to test for similarity between data entries in the attribute. Each dimension in the aggregate feature vector is assigned an effectiveness, and a cost is computed for each dimension. Based on these two, a subset of dimensions is selected to form an optimized feature vector. This optimized feature vector can then be used to analyze a dataset to find matching data.

Abstract: A memory device as provided may apply a pulse amplitude modulation method to data (DQ) signal transmission/reception and may scale a DQ signal according to an operating frequency condition, so as to improve data transmission performance and effectively improve power consumption. The memory device includes a memory cell array, and a data input/output circuit configured to scale a DQ signal that includes data read from the memory cell array and output the scaled DQ signal. The data input/output circuit is configured to scale the DQ signal based on an n-level pulse amplitude modulation (PAMn) (where n is 4 or a greater integer) with a DQ parameter that corresponds an operating frequency condition and output the DQ signal. Other aspects include memory controllers that communicate with the memory devices, and memory systems that include the memory devices and memory controllers.