Abstract: A processing device determines a duration for executing a portion of an erase operation based on a plurality of execution times of erase operations performed on a memory device. The processing device executes the portion of the erase operation. Responsive to detecting expiration of the duration for executing the erase operation, the processing logic executes an erase suspend operation to suspend the erase operation. Responsive to detecting completion of the erase suspend operation, the processing logic executes one or more commands. The processing device further executes an erase resume operation to resume the erase operation on the memory device.

Abstract: The present disclosure includes apparatuses and methods for buffer reset commands for write buffers. An example apparatus includes a memory and a controller coupled to the memory. The memory can include an array of resistance variable memory cells configured to store data corresponding to a managed unit across multiple partitions each having a respective write buffer corresponding thereto. The controller can be configured to update the managed unit by providing, to the memory, a write buffer reset command followed by a write command. The memory can be configured to execute the write buffer reset command to place the write buffers in a reset state. The memory can be further configured to execute the write command to modify the content of the write buffers based on data corresponding to the write command and write the modified content of the write buffers to an updated location in the array.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for allocating cache resources according to page-level attribute values. In one implementation, the system includes one or more integrated client devices and a cache. Each client device is configured to generate at least a memory request. Each memory request has a respective physical address and a respective page descriptor of a page to which the physical address belongs. The cache is configured to cache memory requests for each of the one or more integrated client devices. The cache comprises a cache memory having multiple ways. The cache is configured to distinguish different memory requests using page-level attributes of respective page descriptors of the memory requests, and to allocate different portions of the cache memory to different respective memory requests.

Abstract: Systems and method are provided for operating a multi-array memory that includes a left memory array and a right memory array of a memory bank. A command is received at memory input pins. A signal representative of the command is propagated to an array control inhibitor. An array inhibit command is received on one or more other pins of the memory and provided to the array control inhibitor. The array control inhibitor is used to prevent arrival of the command to one of the left memory array and the right memory array based on the array inhibit command.

Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device can determine a data rate from a first sensor and a data rate from a second sensor. The processing device can write a first set of data received from the first sensor at a first logical block address (LBA) in the memory device. The processing device can write a second set of data received from the second sensor and subsequent to the first set of data at a second LBA in the memory device. The processing device can remap the first LBA and the second LBA to be logically sequential LBAs. The second LBA can be associated with an offset from the first LBA and the offset can correspond to a data rate of the first sensor.

Abstract: A storage operation suspend system includes a chassis having a storage operation suspend subsystem coupled to a communication system and a storage subsystem in the chassis. The storage operation suspend subsystem performs a first storage operation on a storage die in the storage subsystem, receives a second storage operation instruction via the communication system to perform a second storage operation on the storage die, determines that the second storage operation is a higher priority operation than the first storage operation, determines that a first power amount available in a power budget and a second power amount allocated from the power budget to the first storage operation is sufficient to perform the second storage operation when the first storage operation is suspended and, in response, suspends the first storage operation and performs the second storage operation and, following completion of the second storage operation, resumes performance of the first storage operation.

Abstract: A data storage device and method for host buffer management are provided. In one embodiment, a data storage device is provided comprising a non-volatile memory and a controller. The controller is configured to receive a read command from a host; read data from the non-volatile memory; identify a location in a host memory buffer (HMB) in the host that is available to store the data; write the data to the location in the HMB; and inform the host of the location in the HMB that stores the data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: An apparatus includes a processor, a memory communicatively coupled to the processor, an acceleration framework circuit communicatively coupled to the memory and the processor, and a device driver. The device driver is configured to receive a request for data manipulation by a software defined storage (SDS) application. The device driver is configured to determine whether the request for data manipulation can be offloaded from the processor to the acceleration framework circuit. The device driver is configured to, based upon the determination of whether the request for data manipulation can be offloaded from the processor to the acceleration framework circuit, selectively cause the request to be executed by the acceleration framework circuit or the SDS application through execution on the processor.

Abstract: A memory device includes a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic performs a plurality of asynchronous memory access operations on the plurality of memory planes, detects an occurrence of an asynchronous interrupt event, and initiates a termination procedure for each of the plurality of asynchronous memory access operations to permit each of the plurality of asynchronous memory access operations to end at different times. In response to a first memory access operation of the plurality of asynchronous memory access operations ending, the control logic asserts a command result signal, wherein the command result signal is de-asserted automatically in response to receipt of a subsequent memory access command directed to any of the plurality of memory planes, and asserts a persistent event register signal, wherein the command result signal is de-asserted in response to receipt of a clear event register command.

Abstract: A method may include, in an operating system of an information handling system: responsive to a determination that a storage resource of the information handling system is experiencing a predictor of a failure of the storage resource, issuing a command to the storage resource to reload firmware code of the storage resource; responsive to the storage resource reloading the firmware code and reset of the storage resource following reloading of the firmware code, determining whether the predictor persists; and responsive to determining whether the predictor persists, performing a responsive action.

Abstract: An information handling system may include at least one processor; a network interface; and a physical storage resource including a flash translation layer (FTL) operable to provide a mapping between logical storage addresses and physical storage addresses. The information handling system may be configured to: receive a request for a snapshot; for used portions of the physical storage resource, change a metadata identifier from a used status to a snapshot status; prevent deletion of those portions associated with the snapshot status; and transmit, via the network interface, information associated with the portions that are associated with the snapshot status.

Abstract: A degree of fragmentation is determined based on a number of holes present in a storage system layout or a portion of a layout. Edges between the holes and used portions of the storage system are tabulated by scanning a storage space. The occurrences of a pattern of used/available allocation units and/or the occurrences of another pattern available/used allocation units are recognized. A fragmentation value is calculated based on occurrences of the patterns in view of the total storage space. The present fragmentation measurement system utilizes the number of occurrences of the holes in assessing fragmentation.

Abstract: Methods, computer program products, computer systems, and the like for efficient metadata management are disclosed, which can include determining whether a change in a status of data has occurred. In response to a determination that the change has occurred, such methods, computer program products, and computer systems can include determining whether a move condition has been met, and, in response to a determination that the move condition has been met, moving the metadata from the first storage unit to a second storage unit.

Abstract: Disclosed herein are system, method, and computer program product aspects for managing a storage system. In an aspect, a host device may generate a configuration corresponding to a file and transmit the configuration to a memory device, such as 3D NAND memory. The configuration instructs the memory device to refrain from transmitting a logic-to-physical (L2P) dirty entry notification to the host device. The L2P dirty entry notification corresponds to the file. The host device may also generate a second configuration corresponding to the file and transmit the second configuration to the memory device. The second configuration instructs the memory device to resume transmitting the L2P dirty entry notification corresponding to the file to the host device.

Abstract: A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.

Abstract: Systems and methods for verifying firmware before it is loaded to a memory device are presented herein. An amount of available memory remaining in a memory device after firmware is written to the memory device is determined, and padding data having a size equal to the determined amount of remaining available memory is generated and appended to the firmware (e.g., the firmware is padded with the padding data). In this way, there is no room for malicious code or a malicious version of the firmware in the memory device. A processing device may determine a verification value of the padded firmware and store the verification value. The verification value may be a cryptographic hash of the padded firmware or a cryptographic signature of the padded firmware. The padded firmware is then written to the memory device. The firmware may be read from the memory device and verified using the verification value.

Abstract: The present disclosure is related to methods, systems, and machine-readable media for managing extent sharing between snapshots using mapping addresses. A first mapping address can be assigned to a first extent responsive to a request to write the first extent. A second mapping address can be assigned to a second extent responsive to a request to write the second extent. A snapshot can be created. A snapshot mapping address, that is monotonically increased from the second mapping address, can be assigned to the snapshot. A third mapping address, that is monotonically increased from the second mapping address, can be assigned to a third extent of the snapshot responsive to a request to write the third extent.

Abstract: The present disclosure is to optimize processes in a storage system. A storage system includes: a first controller including a first computing device and a first memory; a second controller including a second computing device and a second memory; and an interface circuit that transfers data between the first controller and the second controller. The interface circuit reads first compressed data from the second memory. The interface circuit decompresses the first compressed data to generate first uncompressed data, and writes the first uncompressed data into the first memory.

Abstract: A memory system includes a memory; and a memory controller which includes a spare buffer suitable for storing an error location in the memory and data at the location, and commands the memory to perform a spare read operation when a read operation needs to be performed in a region of the memory including the error location.

Abstract: A method and apparatus for performing access control of a memory device with aid of multi-stage garbage collection (GC) management are provided. The method includes: during a first GC stage, sending a first simple read command to the NV memory in order to try reading first valid data from a first source block, sending the first valid data into an internal buffer of the NV memory, for being programed into a first destination block, sending a second simple read command to the NV memory in order to try reading second valid data from the first source block, and in response to reading the second valid data from the first source block being unsuccessful, preventing retrying reading the second valid data from the first source block; completing at least one host-triggered operation; and during a second GC stage, retrying reading the second valid data from the first source block.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for allocating cache resources according to page-level attribute values. In one implementation, the system includes one or more integrated client devices and a cache. Each client device is configured to generate at least a memory request. Each memory request has a respective physical address and a respective page descriptor of a page to which the physical address belongs. The cache is configured to cache memory requests for each of the one or more integrated client devices. The cache comprises a cache memory having multiple ways. The cache is configured to distinguish different memory requests using page-level attributes of respective page descriptors of the memory requests, and to allocate different portions of the cache memory to different respective memory requests.

Abstract: Solid State Drive devices with hardware accelerators and methods for apportioning storage resources with tokens in the SSD are disclosed. SSDs typically comprise an array of non-volatile memory devices and a controller which manages access to the memory devices. The controller may also comprise one or more accelerators to either improve the performance of the SSD itself or to offload specialized computation workloads of a host-computing device. Different accelerators may be dynamically assigned portions of the non-volatile memory array according to the type of data being accessed and/or the throughput required. Provision is also made for the data to be accessed directly by the accelerators bypassing the controller. The accelerators may also share data bus bandwidth and resources with each other or the storage device controller. To minimize conflicts and improve the storage device performance, a system of tokens for both cache memory and bus bandwidth is used to dynamically assign these resources.

Abstract: Systems and methods are disclosed for providing utilization of device resources based on host assisted grouping of applications. In certain embodiments, a data storage device includes a non-volatile memory, a volatile memory, and a controller configured to: receive application group information associated with applications from a host, wherein the application group information indicates corresponding application groups for the applications on the host; receive a plurality of write requests associated with a plurality of applications from the host, wherein the plurality of applications is included in the same application group; write data for each write request of the plurality of write requests in parallel across a plurality of channels associated with a plurality of dies in the non-volatile memory such that the data for the plurality of write requests share a parity buffer; and generate parity data for the data for the plurality of write requests.

Abstract: According to one embodiment, a memory system includes a memory controller configured to send a first command set including arithmetic operation target data and an address that designates a memory cell to store weight data; and a nonvolatile semiconductor memory configured to receive the first command set from the memory controller, read the weight data from the memory cell designated by the address, perform an arithmetic operation based on the arithmetic operation target data and the weight data, and send arithmetic operation result data to the memory controller.

Abstract: A memory sub-system configured to manage programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system. The memory sub-system counts single-page transitions of atomic programming modes performed within a memory sub-system and determines whether or not to allow any two-page transition of atomic programming modes based on whether an odd or even number of the single-page transitions have been counted. When an odd number of the transitions have been counted, no two-page transition is allowed; otherwise, one or more two-page transitions are allowable. A next transition of atomic programming modes is selected based on the determining of whether or not to allow any two-page transitions.

Abstract: Methods and systems for a networked storage system is provided. One method includes transforming by a processor, performance parameters associated with storage volumes of a storage system for representing each storage volume as a data point in a parametric space; generating by the processor, a plurality of bins in the parametric space using the transformed performance parameters; adjusting by the processor, bin boundaries for the plurality of bins for defining a plurality of service levels for the storage system based on the performance parameters; and using the defined plurality of service levels for operating the storage system.

Abstract: Methods, systems, and devices for memory can include techniques for identifying first quantities of write counts for a first plurality of super management units (SMUs) in a mapped region of a memory sub-system, identifying, by a hardware component of the memory sub-system, a first SMU of the first plurality that includes a fewest quantity of write counts of the first quantity of write counts, and performing a wear-leveling operation based at least in part on a first quantity of write counts of the first SMU of the first plurality in the mapped region being less than a second quantity of writes counts of a second SMU of a second plurality of SMUs in an unmapped region of the memory sub-system.

Abstract: Provided is a genome data compression method of compressing FASTQ-formatted genome data, the method including: storing, by a first core that is one of the M cores, fixed header data in the first line of the first piece of sequence data in a compression result storage; and allocating, by the first core, N (N is a natural number of 2 or greater) pieces of the sequence data to each of the other M-1 (M is a natural number of 4 or greater) cores (hereinafter, referred to as “the remaining cores”), and performing compression by each of the remaining cores to compress N*(M-1) pieces of the sequence data together in parallel processing, and storing a compression result in the compression result storage, wherein the compression performed by each of the remaining cores is performed, including: primary compression in which for the N pieces of the sequence data, a process of the following stages for each piece of the sequence data is repeated: a stage in which a fixed header in the first line is removed; a stage in which

Abstract: A server system is provided that includes one or more compute nodes that include at least one processor and a host memory device. The server system further includes a plurality of solid-state drive (SSD) devices, a local non-volatile memory express virtualization (LNV) device, and a non-transparent (NT) switch for a peripheral component interconnect express (PCIe) bus that interconnects the plurality of SSD devices and the LNV device to the at least one processor of each compute node. The LNV device is configured to virtualize hardware resources of the plurality of SSD devices. The plurality of SSD devices are configured to directly access data buffers of the host memory device. The NT switch is configured to hide the plurality of SSD devices such that the plurality of SSD devices are not visible to the at least one processor of each compute node.

Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums that provide for techniques for scrambling and/or updating meta-data that enable an efficient internal copyback operation. In some examples, in order to update the meta-data, the meta-data and host-data are separated and the only the meta-data is sent to the controller to be updated during a modified internal copyback operation. The host-data is not transmitted to the controller. While sending the meta-data utilizes resources of the communication link between the memory dies and the controller, it uses much fewer resources than if the host-data were also transmitted.

Abstract: According to one embodiment, a controller of a memory system executes a first write operation of writing write data into a first storage region, in response to reception of one or more write requests for specifying a first zone from a host, during a period from execution of an erase operation of the first storage region until a first time elapses. When the first time has elapsed after execution of the erase operation, in a state in which an unwritten region having a size larger than or equal to a first size remains in the first storage region, the controller does not execute the first write operation, allocates the first storage region as a nonvolatile buffer capable of temporarily storing write data to be written to each of a plurality of zones.

Abstract: Embodiments provide a scheme for estimating an optimal read threshold voltage using a deep neural network (DNN) with reduced number of processing. A controller receives first and second program voltage (PV) levels associated with read operations on cells. The controller estimates first and second probability distribution parameter sets representing skew normal distributions of the first and second PV levels, respectively. The controller estimates an optimal read threshold voltage based on the first and second probability distribution parameter sets. The optimal read threshold voltage is a read threshold voltage such that first probability density function (PDF) value of the skew normal distribution of the first PV level is the same as the second PDF value of the skew normal distribution of the second PV level.

Abstract: Methods, systems, and devices for reduced pin status register are described. An apparatus may include a first memory die and a second memory die each coupled with a data bus. The apparatus may further include a controller coupled with the first memory die and the second memory die via the data bus that is configured to transmit a first command associated with a first operation to the first memory die and a second command associated with a second operation to the second memory die. The controller may further transmit a third command concurrently to the first memory die and the second memory die, the third command requesting a first status of the first operation and a second status of the second operation. The controller may receive the first status and the second status concurrently via the data bus from the first memory die and the second memory die.

Abstract: Methods, systems, and devices for providing for trust during startup of an information handling system (IHS) are disclosed. When an IHS starts up, data may be read into memory and used by a processor of the IHS to begin execution of a startup management entity that places the IHS into a desired operating system. To reduce the likelihood of the data used for IHS startup causing the IHS to enter an undesired state (e.g., due to data corruption or intentional action), the data may be verified prior to be being read into memory. If the data is unverifiable, then corrective action may be taken.

Abstract: Apparatuses and methods can be related to implementing edge compute components in a memory array. Compute components can be implemented under a memory array. Implementing compute components under a memory array can limit control access to the compute components due to die space utilized by the compute components. A portion of the compute components (e.g., compute components on the edge) may have control access that is not available to the remainder of the compute components.

Abstract: Aspects of the present disclosure relate to data cache management. In embodiments, a logical block address (LBA) bucket is established with at least one logical LBA group. Additionally, at least one LBA group is associated with two or more distinctly sized cache slots based on an input/output (IO) workload received by the storage array. Further, the association includes binding the two or more distinctly sized cache slots with at least one LBA group and mapping the bound distinctly sized cache slots in a searchable data structure. Furthermore, the searchable data structure identifies relationships between slot pointers and key metadata.

Abstract: An embodiment may involve obtaining an image composed of color channels, wherein each of the color channels represents colors therein with n bits per pixel; quantizing each of the color channels to be represented by m bits per pixel; using a space-filling curve to convert each of the color channels as quantized into respective vectors; generating, for each of the respective vectors, a respective set of m arrays, wherein the m arrays for a particular vector of the respective vectors contain indices of where a fixed value selected from a range of 0 to m?1 is found in the particular vector; applying, to each of the m arrays for each of the respective vectors, differential encoding and compression of the indices therein; mapping each of the m arrays for each of the respective vectors to blocks of nucleotides; synthesizing the blocks; and storing, in a DNA-based storage medium, the blocks.

Abstract: A system stores transaction data in a ring chain architecture. A ring chain comprises blocks of data stored as a length-limited block chain in a ring buffer configuration. A block of transactions is stored on a ring chain until enough new blocks are added to overwrite the ring buffer with new blocks. The system stores multiple ring chains that update at varying frequencies. A new block on a lower frequency ring chain stores an aggregation of data from the blocks that were added to a higher frequency ring chain in the time since the previous addition of a block to the lower frequency ring chain. Thus, a system of ring chains stores progressively summarized state transition data over progressively longer time intervals while maintaining immutability of the record and reducing storage requirements.

Abstract: Delaying deletion of a dataset, including: associating an eradication timer with the dataset, wherein the eradication timer specifies an amount of time to delay a requested deletion of the dataset; determining that the amount of time to delay the requested deletion of the dataset should be modified; and modifying the eradication timer to specify a modified amount of time to delay the requested deletion of the dataset.

Abstract: A QLC based data storage device leverages a host memory buffer (HMB) to achieve QLC direct write that increases performance of the QLC data storage device and reducing or eliminating disadvantages associated with a QLC folding approach. In one example, the QLC based data storage device includes a controller configured to receive a request to write data to a non-volatile memory, determine whether the request is a sequential write operation, determine whether a HMB of the data storage device is enabled, determine whether a HMB allocation is successful for a quad-level cell direct write, and responsive to determining that the request is not the sequential write operation, the HMB of the data storage device is enabled, and the HMB allocation is successful for the quad-level cell direct write, perform a direct write operation in a quad-level cell block of the non-volatile memory.

Abstract: A memory system is provided. The memory system includes a memory controller and a data bus electrically coupled to the memory controller. The memory system further includes one or more memory devices communicatively coupled to the memory controller via the data bus, wherein the memory controller is configured to derive a read profile for each of the one or more memory devices to account for a time propagation delay of data being sent via the data bus during read operations of the one or more memory devices.

Abstract: A computer storage device having: a host interface; a controller; non-volatile storage media having memory units of different types and having different program erase budgets; and firmware. The firmware instructs the controller to: generate an address map mapping logical addresses to physical addresses of the memory units the different types; and adjust the address map based at least in part on the program erase budgets to level wear across the memory units of the different types.

Abstract: Systems, apparatuses, and methods related to media management, including “garbage collection,” in memory or storage systems or sub-systems, such as solid state drives, are described. For example, a battery state associated with the memory system or sub-system may be used as an indicator or basis for managing a garbage collection operation on a data block. A controller or the system or sub-system may determine that a battery state or condition satisfies a criterion. Based on determining that the criterion is satisfied the, the garbage collection operation may be postponed until the battery state changes to satisfy a different battery condition.

Abstract: According to one embodiment, a memory system receives from a host a first write request including a first block identifier designating a first write destination block to which first write data is to be written. The memory system acquires the first write data from a write buffer temporarily holding write data corresponding to each of the write requests, and writes the first write data to a write destination page in the first write destination block. The memory system releases a region in the write buffer, storing data which is made readable from the first write destination block by writ the first write data to the write destination page. The data made readable is a data of a page in the first write destination block preceding the write destination page.

Abstract: In certain aspects, a memory device includes an array of memory cells, an input/output (I/O) circuit, and control logic coupled to the I/O circuit. The array of memory cells includes N main banks and M redundant banks, where each of N and M is a positive integer, and N is great than M. The I/O circuit is coupled to the N main banks and the M redundant banks and configured to direct N pieces of data to or from N working banks, respectively. The control circuit is configured to determine the N working banks from the N main banks and the M redundant banks based on bank fail information indicative of K failed main banks of the N main banks. The N working banks include K redundant banks of the M redundant banks, where K is a positive integer not greater than M. The control circuit is further configured to control the I/O circuit to direct K pieces of data of the N pieces of data to or from the K redundant banks, respectively.

Abstract: Embodiments of the present disclosure include a digital circuit and method for multi-stage compression. Digital data values are compressed using a multi-stage compression algorithm and stored in a memory. A decompression circuit receives the values and performs a partial decompression. The partially compressed values are provided to a processor, which performs the final decompression. In one embodiment, a vector of N length compressed values are decompressed using a first bit mask into two N length sets having non-zero values. The two N length sets are further decompressed using two M length bit masks into M length sparse vectors, each having non-zero values.

Abstract: A data storage device, in one implementation, includes a memory device having Single Level Cell (SLC) blocks and Multi-Level Cell (MLC) blocks, such as Triple Level Cell (TLC) blocks. If a SLC block is determined to have errors, the SLC block is reallocated as a TLC block. In some implementations, the TLC block is used to store TLC cold data.

Abstract: A memory system identifies, in a logical to physical (L2P) journal associated with a memory device, a first journal entry reflecting a two pass programming operation, where the two pass programming operation includes a first pass to program data to a second memory location identified by a second physical address and a second pass to program a same data to a same second memory location identified by a same second physical address. The system determines whether the second pass of the two pass programming operation is complete. Responsive to determining that the second pass of the two pass programming operation is complete, the system causes a second journal entry of the L2P journal to reference from a first physical address to the second physical address. The system reconstructs the L2P table based on the second journal entry.

Abstract: A memory sub-system configured to dynamically determine input/output sizes of write commands based on a media physical layout of a memory sub-system. The memory sub-system can identify, dynamically in response to write commands being selected for execution in media units of the memory sub-system, a portion of a media layout that maps from logical addresses identified by the write commands in the logical address space to physical addresses of memory units in the media units. Based on the media layout, an input/output size for a next write command is identified and transmitted to the host system in a response. The host system generates the next write command and configures the amount of data to be written through the next write command based on based on the input/output size identified in the response.

Abstract: A storage system includes a NAND storage media and a nonvolatile storage media as a write buffer for the NAND storage media. The write buffer is partitioned, where the partitions are to buffer write data based on a classification of a received write request. Write requests are placed in the write buffer partition with other write requests of the same classification. The partitions have a size at least equal to the size of an erase unit of the NAND storage media. The write buffer flushes a partition once it has an amount of write data equal to the size of the erase unit.