Abstract: A data writing control device includes: a determination unit that determines whether a request from a requestor is a partial-write request for data and the partial-write is continuously performed to the same address; a transmission unit that, when the request from the requestor is the partial-write request for data and the partial-write is performed to an address different from an address of the previous partial-write, transmits a read request for data to the requestor; and a hold unit that holds write data included in the partial-write request and data indicating a rewritten location of the write data until read data corresponding to the read request for the data is received.

Abstract: A storage control device includes a first rewriting section, a second rewriting section, and a first retry control section. The first rewriting section performs first rewrite to rewrite other of two binary values into a memory cell in which one of the two binary values is written. The second rewriting section performs second rewrite to rewrite the one of the two binary values into the memory cell in which the other of the two binary values is written. The first retry control section causes the memory cell that has undergone the first rewrite to be subjected to the second rewrite followed by the first rewrite again if an error occurs during the first rewrite.

Abstract: A rewriting system comprises a plurality of electronic control units mounted on a vehicle, each of the plurality of electronic control units including a storage for storing control information, and a device for sending new control information to rewrite the control information stored in the storages of the plurality of electronic control units with the new control information. One of the plurality of electronic control units is configured to make a determination whether the rewriting in the other electronic control units has been completed in response to a completion of the rewriting in the one of the plurality of electronic control units, and make a notification of a result of the determination. Thus, the progress of the rewriting for a plurality of control units is automatically determined and notified to a user. The user can immediately recognize the progress of the rewriting work.

Abstract: A non-volatile memory, such as a NAND memory, may be encrypted by reading source blocks, writing to destination blocks, and then erasing the source blocks. As part of the encryption sequence, a power fail recovery procedure, using sequence numbers, is used to reestablish a logical-to-physical translation table for the destination blocks.

Abstract: An information storage device includes a storage unit to which a storage region is assigned, a first management information storage unit that stores address information indicating an address range of the storage region in association with identification information identifying the storage region, and a processor that executes a procedure that includes acquiring the address information corresponding to the identification information from the first management information storage unit and accesses the storage region corresponding to the address information and rewriting the identification information stored in the first management information storage unit.

Abstract: In some embodiments, an apparatus includes a register having a first portion and a second portion. The first portion of the register has multiple bits and the second portion of the register has multiple bits. Each bit from the multiple bits of the first portion of the register is associated with a bit from the multiple bits of the second portion of the register such that a bit from the multiple bits of the first portion of the register is set for its associated bit from the multiple bits of the second portion of the register to be written.

Abstract: A storage control apparatus includes: a pre-processing-execution determining block for determining whether or not either one of an erase operation and a program operation is to be executed as pre-processing in a write operation to be carried out on a predetermined data area to serve as a write-operation object; and a pre-read processing block for reading out pre-read data from the data area prior to the write operation if a result of the determination indicates that the pre-processing is to be executed. The apparatus further includes a bit operating block for carrying out: the pre-processing and one of the erase and program operations which is not the pre-processing as post-processing if a result of the determination indicates that the pre-processing is to be executed; and the post-processing without carrying out the pre-processing if a determination result indicates that the pre-processing is not to be executed.

Abstract: A computer-readable, non-transitory medium storing a program for measuring a performance in a system including a storage unit and a plurality of control units for controlling an access to the storage unit, the program causing a computer to execute a procedure, the procedure includes estimating a specification area in address information including an address area in which an address of an access target of the storage unit is set and the specification area in which specification information for specifying a control unit for controlling an access to the access target is set, and verifying a reliability of the system by accessing the storage unit on the basis of a specification information in the specification area.

Abstract: According to an embodiment, a controller includes a write control unit configured to make a control that converts data requested to be written by an external device into pieces of cluster data with a size of a cluster of a storage medium, compresses each piece of cluster data, determines a corresponding physical address of a write destination in the storage medium according to a predetermined rule, and writes the compressed pieces of cluster data to the storage medium using the physical address of the write destination. The write control unit also makes a control that writes a correspondence between the physical address and a corresponding logical address to a storage unit. The controller also includes a read control unit configured to a control that reads a piece of cluster data from the storage medium using an acquired physical address, and decompresses the read piece of cluster data.

Abstract: In a storage apparatus using AW technology, deterioration in I/O performance accompanying saving of data for creating a snapshot is suppressed as much as possible. When saving a snapshot image after returning a write completion response to a host computer, a storage apparatus according to the present invention performs the saving preferentially for a storage area with a low priority of snapshot image deletion.

Abstract: A method, apparatus, and system of a software technique for improving disk write performance on raid system where write sizes are not an integral multiple of number of data disks are disclosed. In one embodiment, a method includes configuring a queue module to place an amount of data of a write operation into a data buffer module associated with a memory system if writing the amount of data to the memory system would generate a read-modify-write operation to occur, using the data buffer module to temporarily store the amount of data, writing the amount of data from the data buffer module to the memory system. The method may include algorithmically determining the amount of data to place in the data buffer module as a portion of the write operation that may cross a boundary between a striped sector unit (SSU) and/or an other SSU.

Abstract: A system and method for generating a triage dump of useful memory data from a computer that encounters an error while executing one or more software programs. The computer system may identify data values within the triage dump that are characteristic of personal data. To protect the privacy of the software user the personal data may be poisoned by overwriting the data values with overwrite values. The overwrite values used to poison the data values may be predetermined, based on the data values themselves, or chosen at random. The triage dump may be sent to an external server to associated with the developer of the one or more software programs for analysis. When overwrite values are dynamically selected, the specific overwrite values used may be sent to the server in connection with a triage dump.

Abstract: A cache memory apparatus includes an L1 cache memory, an L2 cache memory coupled to the L1 cache memory, an arithmetic logic unit (ALU) within the L2 cache memory, the combined ALU and L2 cache memory being configured to perform therewithin at least one of: an arithmetic operation, a logical bit mask operation; the cache memory apparatus being further configured to interact with at least one processor such that atomic memory operations bypass the L1 cache memory and go directly to the L2 cache memory.

Abstract: An apparatus includes an input/output (I/O) interface configured to couple a controller to an I/O buffer of a memory device. The controller includes an erase module coupled to the I/O interface. The erase module is configured to issue an instruction to the memory device to erase data from the memory device. The controller includes an erase suspend module coupled to the I/O interface. The erase suspend module is configured to determine that an erase operation executing within the electronic memory device satisfies a suspend policy in response to receiving a memory access request to perform an operation on the memory device on which the erase operation is executing. The erase suspend module is further configured to issue a suspend command to the memory device to suspend the erase operation.

Abstract: A technique for efficiently boosting the priority of a preemptable data reader while resolving races between the priority boosting and the reader exiting a critical section or terminating in order to eliminate impediments to grace period processing that defers the destruction of one or more shared data elements that may be referenced by the reader until the reader is no longer capable of referencing the one or more data elements. A determination is made that the reader is in a read-side critical section and the reader is designated as a candidate for priority boosting. A verification is made that the reader has not exited its critical section or terminated, and the reader's priority is boosted to expedite its completion of the critical section. The reader's priority is decreased following its completion of the critical section.

Abstract: When a thread begins an atomic transaction, the thread reads one or more variables from one or more source addresses. The read portion of the transaction is constrained to a predetermined amount of time or number of cycles (N). The mechanism then performs a test and set operation to determine whether any other threads hold locks on the one or more source addresses. If the locks for the one or more source addresses are free, then the thread acquires locks on the one or more source addresses. The thread then performs work and updates the one or more variables. Thereafter, the mechanism delays for an amount of time or number of cycles greater than or equal to N before releasing the locks. If another thread attempts to acquire a lock on the one or more source addresses, then the test and set operation for that other thread will fail.

Abstract: Described herein are method and apparatus for performing wear leveling of erase-units of an LLRRM device that considers all active erase-units. Wear counts of all active erase-units (containing client data) and free erase-units (not containing client data) are tracked. Wear counts are used to determine low-wear active erase-units having relatively low wear counts and high-wear free erase-units having relatively high wear counts. In some embodiments, data contents of low-wear active erase-units are transferred to high-wear free erase-units, whereby the low-wear active erase-units are converted to free erase-units and may later store different client data which may increase the current rate of wear for the erase-unit. The high-wear free erase-units are converted to active erase-units that store client data that is infrequently erased/written, which may reduce the current rate of wear for the erase-unit. As such, wear is spread more evenly among erase-units of the LLRRM device.

Abstract: A method, computer management apparatus, and computer program product are provided for processing data stored on a sequential storage media within a computational computing environment. A block reference table and most often read blocks are loaded from a modified tape format of a sequential storage media into an internal memory of a sequential storage media device. During write command processing, a data deduplication procedure is performed using a modified block reference table. It is determined if entries from the block reference table must be deleted and responsive to this identifying and deleting host block and device block entries from the block reference table.

Abstract: A first and a second physical disk identifier, a physical Logical Block Address (LBA), a data length, and a span identifier are calculated from a data write operation. A first request command frame is created for retrieving the existing data block from the storage array, the first request command frame including at least one of the calculated parameters. At least one second request command frame is created for retrieving the at least one existing parity data block from the storage array, the at least one second request command frame including the calculated at least one second physical disk identifier and at least one of the calculated parameters. At least one new parity data block is calculated utilizing the existing data block, the new data block, and the at least one existing parity data block.

Abstract: A write DMA includes a write unit, a read unit and a parity generation unit. The read unit reads parity data from one of two NAND flashes storing the parity data therein. The parity generation unit generates parity data based on the read parity data and a plurality of stripes obtained by dividing user data. The write unit writes a stripe into any of a plurality of NAND flashes storing stripes therein, and writes generated parity data into the other NAND flash from which parity data is not read.

Abstract: A system includes a host device that may be configured to initiate memory requests to a system memory. The system also includes a memory controller that may be configured receive the memory requests and to format the memory requests into memory transactions that are conveyed to the memory device via a memory interface. The memory transactions include a plurality of memory write command types. Each memory write command type corresponds to a different respective schedule for conveying a corresponding data payload.

Abstract: The technique introduced here involves using a block address and a corresponding generation number as a “fingerprint” to uniquely identify a sequence of data within a given storage domain. Each block address has an associated generation number which indicates the number of times that data at that block address has been modified. This technique can be employed, for example, to maintain cache coherency among multiple storage nodes. It can also be employed to avoid sending the data to a network node over a network if it already has the data.

Abstract: According to one embodiment, a memory architecture implemented method is provided, where the memory architecture includes a logic chip and one or more memory chips on a single die, and where the method comprises: reading values of data from the one or more memory chips to the logic chip, where the one or more memory chips and the logic chip are on a single die; modifying, via the logic chip on the single die, the values of data; and writing, from the logic chip to the one or more memory chips, the modified values of data.

Abstract: A method for operating a memory system and a memory buffer device. The method includes receiving an external clock signal from a clock device of a CPU of a host computer to a buffer device, and receiving an ODT signal from the CPU to a command port of the buffer device. Buffer device provides the self-termination information internally to the common data bus by automatically detecting the read or write command on the common command bus and adjust the termination resistor array in a pre-determined value and timing fashion so that information can be read from or write to a data line of only one of the plurality of DIMM devices coupled together through a common data bus interface. All DIMM devices other than the DIMM device being read can be maintained in a termination state to prevent any signal from traversing to the common the common data bus interface.

Abstract: A disk drive receives a request to write at least one block of a first block size, wherein the disk drive is configured to store blocks of a second block size that is larger in size than the first block size. The disk drive stores a plurality of emulated blocks of the first block size in each block of the second block size. The disk drive generates a read error, in response to reading a selected block of the second block size in which the at least block of the first block size is to be written via an emulation. The disk drive performs a destructive write of selected emulated blocks of the first block size that caused the read error to be generated. The disk drive writes the at least one block of the first block size in the selected block of the second block size.

Abstract: Systems and methods for synchronizing thread wavefronts and associated events are disclosed. According to an embodiment, a method for synchronizing one or more thread wavefronts and associated events includes inserting a first event associated with a first data output from a first thread wavefront into an event synchronizer. The event synchronizer is configured to release the first event before releasing events inserted subsequent to the first event. The method further includes releasing the first event from the event synchronizer after the first data is stored in the memory. Corresponding system and computer readable medium embodiments are also disclosed.

Abstract: Some of the embodiments of the present disclosure provide an apparatus comprising a command cancellation channel (CCC) including a plurality of stages, the CCC configured to receive a first memory address of a sequence of memory addresses and a corresponding first modification command, determine that at least a first stage of the plurality of stages includes the first memory address and a corresponding second modification command, and erase the first memory address or cancel the second modification command while shifting the first memory address and the second modification command from the first stage to a second stage. Other embodiments are also described and claimed.

Abstract: A method for managing an amount of IO requests transmitted from a host computer to a storage system is described. A current latency value of an IO request most recently removed from an issue queue maintained by the host computer in order to transmit IO requests from the host computer to the storage system is periodically determined. An average latency value is the calculated based on the current latency value and a size limit of the issue queue is adjusted based in part on the average latency value. Upon receiving an IO request from one of a plurality of client applications running on the host computer, it can then be determined whether a number of pending IO requests in the issue queue has reached the size limit and the IO request can be transmitted to the issue queue if the number of pending IO request falls within the size limit.

Abstract: A computing apparatus for reducing the amount of processing in a network computing system which includes a network system device of a receiving node for receiving electronic messages comprising data. The electronic messages are transmitted from a sending node. The network system device determines when more data of a specific electronic message is being transmitted. A memory device stores the electronic message data and communicating with the network system device. A memory subsystem communicates with the memory device. The memory subsystem stores a portion of the electronic message when more data of the specific message will be received, and the buffer combines the portion with later received data and moves the data to the memory device for accessible storage.

Abstract: An electronic circuit (200) for use with an accessing circuit (110) that supplies a given address and a partial write data portion and also has dummy cycles. The electronic circuit (200) includes a memory circuit (230) accessible at addresses, an address buffer (410), a data buffer (440) coupled to the memory circuit (230), and a control circuit (246) operable in the dummy cycles to read data from the memory circuit (230) to the data buffer (440) from a next address location in the memory circuit (230) and to store that next address in the address buffer (410).

Abstract: A memory interface system can include a memory controller configured to operate at a first operating frequency. A physical interface block can be coupled to the memory controller. The physical interface block can be configured to communicate with the memory controller at the first operating frequency and communicate with a memory device at a second operating frequency that is independent of the first operating frequency.

Abstract: Disclosed is a method for protecting sensitive data in a storage device having wear leveling. In the method, a write command, with an associated sensitive write signal indicating that sensitive data is associated with the write command, is received. The sensitive data is further associated with at least one address pointing to a storage location within an initial physical storage block. The write command is executed by writing to at least one storage location within an available physical storage block, pointing the at least one address to the at least one storage location within the available physical storage block, and erasing the initial physical storage block to complete execution of the write command.

Abstract: A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command.

Abstract: A storage device is provided for direct memory access. A controller of the storage device performs a mapping of a window of memory addresses to a logical block addressing (LBA) range of the storage device. Responsive to receiving from a host a write request specifying a write address within the window of memory addresses, the controller initializes a first memory butler in the storage device and associates the first memory buffer with a first address range within the window of memory addresses such that the write address of the request is within the first address range. The controller writes to the first memory buffer based on the write address. Responsive to the buffer being full, the controller persists contents of the first memory buffer to the storage device using logical block addressing based on the mapping.

Abstract: One embodiment of the invention sets forth a CROP configured to perform both color raster operations and atomic transactions. Upon receiving an atomic transaction, the distribution unit within the CROP transmits a read request to the L2 cache for retrieving the destination operand. The distribution unit also transmits the source operands and the operation code to the latency buffer for storage until the destination operand is retrieved from the L2 cache. The processing pipeline transmits the operation code, the source and destination operands and an atomic flag to the blend unit for processing. The blend unit performs the atomic transaction on the source and destination operands based on the operation code and returns the result of the atomic transaction to the processing pipeline for storage in the internal cache. The processing pipeline writes the result of the atomic transaction to the L2 cache for storage at the memory location associated with the atomic transaction.

Abstract: A network device may operate to increase application performance over a wide area network. In one particular implementation, the network device may monitor accesses to a disk drive from entities and determine whether an entity is accessing the disk drive in a manner that causes a disproportionate amount of performance degradation. If so, the network device may throttle access to the disk drive for the entity.

Abstract: In some embodiments, a file management unit located in the operating system detects a write operation that writes the data blocks within the consistency snapshot (in main memory) to the persistent storage. The file management unit can then determine that all transactions have been completed before the write operation begins. In some instances, the file management unit then attempts to write the data blocks within the consistency snapshot to the persistent storage. The file management unit can then receive a notification that the write operation did not successfully write the data blocks from the consistency snapshot to the persistent storage. In some embodiments, the write operation is not successful because there are fewer free data blocks in the persistent storage than needed for writing the data blocks within the consistency snapshot to persistent storage. The file management can then wait a period of time.

Abstract: A method, apparatus, and system of presentation of a read-only clone Logical Unit Number (LUN) to a host device as a snapshot of a parent LUN are disclosed. In one embodiment, a method includes generating a read-write clone LUN of a parent LUN and coalescing an identical data instance of the read-write clone LUN and the parent LUN in a data block of a volume of a storage system. A block transfer protocol layer is modified to refer the read-write clone LUN as a read-only clone LUN, according to the embodiment. Furthermore, according to the embodiment, the read-only clone LUN is presented to a host device as a snapshot of the parent LUN.

Abstract: A system and method for generating a triage dump of useful memory data from a computer that encounters an error while executing one or more software programs. The computer system may identify data values within the triage dump that are characteristic of personal data. To protect the privacy of the software user the personal data may be poisoned by overwriting the data values with overwrite values. The overwrite values used to poison the data values may be predetermined, based on the data values themselves, or chosen at random. The triage dump may be sent to an external server to associated with the developer of the one or more software programs for analysis. When overwrite values are dynamically selected, the specific overwrite values used may be sent to the server in connection with a triage dump.

Abstract: A method of managing memory, the method including extracting location information of erasure data in which file allocation information has been deleted, and performing an overwrite job on the erasure data in a memory, based on the extracted location information.

Abstract: Subject matter disclosed herein relates to performing concurrent memory operations.

Abstract: The present invention provides a write circuit, a read circuit, a memory buffer and a memory module. The write circuit includes: a data collecting unit, a first check unit, a data restoring unit, a first check data generating unit, a first adjusting unit and a write unit; the read circuit includes: a data read unit, a second check unit, an output data generating unit, a second check data generating unit, a second adjusting unit and an output unit; the memory buffer includes the write circuit and the read circuit; the memory module includes the memory buffer and multiple memory chips connected to the memory buffer. Advantages of the present invention lie in that: data can be transmitted with a memory controller in a low power consumption manner, and the data transmitted based on conversion control data can be read out of or written into a DDR4 memory chip.

Abstract: A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each of the memory devices receives at least one of the serial streams of bits from the memory controller and converts the serial stream of bits to a set of parallel bits for storage.

Abstract: Memories, buffered write command circuits, and methods for executing memory commands in a memory. In some embodiments, read commands that are received after write commands are executed internally prior to executing the earlier received write commands. Write commands are buffered so that the commands can be executed upon completion of the later received read command. One example of a buffered write command circuit includes a write command buffer to buffer write commands and propagate buffered write commands therethrough in response to a clock signal and further includes write command buffer logic. The write command buffer logic generates an active clock signal to propagate the buffered write commands through the write command buffer for execution, suspends the active clock signal in response to receiving a read command after the write command is received, and restarts the active clock upon completion of the later received read command.

Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

Abstract: In a semiconductor storage device 10 included in a liquid container 20, on reception of an encoding request for encoding readout data, a write-read controller 140 changes over the position of a switch 141 to output encoded readout data, which is obtained by an encoding operation in a data encoding circuit 150, to a data signal terminal SDAT. In the case of no reception of the encoding request for encoding the readout data, on the other hand, the write-read controller 140 changes over the position of the switch 141 to output raw data read out from a memory array 100 to the data signal terminal SDAT.

Abstract: The operation of a FIFO buffer memory includes writing the data at input to the memory in a single write location, and making the single write location available for writing an input datum with a shift of the datum written in the single write location to another location of the memory. At each operation of writing of an input datum in the single write location, there is scheduled shifting of the datum written therein to another location, without waiting for a new write request, thus eliminating the combinational constraint between the two operations.

Abstract: Memory is divided up during the gathering of histogram data so that a portion of the memory is configured for storing the high counts expected at the minimum and maximum codes/addresses, and at least one other portion is configured for storing the lower counts expected at other codes/addresses. By configuring memory portions in this manner, memory can be more efficiently allocated.

Abstract: Techniques and structures are disclosed in which memory training for DDR or other memory can be performed more rapidly. A memory controller is configured so that one or more memory parameters (e.g., timing delay) can be determined for one or more hardware elements such as delay locked loops (DLLs). Training may be performed without intermediation by (or reporting of results to) a system BIOS. Thus, training may be performed fully in hardware. Voltage training techniques are also disclosed.

Abstract: An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.