Abstract: A memory system includes a nonvolatile memory including a memory space of logical addresses which is formatted from outside by an additional-write type file system, and a memory controller controlling the nonvolatile memory, the memory controller transmitting n error to the outside of the system if the memory controller is instructed to write data in a logical address which is equal to or smaller than a logical address of previously written data in an address area of the memory space. The memory controller controls the logical address and a physical address of the nonvolatile memory, and in conjunction with the additional-write type file system makes it possible to avoid “copy-involving write” each time file data in the nonvolatile memory is updated, thereby to promote high-speed operation by prevention of decrease in file update speed.

Abstract: Method and apparatus for securely erasing data from a non-volatile memory, such as but not limited to a flash memory array. In accordance with various embodiments, an extended data set to be sanitized from the memory is identified. The extended data set includes multiple copies of data having a common logical address and different physical addresses within the memory. The extended data set is sanitized in relation to a characterization of the data set. The data sanitizing operation results in the extended data set being purged from the memory and other previously stored data in the memory being retained.

Abstract: A method of writing data to a non-volatile memory with minimum units of erase of a block, a page being a unit of programming of a block, may read a page of stored data addressable in a first increment of address from the memory into a page buffer, the page of stored data comprising an allocated data space addressable in a second increment of address, pointed to by an address pointer, and comprising obsolete data. The first increment of address is greater than the second increment of address. A portion of stored data in the page buffer may be updated with the data to form an updated page of data. Storage space for the updated page of data may be allocated. The updated page of data may be written to the allocated storage space. The address pointer may be updated with a location of the allocated storage space.

Abstract: A method of executing an erasing instruction to erase host data from a flash memory device is provided. The method initiates with receiving from a host device an erase instruction to erase host data from an array of NAND flash memory cells grouped into separately-erasable device blocks, each device block including multiple device pages, the host data being a portion of device data that is stored in a device block. The host data is marked as erased, and a message is sent to the host device indicating that the host data has been erased.

Abstract: When a page on a random access memory (RAM) having a value matching a page on a read only memory (ROM) is detected, a memory management section of a memory manager updates a conversion table so that the page on the ROM having the matching value is referred to, and discards the detected page on the RAM. The present technology is applicable to, for example, a built-in device.

Abstract: A dispersed storage (DS) unit a processing module and a plurality of hard drives. The processing module is operable to maintain states for at least some of the plurality of hard drives. The processing module is further operable to receive a memory access request regarding an encoded data slice and identify a hard drive of the plurality of hard drives based on the memory access request. The processing module is further operable to determine a state of the hard drive. When the hard drive is in a read state and the memory access request is a write request, the processing module is operable to queue the write request, change from the read state to a write state in accordance with a state transition process, and, when in the write state, perform the write request to store the encoded data slice in the hard drive.

Abstract: A method for writing data to a disk drive. The method includes: receiving a write command; and, determining whether a beginning and an end of a rewrite area specified by the write command agree with boundaries of large-sized data sectors on a disk. The method also includes: reading head and tail data sectors and making a backup of the head and tail data sectors in first and second non-volatile memory areas, respectively, if the beginning of the rewrite area does not agree with the boundaries. The method includes starting a rewrite of the rewrite area after completing backups into first and second non-volatile memory areas. Moreover, the method includes: determining a state stage by using data in first, second, third and fourth non-volatile memory areas if a power shut-down occurs during execution of the write command; and, executing a recovery process in accordance with the determined state stage.

Abstract: A system includes a host device that may be configured to initiate memory requests to a system memory. The system also includes a memory controller that may be configured receive the memory requests and to format the memory requests into memory transactions that are conveyed to the memory device via a memory interface. The memory transactions include a plurality of memory write command types. Each memory write command type corresponds to a different respective schedule for conveying a corresponding data payload.

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: A method and apparatus for securely sharing content are provided, which can securely share the content without allowing access by unauthorized third parties. The method of securely sharing content includes a first domain, which has content that requires security among a plurality of domains logically generated on a hardware platform, sharing the content with at least one second domain, and if the second domain intends to write the content in a region in which writing is not permitted, preventing the writing of the content.

Abstract: A system and method for detecting changes of memory state. In accordance with one embodiment, memory locations to be observed are determined, and pages of these locations are marked as read-only. Then, guest instructions execute during a trial period. During the trial period, guest instructions attempting to write to the identified memory locations cause page faults which result in identifying the instructions. At the end of the trial period, the pages are returned to a writable status, and attempts to modify the memory locations by the guest code are detected based on the instruction identifier. The system and method can be used for efficient frame list topology monitoring, such as in a virtual USB controller of a virtual machine.

Abstract: There are provided methods for single-owner multi-consumer work queues for repeatable tasks. A method includes permitting a single owner thread of a single owner, multi-consumer, work queue to access the work queue using atomic instructions limited to only a single access and using non-atomic operations. The method further includes restricting the single owner thread from accessing the work queue using atomic instructions involving more than one access. The method also includes synchronizing amongst other threads with respect to their respective accesses to the work queue.

Abstract: Comprises a memory control unit which transmits and receives data to and from respective interface control units in accordance with access requests and also controls access to the memory and a buffer which temporarily stores data smaller than 64 B, wherein the memory control unit, during access to the memory, if the processing data to be processed is 64 B, accesses the memory by using the processing data or, if the processing data is data smaller than 64 B, stores the data smaller than 64 B in the buffer, subsequently, if the address of the new processing data which became the processing data is sequential to the address of the data smaller than 64 B stored in the buffer, combines the new processing data and the data of the buffer and, on condition that the combined processing data is 64 B data, writes the combined processing data in the memory.

Abstract: A data writing method for writing data from a host system into a flash memory chip is provided. The method includes configuring a plurality of logical page addresses, grouping the logical page addresses into a plurality of logical blocks, and recording the data dispersion degree of each of the logical blocks. The method also includes receiving write-in data from the host system, identifying a logical block that a logical page address to be written by the host system belongs to, and writing the write-in data into the flash memory chip according to the data dispersion degree of the logical block, wherein the data dispersion degree of each of the logical blocks is not larger than a logical block data dispersion degree threshold value. Accordingly, the method can effectively reduce the time for executing a host write command.

Abstract: Some of the embodiments of the present disclosure provide an apparatus comprising a command cancellation channel (CCC) including a plurality of stages, the CCC configured to receive a first memory address of a sequence of memory addresses and a corresponding first modification command, determine that at least a first stage of the plurality of stages includes the first memory address and a corresponding second modification command, and erase the first memory address or cancel the second modification command while shifting the first memory address and the second modification command from the first stage to a second stage. Other embodiments are also described and claimed.

Abstract: Memories, buffered write command circuits, and methods for executing memory commands in a memory. In some embodiments, read commands that are received after write commands are executed internally prior to executing the earlier received write commands. Write commands are buffered so that the commands can be executed upon completion of the later received read command. One example of a buffered write command circuit includes a write command buffer to buffer write commands and propagate buffered write commands therethrough in response to a clock signal and further includes write command buffer logic. The write command buffer logic generates an active clock signal to propagate the buffered write commands through the write command buffer for execution, suspends the active clock signal in response to receiving a read command after the write command is received, and restarts the active clock upon completion of the later received read command.

Abstract: According to one general aspect, a method may include receiving, from a processor at an I/O controller, a write-distribute command that includes an indication of data to be written to a group of storage mediums and instructions that the data should be written to multiple storage locations within the group of storage mediums. In various embodiments, the method may also include, based on the command's instructions, writing the data to at least a first storage location of the storage mediums. In one embodiment, the method may include returning a write completion message, from the I/O controller to the processor, after the data is written to a first storage location.

Abstract: An emulated electrically erasable memory system includes a random access memory (RAM) and a non-volatile memory (NVM). A write access to the RAM is received which provides first write data and a first address, where the first write data is stored in the RAM at the first address, and a currently filling sector of the NVM is updated to store both the first write data and the first address as a first record. In response to the write access, based on whether there are any remaining active records in an oldest filled sector of the NVM, a portion of an erase process or a transfer of up to a predetermined number of active records from the oldest filled sector to the currently filling sector is performed. The predetermined number of active records is less than a maximum number of total records that may be stored within the oldest filled sector.

Abstract: A data processing apparatus includes a memory which receives and outputs data with a predetermined data width, an operation circuit which outputs a read command or a write command to access the memory, and an access control circuit which replaces a part of first read data read from the memory with a partial data, and outputs partially replaced data as write data to the memory when receiving the write command and the partial data with a data width smaller than the predetermined data width associated with the write command, from the operation circuit. The access control circuit replaces a part of second read data which has been acquired in response to the read command outputted before, instead of the first read data, with the partial data, and outputs replaced partially data as the write data if the write command has been outputted in connection with a read command outputted before the write command.

Abstract: The design of nonblocking linked data structures using single-location synchronization primitives such as compare-and-swap (CAS) is a complex affair that often requires severe restrictions on the way pointers are used. One way to address this problem is to provide stronger synchronization operations, for example, ones that atomically modify one memory location while simultaneously verifying the contents of others. We provide a simple and highly efficient nonblocking implementation of such an operation: an atomic k-word-compare single-swap operation (KCSS). Our implementation is obstruction-free. As a result, it is highly efficient in the uncontended case and relies on contention management mechanisms in the contended cases. It allows linked data structure manipulation without the complexity and restrictions of other solutions.

Abstract: Read latencies in a memory array can be reduced by suspending write operations. In one example, a process includes, writing a first data set into a memory, interrupting a second memory write operation, and reading the first data set from the memory after interrupting the second memory write operation.

Abstract: The memory controller comprises a data holding unit which is composed of plural unit areas each for holding data corresponding to one logical page among logical pages each composed of plural logical sectors each assigned a logical address provided from a host system. The memory controller writes data held in a unit area which holds large amounts of write data, to the flash memories, in preference to data held in a unit area which holds small amounts of write data.

Abstract: The disclosure relates to techniques for locking and unlocking cache lines in a cache included within a multi-media processor that performs read-modify-write functions using batch read and write requests for data stored in either an external memory or an embedded memory. The techniques may comprise receiving a read request in a batch of read requests for data included in a section of a cache line and setting a lock bit associated with the section in response to the read request. When the lock bit is set, additional read requests in the batch of read requests are unable to access data in that section of the cache line. The lock bit may be unset in response to a write request in a batch of write requests to update the data previously read out from that section of the cache line.

Abstract: First operations and second operations are performed in parallel. The first operations are operations to write first data to a first unit area which is any one of unit areas. The second operations are operations to read second data corresponding to the same logical page as first data from one or more flash memories and write the second data to a second unit area which is any one of the unit areas and different from the first unit area. Data transfer is performed between the first unit area and the second unit area so as to form data composed of the first data and a portion of the second data which is not replaced with the first data.

Abstract: According to one embodiment, a nonvolatile semiconductor memory includes two memory planes in a chip, a I/O circuit in the chip, the I/O circuit shared by the two memory planes, and a control circuit in the chip, the control circuit controlling a write operation, a verify operation and a read operation to the two memory planes independently. Each of the two memory planes comprises a memory cell array and a data register stored write data temporarily. The control circuit configured to transfer the write data to the data registers in the two memory planes in parallel to execute the write and verify operations to every memory plane one by one in a mirroring write mode, and transfer the write data to the data register in one of the two memory planes to execute the write and verify operations in a normal write mode.

Abstract: Method and apparatus for sanitizing a memory using bit-inverted data. In accordance with various embodiments, a memory location is sanitized by sequential steps of reading a bit value stored in a selected memory cell of the memory, inverting the bit value, and writing the inverted bit value back to the selected memory cell. The memory cell may be erased between the reading and writing steps, as well as after the writing step. Random bit values may be generated and stored to the memory cell, and run-length limited constraints can be used to force bit-inversions.

Abstract: Systems and methods for controlling memory access operations are disclosed. The system may include one or more requestors performing requests to memory devices. Within a memory controller, a request queue receives requests from a requestor, a bank decoder determines a destination bank, and the request is placed in an appropriate bank queue. An ordering unit determines if the current request can be reordered relative to the received order and generates a new memory cycle order based on the reordering determination. The reordering may be based on whether there are multiple requests to the same memory page, multiple reads, or multiple writes. A memory interface executes each memory request in the memory cycle order. A data buffer holds write data until it is written to the memory and read data until it is returned to the requestor. The data buffer also may hold memory words used in read-modify-write operations.

Abstract: A network device may operate to increase application performance over a wide area network. In one particular implementation, the network device may monitor accesses to a disk drive from entities and determine whether an entity is accessing the disk drive in a manner that causes a disproportionate amount of performance degradation. If so, the network device may throttle access to the disk drive for the entity.

Abstract: A method, apparatus and program storage device for performing a return/rollback process for RCU-protected data structures is provided that includes checking a user-level state of a preempted thread having a RCU read-side critical section, and executing the critical section of the thread after preemption when the user-level state of the thread indicates execution, otherwise returning to a point of preemption, resuming execution of the thread and disabling checking the user-level state when the user-level state of the thread indicates return.

Abstract: The invention relates to any electronic device such as a chip card, a passport, a dongle or any other object requiring personalization of the content of a memory. More precisely, the invention provides for a method for processing a data item of a container stored in a memory, said method being implemented by the electronic device by utilizing in particular a table of identifiers. The invention furthermore provides for a prior step for associating a data identifier with a data item of a container and creating said table of identifiers.

Abstract: A memory device and related techniques are provided to modify data stored in the memory device without the need to send the data to an external device. A command is received at the memory device to modify data stored at a memory location in a memory array of the memory device. The command includes a value to be used for modifying the data. The memory device reads data from the memory location. The data read from the memory location is modified with modify circuit in the memory device based on the value obtained form the command to produce results data. The results data produced by the modify circuit is written back to the memory location. Since the memory device does not need to send the data read from the memory array off-chip to another device, referred to herein as a host device, to update the data, the input/output bandwidth of the bandwidth is substantially reduced, allowing for lower power memory device operation and reduced latency.

Abstract: One embodiment of the invention sets forth a mechanism for efficiently processing atomic operations transmitted from multiple general processing clusters to an L2 cache. A tag look-up unit tracks the availability of each cache line in the L2 cache, reserves the necessary cache lines for the atomic operations and transmits the atomic operations to an ALU for processing. The tag look-up unit also increments a reference counter associated with a reserved cache line each time an atomic operation associated with that cache line is received. This feature allows multiple atomic operations associated with the same cache line to be pipelined to the ALU. A ROP unit that includes the ALU may request additional data necessary to process an atomic operation from the L2 cache. Result data is stored in the L2 cache and may also be returned to the general processing clusters.

Abstract: A data storage system and associated method comprising system configuration information; a first processor adapted for identifying a portion of the system configuration information in response to a configuration change request to the memory space, and for signaling an update request incident with the configuration change request to a second processor; and a second processor adapted for updating the portion in response to the update request and independently of the first processor.

Abstract: A semiconductor memory device includes a memory cell array and an error correction code (ECC) engine. The memory cell array stores bits of normal data and parity data therein. The ECC engine performs a masking operation in a masking mode, the ECC engine calculating the parity data using the normal data. The normal data includes a first section that is to be updated and a second section that is to be saved by the masking operation.

Abstract: A method is used for editing a data element stored in a static memory device comprising a plurality of storage units. The method includes a step of copying a content of one of the storage units to a dynamic memory device, wherein the content comprises the data element. The method further includes editing the data element while the data element is stored in the dynamic memory. The method also includes erasing said one of the storage units, and writing the content, including the data element that has been edited, into one of the storage units.

Abstract: Some of the embodiments of the present disclosure provide an apparatus comprising a command cancellation channel (CCC) including a plurality of stages, the CCC configured to receive a first memory address of a sequence of memory addresses and a corresponding first modification command, determine that at least a first stage of the plurality of stages includes the first memory address and a corresponding second modification command, and erase the first memory address or cancel the second modification command while shifting the first memory address and the second modification command from the first stage to a second stage. Other embodiments are also described and claimed.

Abstract: Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, mechanisms, and means for a storage controller (e.g., memory controller, disk controller, etc.) performing a set of multiple operations on cached data with a no-miss guarantee until the multiple operations are complete, which may, for example, be used by a packet processor to quickly update multiple statistics values (e.g., byte, packet, error counts, etc.) based on processed packets. Operations to be performed on data at the same address and/or in a common data structure are grouped together and burst so that they arrive at the storage system in contiguous succession for the storage controller to perform. By not allowing the storage controller to flush the data from its cache until all of the operations are performed, even a tiny cache attached to the storage controller can reduce the bandwidth and latency of updating the data.

Abstract: Data storage reliability is maintained in a write-back distributed data storage system including multiple nodes, each node comprising a processor and an array of failure independent data storage devices. Information is stored as a set of stripes, each stripe including a collection of multiple data strips and associated parity strips, the stripes distributed across multiple corresponding primary data nodes and multiple corresponding parity nodes. A primary data node maintains the data strip holding a first copy of data, and each parity node maintains a parity strip holding a parity for the multiple data strips. A read-modify-write parity update protocol is performed for maintaining parity coherency, the primary data node driving parity coherency with its corresponding parity nodes, independently of other data nodes, in order to keep its relevant parity strips coherent.

Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

Abstract: An apparatus includes a first storage unit, a second storage unit, a setting unit configured to set a level of data deletion used for executing a job, an identification unit configured to identify a storage unit to be used for the job, and a control unit configured to, if the set level is a predetermined level and the identified storage unit is the first storage unit, store data of the job into the first storage unit and overwrite the stored data when the job is executed, and configured to, if the set level is the predetermined level and the identified storage unit is the second storage unit, encrypt data of the job and store the encrypted data into the second storage unit when the job is executed.

Abstract: A buffer management method is provided. A host issues a read command requesting access for a read data block and a write command requesting recording of a write data block. A write buffer is dedicated to store the write data block. A read buffer is dedicated to store the read data block. The method comprises entering the optical disc recorder into a write loop. During the write loop, the optical disc recorder triggering a write command handling procedure in response to the write command; triggering a read command handling procedure in response to the read command; and triggering a pre-recording procedure to prepare the write data block in the write buffer for recording. Wherein contents between the write buffer and read buffer are exchangeable during the write handling procedure, the read handling procedure or the pre-recording procedure.

Abstract: A non-volatile memory device having a memory array is configured to prevent power voltage noise generation during programming, thereby improving reliability. An associated programming method of the non-volatile memory device includes storing data input from an external source to a cache register. The stored data is moved to a main register. The cache register is cleared and the data stored in the main register is programmed to the memory cell array.

Abstract: A database of codesets for a remote control device includes codeset information blocks for derivative codesets and codeset information blocks for nonderivative codesets. A codeset information block for a derivative codeset includes: a bit indicating that the block is for a derivative codeset, a plurality of bits each of which corresponds to a respective one of a plurality of fields in a referenced codeset information block, and a pointer that points to the referenced codeset information block. The digital value of a bit determines whether information from the corresponding field in the referenced block will be used as part of the derivative codeset or whether such information is contained in the derivative codeset information block itself. The sizes of the fields in the referenced block are predetermined or are determinable, so a field in the referenced block can be located if its bit is set in the referencing block.

Abstract: In an embodiment, a data processing system comprises a storage system coupled to a unit under test comprising a heap memory, a static memory and a stack; second logic operable to perform: detecting one or more changes in a first state of the heap memory and the static memory; storing, in the storage system, as a state point of the unit under test, the one or more changes in the first state of the heap memory and the static memory; third logic operable to perform: receiving a request to change the memory under test to a particular state point; in response to the request, loading the particular state point from the storage system and applying the state point to the heap memory and the static memory to result in changing the heap memory and the static memory to a second state that is substantially equivalent to the first state.

Abstract: A memory interface system can include a memory controller configured to operate at a first operating frequency. A physical interface block can be coupled to the memory controller. The physical interface block can be configured to communicate with the memory controller at the first operating frequency and communicate with a memory device at a second operating frequency that is independent of the first operating frequency.

Abstract: There is provided a memory device capable of stably storing recorded data over a long term of several decades or longer and capable of reliably reading stored data. A first circuit 200 and a second circuit 300 are separately implementable, and the first circuit 200 includes a data recording circuit 210 reading recorded data from an address appointed by an address signal when a read/write signal stays at a first level and writing data to the address appointed by the address signal when the read/write signal stays at a second level, and a write/read control circuit 230 performing data write/read control on the data recording circuit according to the address signal in response to a read or write instruction from the second circuit.

Abstract: A method for implementation of memory management on a read/write memory of a data processing device, in which a multiplicity of tasks (T1-T6) occupy at least parts of the read/write memory, and parts of the read/write memory that were occupied by the tasks (T1-T6) but are no longer needed are found by way of time-based memory cleanup, and released again. The method includes reserving at least one processor of the data processing device for every task (T1-T6), for a duration of at least one time slot, and performing memory cleanup in free time slots reserved for memory cleanup. Work-based memory cleanup is performed by interrupting the tasks (T1-T6) during the time slots reserved for these tasks, before and/or after every memory allocation, for a specific period of time, for the purpose of memory cleanup.

Abstract: A data writing method for a storage device includes utilizing the storage device to transmit identification information according to a data writing request from a processing unit, utilizing the processing unit to transmit data writing information corresponding to the identification information according to the identification information, and utilizing the storage device to perform a data writing process according to the data writing information.

Abstract: Techniques are provided which may be implemented in various methods and/or apparatuses that to provide a virtual buffer interface capability between a plurality of processes/engines and a memory pool.

Abstract: An information processing apparatus for recording data onto a recording medium, includes an access controller for outputting, to a medium-specific controller, record data input from an application and directed to the recording medium. The access controller performs a read-modify-write (RMW) operation by verifying whether one of a record start position and a record end position of the record data input by a logical sector unit from the application is different from a delimitation position of a physical sector as an access unit of the recording medium, acquiring the record data by the physical sector unit and storing the record data onto a memory if one of the record start position and the record end position is different from the delimitation position, updating logical sector data as part of stored physical sector data with the input record data, and outputting the updated physical sector data to the medium-specific controller.