Abstract: Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests.

Abstract: Techniques for preserving memory affinity in a computer system is disclosed. In response to a request for memory access to a page within a memory affinity domain, a determination is made if the request is initiated by a processor associated with the memory affinity domain. If the request is not initiated by a processor associated with the memory affinity domain, a determination is made if there is a page ID match with an entry within a page migration tracking module associated with the memory affinity domain. If there is no page ID match, an entry is selected within the page migration tracking module to be updated with a new page ID and a new memory affinity ID. If there is a page ID match, then another determination is made whether or not there is a memory affinity ID match with the entry with the page ID field match. If there is no memory affinity ID match, the entry is updated with a new memory affinity ID; and if there is a memory affinity ID match, an access counter of the entry is incremented.

Abstract: A reproducing apparatus and method includes a reproducing unit to reproduce mainstream data and sub audio data separately added in the mainstream data, wherein the reproducing unit comprises a counter used in reproducing the sub audio data. Accordingly, it is possible to more naturally reproduce still image data, such as a browsable slide show, to which sub audio data is additionally included, thus preventing an interruption in reproduction of the sub audio data even during a forward or reverse play.

Abstract: A method of managing memory may include selecting an object of a memory heap to be de-allocated and initiating a deferred lock configured to delay de-allocation of the object. The deferred lock may be acquired in response to a thread leaving a computing space, and the object may be de-allocated.

Abstract: A RAID storage array having a controller and plurality of disk drives is configured into a plurality of groups. The plurality of disk drives are in a plurality of drive trays. The controller includes a main memory. A set of configuration information is stored on a central nonvolatile memory device. The set of configuration information includes group configuration information corresponding to each group of the plurality of groups with which a corresponding disk drive is associated. The set of configuration information is stored on a plurality of remote nonvolatile memory devices that are each associated with at least one of the plurality of drive trays. A bootware control process is loaded into the main memory. The bootware control process is executed. A plurality of service layer processes are loaded into the main memory. The plurality of service layer processes are executed in parallel under the control of the bootware control process.

Abstract: The present disclosure includes methods, devices, modules, and systems for storing selective register reset. One method embodiment includes receiving an indication of a die and a plane associated with at least one address cycle. Such a method can also include selectively resetting a particular register of a number of registers, the particular register corresponding to the plane and the die.

Abstract: A storage device can comprise storage media that can have differing characteristics. A storage manager can obtain the characteristics of a storage device, and of individual portions, such as individual media, of the storage device, by querying the device, querying a database, or through empirical observation or testing. The storage manager can then divide the media of the storage device into storage media parts, that can comprise some or all of the individual storage media. Data can then be stored on one or more storage media parts in accordance with the information provided by metadata associated with the data, such that the data is stored on storage media parts that are optimal for such data, from among the available storage media parts, based on the information from the associated metadata.

Abstract: A method of managing storage device resets in a system using shared storage is provided. A reset instruction is received at a shared storage device from a first node. In response, the storage device is at least partially reset, including aborting one or more queued I/O commands including a first I/O command received from a second node. A reset notification timer is started. If an I/O command is received from the second node during the reset notification timer, in response to receiving the I/O command the second node is notified of the storage device reset such that the second node can determine that the first I/O command was aborted. If no I/O command is received from the second node during the reset notification timer, at the expiration of the timer, the second node is notified of the storage device reset such that the second node can determine that the first I/O command was aborted.

Abstract: When a command to restore a logical unit is issued after a command to delete the logical unit, the logical unit is restored easily. When a controller receives an LU deletion command from a management terminal and if the relevant LU is a normal LU, it retains information about the deletion target LU, from among information in an LU management table, as reset information; and if the relevant LU is a virtual LU, the controller retains information about the deletion target LU, from among information in a virtual address table, as the reset information. If the controller receives an LU restoration command to restore the deletion target LU as an access target LU, from the management terminal, it restores the retained reset information as setting information corresponding to the access target LU and manages the restored setting information by using the LU management table or the virtual address table, thereby processing an access request from a host computer.

Abstract: In a method of initializing a computer memory that receives data from a plurality of redrive buffers, a predetermined data pattern of a selected set of data patterns is stored in selected redrive buffers of the plurality of redrive buffers. Each of the selected set of data patterns includes a first initialization data pattern and an error correcting code pattern that is a product of a logical function that operates on the first initialization data pattern and an address in the computer memory. The selected set of data patterns includes each possible value of error correcting code pattern. A redrive buffer of the plurality of redrive buffers that has stored therein an error correcting code pattern that corresponds to the selected address is selected when sending a first initialization data pattern to a selected address. The selected redrive buffer is instructed to write to the selected address the first initialization data pattern and the error correcting code pattern that corresponds to the selected address.

Abstract: A system and method of squeezing slabs of memory empty are provided. A slab is a block of allocated memory space that is dedicated to holding one type of data. When it is determined that a slab of memory is to be squeezed empty, no object may be allocated from the slab. That is, new data is precluded from being placed in any unused space of the slab. Further, data is also precluded from being placed in any space in the slab that becomes unused anytime thereafter. When the slab becomes empty, the slab is de-allocated.

Abstract: It is an object of the present invention to provide a storage apparatus that can suppress access performance degradation owing to processing of data deduplication. The storage apparatus according to the present invention acquires a sum of the access frequencies to each of redundantly allocated pieces of data, and performs the deduplication on the pieces of data having the sum of access frequencies less than a prescribed threshold (FIG. 10).

Abstract: A method for measuring a lifespan of a memory device includes measuring an operation time of the memory device and generating lifespan information by comparing the measured operation time with a reference operation time.

Abstract: A mechanism is provided for firehose dumping modified data in a static random access memory of a hard disk drive to non-volatile memory of the hard disk drive during a power event. Responsive an indication of a power event in the hard disk drive, hard disk drive command processing is suspended. A token is set in the non-volatile storage indicating that flash memory in the non-volatile memory contains modified data. A portion of a static random access memory cache table containing information on the modified data in the static random access memory is copied to the flash memory. The modified data from the static random access memory is then copied to the flash memory. Responsive to a determination that the power event that initiated the copy of the modified data in the static random access memory to the flash memory is still present, the hard disk drive is shut down.

Abstract: Various methods are provided for leakage reduction via optimized reset states and improving performance for storage elements. The methods include selecting a storage element, where the storage element comprises at least one storage element component sized to reduce static current leakage or at least one storage element component adapted to increase at least one of speed or performance of the storage element. The methods also call for determining a preferred reset state for the storage element, wherein the preferred reset state is based at least upon the reduction of static current leakage, the speed or the performance of the storage element. The methods also call for setting the storage element reset state to the preferred reset state.

Abstract: A method for erasing a non-volatile memory includes: performing a first pre-erase program step on the non-volatile memory; determining that the non-volatile memory failed to program correctly during the first pre-erase program step; performing a first soft program step on the non-volatile memory in response to determining that the non-volatile memory failed to program correctly; determining that the non-volatile memory soft programmed correctly; performing a second pre-erase program step on the non-volatile memory in response to determining that the non-volatile memory soft programmed correctly during the first soft program step; and performing an erase step on the non-volatile memory. The method may be performed using a non-volatile memory controller.

Abstract: A method for initializing a memory area, the method includes: receiving a request to access a first memory sub area of a first memory area that comprises multiple memory sub areas; and initializing the first memory sub area if a first memory area initialization indicator differs from a first memory sub area initialization request indicator; wherein the first memory area initialization request indicator is a multiple bit variable indicative of a time of a last request to initialize the first memory area and the first memory sub area initialization indicator is a multiple bit variable indicative of a time of a request to initialize the first memory area that resulted in a last initialization of the first memory sub area.

Abstract: A microcontroller (30) includes a processor (32), an embedded memory (46) operatively coupled to the processor (32), and a microcontroller test interface (34) operatively connected to the processor (32) and the memory (36). The microcontroller (30) responds to a reset signal to perform a reset initiation that causes an initial disabled state of the test interface (34) to be set and execution of initiation code with the processor (32). This code execution optionally establishes a further disabled state. The microcontroller (30) provides an enabled state of the test interface for memory (46) access through the test interlace (34) during microcontroller (30) operation subsequent to the reset initiation unless the further disabled memory (46) access state is established by execution of the initiation code.

Abstract: A data management method of a data storage device having a data management unit different from a data management unit of a user device receives information regarding a storage area of a file to be deleted, from the user device, selects a storage area which matches with the data management unit of the data storage device, from among the storage area of the deleted file, and performs an erasing operation on the selected storage area which matches with the data management unit.

Abstract: Described embodiments provide a method of recovering storage space on a solid state disk (SSD). An index and valid page count are determined for each block of a segment of an SSD. If the valid page count of at least one block in the segment is zero, a quick clean is performed. A quick clean deallocates blocks having zero valid pages and places them in a queue for erasure. Otherwise, a deep clean is performed. A deep clean determines a compaction ratio, N-M, wherein N is a number of partially valid blocks and M is a number of free blocks required to compact the valid data from the N partially valid blocks into M entirely valid blocks. At least one data structure of the SSD is modified to refer to the M entirely valid blocks, and the N partially valid blocks are placed in the queue for erasure.

Abstract: Methods permitting erasures to be performed evenly over time in memory, thereby extending the service life of a data storage device, and devices operable to perform those methods. Erasures performed on a given physical block in memory are tracked by incrementing a corresponding erase count included in an entry associated with a logical block correlated with that physical block. Each of a plurality of physical blocks included in the memory is associated with logical zones such that each logical zone comprises a different portion of the physical blocks. An erase count indicator is determined for each logical zone. When the total number of erasures for the given physical block reaches a limit, the entry associated with the logical block correlated with that physical block is exchanged with another entry associated with a logical block correlated with a physical block in a logical zone having a lower count indicator.

Abstract: A method of managing storage device resets in a system using shared storage is provided. A reset instruction is received at a shared storage device from a first node. In response, the storage device is at least partially reset, including aborting one or more queued I/O commands including a first I/O command received from a second node. A reset notification timer is started. If an I/O command is received from the second node during the reset notification timer, in response to receiving the I/O command the second node is notified of the storage device reset such that the second node can determine that the first I/O command was aborted. If no I/O command is received from the second node during the reset notification timer, at the expiration of the timer, the second node is notified of the storage device reset such that the second node can determine that the first I/O command was aborted.

Abstract: A delete notification can be received at a storage stack filter in a storage stack. It can be determined whether the delete notification applies to an entire storage volume. If the delete notification does not apply to the entire storage volume, a first set of actions can be taken with the storage stack filter in response to the delete notification. If the delete notification does apply to the entire storage volume, a second set of actions can be taken with the storage stack filter in response to the delete notification.

Abstract: An apparatus includes a nonvolatile memory, an interface that at least receives an erase command of the nonvolatile memory, a first controller that controls the nonvolatile memory to execute data erasing on the basis of the erase command output from the interface, an external input unit which is installed independently of the interface, a second controller that controls the nonvolatile memory to execute data erasing on the basis of an erase instruction signal output from the external input unit, and a change-over circuit that switches between connection of the first controller with the nonvolatile memory and connection of the second controller with the nonvolatile memory, wherein the second controller controls the nonvolatile memory to execute data erasing on the basis of the erase instruction when the connection of the second controller with the nonvolatile memory is established by the change-over circuit.

Abstract: According to one embodiment, a computer program product includes a non-transitory computer-readable storage medium having computer readable program codes embodied in the medium that are executed on a computer. The computer comprises a storage module that stores a plurality of contents. The use order in which the contents are used is determined. The codes, when executed on the computer, cause the computer to perform: transmitting the contents to an external device to store the contents therein; first determining whether each of the contents stored in the storage module satisfies use condition determined according to the use order; deleting content that does not satisfy the use condition from the storage module; second determining whether content, which is stored in the external device and is not stored in the storage module, satisfies the use condition; and receiving the content from the external device if the content satisfies the use condition.

Abstract: The apparatus in one example may have: at first and second processing devices; at least one sequence of processes for the first and second devices; the at least one sequence having a command forward instruction such that, after the first processing device completes processing a first process of the at least one sequence of processes, the first processing device forwards, without producing an interrupt, the command forward instruction to the second processing device to effect processing of a second process of the at least one sequence of processes.

Abstract: The present disclosure includes methods, devices, modules, and systems for storing selective register reset. One method embodiment includes receiving an indication of a die and a plane associated with at least one address cycle. Such a method can also include selectively resetting a particular register of a number of registers, the particular register corresponding to the plane and the die.

Abstract: A storage control device includes an obtaining unit that obtains data; a recognition unit that recognizes an area among areas in a storage unit, as a recordable area, the area to be recognized being where the data obtained by the obtaining unit is stored and overwriting has been executed a predetermined number of times; a recording unit that records data obtained by the obtaining unit onto the recordable area recognized by the recognition unit; a first overwriting unit that executes the overwriting on an area where data has been recorded by the recording unit and the overwriting has not yet been executed the predetermined number of times; and a specifying unit that specifies a remaining count for each of the areas in the storage unit, the remaining count indicating a difference between the predetermined number of times and a number of times the overwriting has been executed.

Abstract: A pool is replicated in the unit of volume providing the pool, and when a physical device is blocked, any volume blocked in the pool is changed to the replicated volume so that the pool and a virtual volume can be recovered. With such a configuration, when any pool or virtual volume is blocked due to blockage of any volume providing the thin provisioning function, volume recovery can be swiftly performed without changing the virtual volume used by a host computer, and consumption of storage resources needed therefor can be suppressed.

Abstract: A method for initializing a memory area, the method includes: receiving a request to access a first memory sub of a first memory area that comprises multiple memory sub areas; and initializing the first memory sub area if a first memory area initialization indicator differs from a first memory sub area initialization request indicator; wherein the first memory area initialization request indicator is a multiple bit variable indicative of a time of a last request to initialize the first memory area and the first memory sub area initialization indicator is a multiple bit variation indicative of a time of a request to initialize the first memory area that resulted in a last initialization of the first memory sub area.

Abstract: Various embodiments for storage initialization and data destage in a computing storage environment are provided. At least a portion of data on a storage device is initialized using a background process, while one of simultaneously and subsequently destaging the at least the portion of the data to the storage device using a foreground process is performed. A persistent metadata bitmap, adapted to indicate whether the at least the portion of the data has been initialized, is staged to cache, the cache operable in the computing storage environment. The background process maintains a volatile bitmap indicating a status of the initialization of the at least the portion of the data in direct correspondence to the metadata bitmap. As the background process initializes the at least the portion of the data, an applicable bit on the persistent metadata bitmap is cleared and a corresponding bit is set on the volatile bitmap.

Abstract: A method for prioritized erasure of a non-volatile storage device, the method including the steps of: providing at least one flash unit of the storage device, wherein each flash unit has a plurality of blocks; writing data into the plurality of blocks; assigning an erasure-priority to each block, wherein the erasure-priority correlates with an erasure-priority of the data; and erasing the data in each block according to the erasure-priority of each block upon receiving an emergency-erase command. Preferably, the step of writing data into the plurality of blocks is performed in an arbitrary order in a first flash unit, and the step of writing into subsequent flash units is performed in correlation with the order in the first flash unit. Preferably, the step of erasing includes aborting erasure, before completing the erasure, for at least some of the plurality of blocks.

Abstract: A storage medium management part includes a stored data amount adjustment part that: stores a maximum data amount which the storage medium can store at the time of startup of a storage control device, and a stored data amount which is an initial stored amount, in a data amount storage part; upon receiving a write amount of a data in response to a write request, writes a new stored data amount calculated by adding the write amount to the already stored data amount, over the already stored data amount; calculates a free space by subtracting the stored data amount from the maximum data amount; determines a deletion amount of the data if the free space does not takes a value not less than a prescribed value; and writes a newly-calculated stored data amount calculated by subtracting the deletion amount from the stored data amount, over the stored data amount.

Abstract: A method is provided for operating a data processing system having a memory. The memory is coupled between a first power supply voltage terminal for receiving a first variable potential and a second power supply voltage terminal for receiving a second variable potential. An initial difference between the first variable potential and the second variable potential is not less than a first voltage. The method comprises: receiving a command to transition the data processing system from a first power supply voltage to a second power supply voltage; changing the second variable potential so that a difference between the second variable potential and the first variable potential is greater than the first voltage; and after changing the second variable potential, changing the first variable potential, wherein a difference between the first variable potential and the second variable potential is not less than the first voltage.

Abstract: A memory management system includes a plurality of processors, a shared memory that can be accessed from the plurality of processors, cache memories provided between each processor of the plurality of processors and the shared memory and invalidation or write back of a specified region can be commanded from a program running on a processor. Programs running on each processor invalidate an input data region of a cache memory with an invalidation command immediately before execution of a program as a processing batch, and write back an output data region of a cache memory to the shared memory with a write back command immediately after execution of a program as a processing batch.

Abstract: A storage device includes storage media and a controller to control access of the storage media. The controller receives an erase command used to specify an erase operation of at least one portion of the storage media. The erase command has a control field controllable by a requestor device that submitted the erase command to the storage device, where the control field has one or more portions settable to cause the storage device to perform one or more of: reporting a progress of the erase operation, and modifying an operational state of the erase operation.

Abstract: A method of operating a processor includes reclaiming a physical register renamed as a microcode architectural register used by a microcode routine. The physical register is reclaimed according to an indicator corresponding to the microcode architectural register and indicating that a pointer to the physical register and corresponding to the microcode architectural register is an active pointer.

Abstract: A solid state drive includes a plurality of flash memory devices, and a memory controller coupled to the plurality of flash memory devices. The memory controller is configured to logically associate blocks from the plurality of flash memory devices to form zip codes, the zip codes associated with corresponding erase counters. The solid state drive further includes a processor and a computer-readable memory having instructions stored thereon. The processor may perform a wear-leveling operation by determining that blocks in a first zip code have been erased and incrementing a first erase counter associated with the first zip code. It may then be determined that a second erase counter associated with a second zip code is low relative to at least one other erase counter, and based on this determination, data from blocks in the second zip code may be written to new blocks as part of a wear-leveling operation.

Abstract: Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests.

Abstract: A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device. The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode detection signal in response to receipt of the memory address signals or a first combination of control signals. An first mode initiation signal is generated a time delay subsequent to the detection signal to initiate the first mode memory access operation. In response to receipt of a second combination of control signals and an active clock signal, the memory access mode detection circuit further generates a second mode detection signal to initiate a second mode memory access operation and to suppress generation of the first mode detection signal, thereby canceling the first mode memory access operation.

Abstract: Systems and methods for performing hierarchical storage operations on electronic data in a computer network are provided. In one embodiment, the present invention may store electronic data from a network device to a network attached storage (NAS) device pursuant to certain storage criteria. The data stored on the NAS may be migrated to a secondary storage and a stub file having a pointer pointing to the secondary storage may be put at the location the data was previously stored on the NAS. The stub file may redirect the network device to the secondary storage if a read request for the data is received from the network device.

Abstract: A computer readable medium stores a program causing a computer to execute a process including receiving an instruction for deleting an information group from a first memory; extracting, from the first memory, information regarding information groups having a parent-child relationship with a target information group to be deleted in accordance with the received instruction; extracting a user identification code associated with the target information group from a second memory; storing an identification code of the target information group, the information regarding the information groups, and the extracted user identification code in association with one another in a third memory; deleting the target information group from the first memory; and changing the structure information stored in the first memory to structure information obtained after the target information group has been deleted from the first memory, by changing the child information group as a child of the parent information group.

Abstract: A storage device includes a memory for storing data in a plurality of logical volumes; a controlling unit for controlling an access to data in accordance with a process comprising the steps of: generating mapping information indicative of a correspondence between logical volume information and recognition information; generating a pseudo logical volume and pseudo logical volume information associated with the pseudo logical volume, the pseudo logical volume being another of the logical volumes; and upon receipt of a command for canceling an assignment of one of the logical volumes to the corresponding recognition information, modifying the mapping information so that recognition information that has been indicative of said one of the logical volumes becomes indicative of the pseudo logical volume information associated with the pseudo logical volume.

Abstract: Garbage collection in a first node server of an in-memory replication system includes: in response to a garbage collection trigger in the first node server, determining whether identification information for a data object eligible for garbage collection in the first node server has been received by the first node server from at least a second node server in the in-memory replication system; and if the identification information has been received from at least the second node server, performing garbage collection on the data object with the first node server.

Abstract: A method is implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to optimize data ramanence over hybrid disk clusters using various storage technologies. The programming instructions are operable to determine one or more data storage technologies accessible by a file system. The programming instructions are operable to determine secure delete rules for each of the one or more storage technologies accessible by the file system. The secure delete rules include a number of overwrites required for data to be securely deleted from each of the one or more storage technologies. The programming instructions are operable to provide the secure delete rules to the file system upon a request for deletion of data for each of the one or more storage technologies a specific amount of times germane to secure delete data from the one or more storage technologies.

Abstract: A second memory stores data in units of segments. An assignment control circuit sets up a buffer space as a logical address space. A buffer space is formed as a set of at least one segment. A state storage circuit stores association between a buffer space and segments as segment assignment information. An address conversion circuit refers to segment assignment information to convert a logical address into a physical address. A segment queue stores a free segment and a buffer queue stores a free buffer. The state storage circuit includes a plurality of register groups each of which includes a plurality of segment registers. A register group is associated with one of the plurality of buffer spaces. A range number identifying a range of logical addresses in the associated buffer space is set up in a segment register.

Abstract: A method includes configuring a flash memory device including a first memory sector having a primary memory sector correspondence, a second memory sector having an alternate memory sector correspondence, and a third memory sector having a free memory sector correspondence, copying a portion of the primary memory sector to the free memory sector, erasing the primary memory sector, and changing a correspondence of each of the first memory sector, the second memory sector, and the third memory sector.

Abstract: A method and system for phasing power-intensive operations is disclosed. A non-volatile storage device controller detects a power reset. The controller is in communication with non-volatile memories in the non-volatile storage device. In response to detecting a power reset, the controller determines a current consumption necessary to reset the non-volatile memories in the non-volatile storage device. The controller simultaneously resets all of the non-volatile memories when the determined current consumption is less than a current consumption threshold. If the determined current consumption is greater than the current consumption threshold, the controller resets a first subset of the plurality of non-volatile memories, and after a predetermined delay, resets a second subset of the non-volatile memories. Therefore, a power-intensive operation may be performed without exceeding a current consumption threshold by dividing the operation into a sequence of steps that do not exceed the threshold.

Abstract: A method of dynamically switching partitions for a memory card having a plurality of physical blocks is provided. The method includes configuring logical blocks for mapping to at least a portion of the physical blocks and dividing the logical blocks into first and second partitions; coupling the memory card to a host system and setting CSD corresponding to the memory card as a first default value corresponding to the first partition, wherein the host system requests the CSD to obtain the first default value and accesses the first partition according to the first default value; and setting the CSD corresponding to the memory card as a second default value corresponding to the second partition in response to a switch command from the host system, wherein the host system re-requests the CSD to obtain the second default value and accesses the second partition according to the second default value.

Abstract: Mechanisms are provided for data placement optimization during runtime of a computer program. The mechanisms detect cache misses in a cache of the data processing system and collect cache miss information for objects of the computer program. Data context information is generated for an object in an object access sequence of the computer program. The data context information identifies one or more additional objects accessed as part of the object access sequence in association with the object. The cache miss information is correlated with the data context information of the object. Data placement optimization is performed on the object, in the object access sequence, with which the cache miss information is associated. The data placement optimization places connected objects in the object access sequence in close proximity to each other in a memory structure of the data processing system.