Abstract: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.

Abstract: A recordable memory device includes a nonvolatile semiconductor memory, and a controller controlling the nonvolatile semiconductor memory based on a recordable system. The nonvolatile semiconductor memory has a user area capable of directly making an access from a host, and a system area managed by the controller. A data writing to the reformatted user area of the nonvolatile semiconductor memory executes from a start point which is an unused area after the final physical address of old recordable data recorded in the user area before the reformat. The data writing executes from a start point which is a top physical address in the user area, when the start point exceeds the final physical address in the user area.

Abstract: A method and apparatus for providing TCAM functionality in a custom integrated circuit (IC) is presented. An incoming key is broken into a predefined number of sub-keys. Each sub-key is sued to address a Random Access Memory (RAM), one RAM for each sub-key. An output of the RAM is collected for each sub-key, each output comprising a Partial Match Vector (PMV). The PMVs are bitwise ANDed to obtain a value which is provided to a priority encoder to obtain an index. The index is used to access a result RAM to return a result value for the key.

Abstract: The invention provides a system and method for tracking memory information associated with dynamically loaded kernel modules with the help of a tracking system. The tracking system defines its own kernel memory allocation functions. Whenever, a dynamic kernel module is loaded/unloaded into/from the kernel space, these newly defined functions are called in response to kernel memory allocation/de-allocation requests from the kernel module. The newly defined functions are responsible for allocating and de-allocating kernel memory, as well as, keeping track of information relating to the kernel memory allocations/de-allocations. The tracked information may be used to identify the source of kernel memory leaks.

Abstract: Embodiments for a local data share (LDS) unit are described herein. Embodiments include a co-operative set of threads to load data into shared memory so that the threads can have repeated memory access allowing higher memory bandwidth. In this way, data can be shared between related threads in a cooperative manner by providing a re-use of a locality of data from shared registers. Furthermore, embodiments of the invention allow a cooperative set of threads to fetch data in a partitioned manner so that it is only fetched once into a shared memory that can be repeatedly accessed via a separate low latency path.

Abstract: A method and apparatus for distributed parallel messaging in a parallel computing system. The apparatus includes, at each node of a multiprocessor network, multiple injection messaging engine units and reception messaging engine units, each implementing a DMA engine and each supporting both multiple packet injection into and multiple reception from a network, in parallel. The reception side of the messaging unit (MU) includes a switch interface enabling writing of data of a packet received from the network to the memory system. The transmission side of the messaging unit, includes switch interface for reading from the memory system when injecting packets into the network.

Abstract: A method and apparatus creates and manages persistent memory (PM) in a multi-node computing system. A PM Manager in the service node creates and manages pools of nodes with various sizes of PM. A node manager uses the pools of nodes to load applications to the nodes according to the size of the available PM. The PM Manager can dynamically adjust the size of the PM according to the needs of the applications based on historical use or as determined by a system administrator. The PM Manager works with an operating system kernel on the nodes to provide persistent memory for application data and system metadata. The PM Manager uses the persistent memory to load applications to preserve data from one application to the next. Also, the data preserved in persistent memory may be system metadata such as file system data that will be available to subsequent applications.

Abstract: In address generation processors, the start and the end of the processing for address generation need to be controlled in addition to controlling the processing for base address generation. A timing control unit manages control for address conversion on a clock cycle basis. The difference between the processing speed in the address generation processors and the processing speed in the address conversion circuit is absorbed by buffers.

Abstract: A method for managing software modules of at least two operating systems sharing physical resources of a computing environment, but running in different partitions separated by a virtualization boundary comprises accumulating module information in a virtualization subsystem that directs the creation and management of the partitions. The accumulated module information is used across the virtualization boundary to manage the use of the software modules. Also, a method for managing software modules comprises making at least two operating systems aware that they are being hosted in a virtualized computing environment.

Abstract: The present invention is directed to systems and methods for improving access to non-volatile solid-state storage systems. Embodiments described herein provide a physical chunk number (PCN), or a physical page number (PPN), by which a controller can access the next available chunks (or pages) in a programming sequence optimized by concurrency. By incrementing the PCN, the controller can program consecutive chunks in the optimized programming sequence. In one embodiment, the programming sequence is determined at the time of initial configuration and the sequence seeks to synchronize data programming and data sending operations in subcomponents of the storage system to minimize contention and wait time. In one embodiment, the PCN includes an index portion to a superblock table with entries that reference specific blocks within the subcomponents in a sequence that mirrors the optimized programming sequence, and a local address portion that references a particular chunk to be programmed or read.

Abstract: One or more registers used to form an address usable in accessing storage are examined to determine if a zero address event has occurred in forming the address. In response to an indication that a zero address event has occurred in address formation, an alert is provided to the program using the address to access storage.

Abstract: Embodiments of the invention relate to reducing memory required to store an array of formulas and values corresponding to a formula-array. A set of formula-array representations is provided and arranged in a successive order. Each formula-array representation is evaluated for an associated memory requirement to support use thereof, followed by conversion to a structure of the formula-array representation at a successive level. Selection of the formula-array representation is determined based upon a minimal memory requirement from the formula-array representations in the order.

Abstract: A bus-protocol converting device includes: a command detecting unit that detects a command sent from an external-memory control device, connected to a primary bus, to a primary bus interface controller; a command converting unit that converts the detected command into a command to be sent from a secondary bus interface controller to an external memory device through a secondary bus; a status detecting unit that detects a status sent from the external memory device; a status converting unit that converts the detected status into a status to be sent from the primary-bus interface controller to the external-memory control device through the primary bus; and a data transfer controller that is provided between the primary bus interface controller and the secondary bus interface controller to perform data transfer between the external-memory control device and the external memory device through a DMA bus.

Abstract: A method for implementing on-demand configuration of a logical volume, wherein the method monitors the amount of available storage capacity of the logical storage volume and determines whether the available storage capacity exceeds a predetermined threshold, such as a percentage of available logical storage space. If the method determines that the storage capacity of the logical storage volume is nearing full capacity, the method determines whether configured physical storage space is available. If the method determines that configured physical storage space is available, the method then reconfigures the logical storage volume to include the configured physical storage space. If configured physical storage space is not available, the method locates unconfigured physical storage space, configures the available physical storage space, and reconfigures the logical volume using the configured physical storage space.

Abstract: An apparatus for abstract memory addressing. A processor for generating an abstract memory address. A base register for storing a base memory address. An adder for adding the base memory address to the abstract memory address and generating a physical address for a device memory. A pointer register for storing the physical address, wherein the pointer register is directly coupled to the device memory.

Abstract: An address controller includes a bit selector that receives a first portion of a requester id and selects a bit from a vector that identifies whether a requesting function is an SR-IOV device or a standard PCIe device. The controller also includes a selector coupled to the bit selector that forms an output comprised of either a second portion of the RID or a first portion of the address portion based on an input received from the selector and an address control unit that receives the first portion of the RID and the output and determines the LPAR that owns the requesting function based thereon, the address control unit providing the corrected memory request to the memory.

Abstract: A virtually indexed and physically tagged memory is described having a cache way size which can exceed the minimum page table size such that aliased virtual addresses VA within the cache way 12 can be mapped to the same physical address PA. Aliasing management logic 10 permits multiple copies of the data from the same physical address to be stored at different virtual indexes within the cache within given or different cache ways.

Abstract: Systems and methodologies are described that facilitate automatically generating interleaved addresses during turbo decoding. An efficient recursive technique can be employed in which layers of nested loops enable the computation of a polynomial and a modular function given interleaved parameters “a” and “b” from a look up table. With the recursive technique, interleaved addresses can be generated, one interleaved address per clock cycle which can maintain turbo decoding performance.

Abstract: A control system of a disk array including multiple data storage disks is provided. The control system includes a front-end circuit, a central processing unit and a back-end circuit. The front-end circuit is for receiving multiple packets corresponding to a first protocol from a network. The central processing unit has multiple cores. One of the cores is configured as a first dedicated core to interpret the packets corresponding to the first protocol into multiple first commands. The other non-dedicated cores are for processing the first commands and outputting multiple first access instructions. The back-end circuit is for translating the first access instructions to access the data storage disks.

Abstract: In a multinode storage system, a virtual disk associated with a storage device to be connected is created, and a slice of a connected storage device is allocated to one segment of the virtual disk. Next, one slice of data in the storage device to be connected is copied to the connected storage device. The rest of the data in the storage device to be connected is divided into slices, which are allocated to segments of the virtual disk. Then, metadata of the rest of the slices is written into a management information area in which copying of the data therefrom has been completed.

Abstract: An electronic apparatus and a booting method of the same are provided. The booting method of the electronic apparatus, including a non-volatile first storage unit storing a device initialization file and a device execution file, and a volatile second storage unit, includes: loading the device execution file from the first storage unit into the second storage unit at an initial booting; generating reference information about the loaded device execution file; maintaining power supplied to the second storage unit when the electronic apparatus is turned off; loading and executing the device initialization file from the first storage unit into the second storage unit at a rebooting; and executing the device execution file stored in the second storage unit with reference to the reference information.

Abstract: A method for second interleaving is disclosed. The method comprises: generating an interleaving address preset in an interleaving matrix for each input data, and writing the data into the interleaving matrix according to the interleaving address; initializing the interleaving address and reading out the data from the interleaving matrix according to the interleaving address; judging whether the reading operation on a column of data in the interleaving matrix is completed or not, if completed, then calculating the interleaving address of the next column in the interleaving matrix according to inter-column replacement rules; otherwise, obtaining the interleaving address by adding its own value to the column spacing; judging whether the reading operations on all data are completed or not, if completed, then the second interleaving ending; otherwise, returning to the step of reading out the data from the interleaving matrix according to the interleaving address, and repeating the above operation.

Abstract: A microprocessor architecture comprising a microprocessor operably coupled to a plurality of registers and arranged to execute at least one instruction. The microprocessor is arranged to determine a class of data operand. The at least one instruction comprises one or more codes in a register specifier that indicates whether relative addressing or absolute addressing is used in accessing a register. In this manner, absolute and relative register addressing is supported within a single instruction word.

Abstract: According to one embodiment, a switching apparatus includes a storage module, a setting module, a managing module and a reconstruction module. The storage module stores data pertaining to the switching function by dividing the data into a plurality of groups. The setting module sets, for each of the plurality of groups, a base address to be allocated by an operating system when the program is started up. The managing module records and manages the base address and data size information of each group when the program is terminated. The reconstruction module, when the program is started up, refers to the base address and the data size information recorded when the program is terminated last time, and reconstructs data in the virtual memory space for each of the plurality of groups based on a reference result.

Abstract: The present invention, in particular embodiments, provides methods, apparatuses and systems directed to providing a mechanism by which clients can transparently access remote file server appliances. Due to this, clients do not need to modify the pathnames in order to access the file servers.

Abstract: A semiconductor memory and a data processing system having hardware for carrying out a method for the improved internal monitoring of addressing circuits in semiconductor memories or in a data processing system, in which logic levels addressing lines are tapped off, the actually selected address or subaddress is represented by additional address bit lines, the actually accessed address/subaddress is recovered using the address bit lines, and the actually selected address/subaddress is compared with the applied address/subaddress, obtained from the additional address bit lines, in order to recognize an error in the addressing circuit.

Abstract: One embodiment of the present invention sets forth a system and method for supporting high-throughput virtual to physical address translation using compressed TLB cache lines with variable address range coverage. The amount of memory covered by a TLB cache line depends on the page size and page table entry (PTE) compression level. When a TLB miss occurs, a cache line is allocated with an assumed address range that may be larger or smaller than the address range of the PTE data actually returned. Subsequent requests that hit a cache line with a fill pending are queued until the fill completes. When the fill completes, the cache line's address range is set to the address range of the PTE data returned. Queued requests are replayed and any that fall outside the actual address range are reissued, potentially generating additional misses and fills.

Abstract: A hierarchical storage management (HSM) system and method. A system is provided comprising: a data usage monitor for extracting data object information from data objects in a hierarchical storage complex that is managed by a content management system; a data relationship repository for storing data object information, wherein the data object information includes relationship data for data objects in the hierarchical storage complex; and a system that analyzes the relationship data and makes data management action recommendations for the hierarchical storage complex.

Abstract: An electronic apparatus for recording data using a non-volatile memory is provided. The electronic apparatus includes a non-volatile memory and a controller. The non-volatile memory stores a plurality of sets of playing information of the electronic apparatus. The controller is coupled to the non-volatile memory for receiving an input data and transforming a data structure of the input data into a bitmapping data structure. The controller includes a bitmapping module that is capable of transforming the input data into data having at least one bit but less than one byte in a bitmapping manner.

Abstract: There is provided an externally readable memory for storing information in each memory address, and this memory is provided with an information refinement detection function; this memory comprises: an input means for entering first input data for comparing data items stored in the memory and second input data for comparing addresses in the memory, wherein the first and second comparison data are externally; means for determining matches/mismatches of both data items stored in the memory and addresses of the memory according to both of the input data provided by the input means, and further performing logic operations on both of the match/mismatch determination results; and means for outputting addresses with positive results of the logic operations. This memory may be applicable in a broad range of fields including intelligent information search as well as artificial intelligence.

Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

Abstract: A mechanism for a binary translator to emit code that will pre-generate information about a memory segment when a segment selector is assigned to a segment register. The binary translator emits code that will be executed when a memory access using that segment register is encountered and the emitted code will access the pre-generated information when evaluating the memory access request. Memory accesses, where a number of bytes being accessed is less than or equal to a predetermined value, are validated with a number of steps in the code emitted by the binary translator.

Abstract: Embodiments of an invention for generating multiple address space identifiers per virtual machine to switch between protected micro-contexts are disclosed. In one embodiment, an apparatus includes privileged mode logic, an interface, and memory management logic. The privileged mode logic is to transfer control of the processor among a plurality of virtual machines. The interface is to perform a transaction to fetch information from a memory. The memory management logic is to translate an untranslated address to a memory address. The memory management logic includes a storage location, a series of translation stages, determination logic, and a translation lookaside buffer. The storage location is to store an address of a data structure for the first translation stage. Each of the translation stages includes translation logic to find an entry in a data structure based on a portion of the untranslated address.

Abstract: In a non-volatile memory storage system such as a flash EEPROM system, a controller switches the manner in which data sectors are mapped into blocks and metablocks of the memory in response to host programming and controller data consolidation patterns, in order to improve performance and reduce wear. Data are programmed into the memory with different degrees of parallelism.

Abstract: A system is provided to ensure a timely secure data erase by determining whether allocating an additional tape drive would improve secure data erase performance by evaluating a quantity of physical volumes to be secure data erased, a maximum queued threshold, an average time to an erasure deadline and a minimum expiration threshold. An additional tape drive is allocated for the secure data erase process when it is determined that allocating an additional tape drive would improve secure data erase performance.

Abstract: A system and method for servicing translation lookaside buffer (TLB) misses may manage separate input and output pipelines within a memory management unit. A pending request queue (PRQ) in the input pipeline may include an instruction-related portion storing entries for instruction TLB (ITLB) misses and a data-related portion storing entries for potential or actual data TLB (DTLB) misses. A DTLB PRQ entry may be allocated to each load/store instruction selected from the pick queue. The system may select an ITLB- or DTLB-related entry for servicing dependent on prior PRQ entry selection(s). A corresponding entry may be held in a translation table entry return queue (TTERQ) in the output pipeline until a matching address translation is received from system memory. PRQ and/or TTERQ entries may be deallocated when a corresponding TLB miss is serviced. PRQ and/or TTERQ entries associated with a thread may be deallocated in response to a thread flush.

Abstract: Scheduling jobs for a plurality of devices includes assigning a run count value to each of the devices, scheduling a number of consecutive jobs up to the run count value, and decrementing the run count value according to the number of consecutive jobs scheduled. The run count value for a particular one of the devices may vary according to a total load of the particular one of the devices. The total load of the particular device may vary according to a number of pending jobs for the particular device and a total number of jobs for all devices coupled to a controller for the devices. The devices may be disk drive devices. Only one read job may be scheduled for a device irrespective of the run count value for the device and devices having pending read jobs may be given precedence over other devices. Multiple read jobs may be scheduled for a device according to the run count value and devices having pending read jobs may be given precedence over other devices.

Abstract: Incremental optimizations and modifications to a disk image can be made after the initial generation of the disk image. In the case of video games, publishers who have access only to a final game image can use the invention to make small improvements to the game disc image without the original game assets and without incurring the cost of generating an entirely new disc image. A mapping data structure represents physical locations of data on disk. The mapping data structure is modified with an editor, and the resulting modified layout is tested using an emulator that emulates interaction between a computer readable medium with the modified layout and computer hardware.

Abstract: Systems and methods for managing storage virtualization in a storage infrastructure are provided. The method comprises examining storage virtualization configurations across a data storage infrastructure having one or more data storage resources, such that configuration data associated with the storage virtualization configurations applied to the one or more data storage resources is stored in a configuration repository; analyzing the configuration data to detect storage virtualization policy inconsistencies across the data storage infrastructure; reporting potential problems associated with applying the storage virtualization configurations to said one or more data storage resources; and automatically implementing recommendations for corrective action to improve storage virtualization, in response to detecting the virtualization policy inconsistencies.

Abstract: The virtual volume is a virtual logical volume that conforms to Thin Provisioning, and is a logical volume configured from a plurality of virtual areas and used by a plurality of applications. In a case where the storage apparatus receives a write request comprising write-destination information for identifying a write-destination virtual area in the virtual volume, and, in addition, the write-destination virtual area is an unallocated virtual area, the storage apparatus selects a medium, which corresponds to the write to the write-destination virtual area and/or the identification information of the source of this write, from a plurality of media, which have different performances and which are each configured from two or more real areas, and allocates a real area from the selected medium to the write-destination virtual area.

Abstract: Embodiments of the present invention provide an apparatus, system, and method of generating an execution instruction. Some demonstrative embodiments my include generating an execution instruction of a predetermined executable format based on memory address data of a memory-access instruction representing a memory address. Other embodiments are described and claimed.

Abstract: The disclosed embodiments provide a system that uses unused bits in a memory pointer. During operation, the system determines a set of address bits in a address space that will not be needed for addressing purposes during program operation. Subsequently, the system stores data associated with the memory pointer in this set of address bits. The system masks this set of address bits when using the memory pointer to access the memory address associated with the memory pointer. Storing additional data in unused pointer bits can reduce the number of memory accesses for a program and improve program performance and/or reliability.

Abstract: A 3D object is represented by a descriptor, wherein a model of the 3D object is a 3D point cloud. A local support for each point p in the 3D point cloud is located, and reference x, y, and z axes are generated for the local support. A polar grid is applied according to the references x, y, and z axes a along an azimuth and a radial directions on an xy plane centered on the point p such that each patch on the grid is a bin for a 2D histogram, wherein the 2D histogram is a 2D matrix F on the grid and each coefficient of the 2D matrix F corresponds to the patch on the grid. For each grid location (k, l), an elevation value F(k, l) is estimated by interpolating the elevation values of the 3D points within the patches to produce the descriptor for the point p.

Abstract: A method for protecting the integrity of a set of memory pages to be accessed by an operating system of a data processing system, includes running the operating system in a virtual machine (VM) of the data processing system; verifying the integrity of the set of memory pages on loading of pages in the set to a memory of the data processing system for access by the operating system; in response to verification of the integrity, designating the set of memory pages as trusted pages and, in a page table to be used by the operating system during the access, marking non-trusted pages as paged; and in response to a subsequent page fault interrupt for a non-trusted page, remapping the set of pages to a region of the data processing system memory which is inaccessible to the virtual machine.

Abstract: A computer-implemented method, system and computer program product are presented for managing an Effective-to-Real Address Table (ERAT) and a Translation Lookaside Buffer (TLB) during test verification in a simulated densely threaded Network On a Chip (NOC). The ERAT and TLB are stripped out of the computer simulation before executing a test program. When the test program experiences an inevitable ERAT-miss and/or TLB-miss, an interrupt handler walks a page table until the requisite page for re-populating the ERAT and TLB is located.

Abstract: A counters array system comprises a memory device having a plurality of addressable memory locations for storing counter-values; a plurality of delta-counter devices. Each delta-counter device is operable to hold a maximum delta-value corresponding to a maximum number of occurrences of an event during a time duration between two counter scans controlled by a scan control unit. Each delta-counter device has an input connected to receive a signal from an event source corresponding to an occurrence of the event, and an output connected to provide a delta-value representing an accumulated number of occurrences of the event to a delta-count update circuit. The delta-count update circuit is connected to the memory device and the counter scan control unit, and being arranged to receive the delta-value and an address of a corresponding counter-value, read the counter-value from the memory device, and provide an updated counter-value incremented by the delta-value to the memory device.

Abstract: Write pointer generation units successively switch and indicate storage locations of data transmitted from a transmitter end LSI from plural buffers constituting FIFO circuits. A clock-step ring buffer delays a gated step signal to instruct an operation stop. When receiving the gated stop signal delayed by the clock-step ring buffer, the write pointer generation units stop switching instructions of the storage locations.

Abstract: A device, method, and system for switching library managers of a data library while maintaining data library storage devices online. A library manager accepts and executes data transaction commands for access to data residing on the storage devices of the data library. A transition manager module receives a directive to transition library management functions from a first library manager to a second library manager. The transition manager module stops the first library manager from accepting new data transaction commands while maintaining the storage devices online. The first library manager may execute previously accepted data transaction commands. The transition manager module suspends the library management functions of the first library manager and activates the library management functions of the second library manager. The storage devices of the data library may complete data transaction commands throughout the library manager transition.