Abstract: Enabling virtualization in a SAS expander is disclosed. For each SAS address to be virtualized through one or more physical or virtual Phy, a reference Phy associated with each SAS address is created within the expander. Next, a route table is generated that includes an entry for each of the SAS addresses being virtualized, each entry associated with one or more of the physical or virtual Phy through which the SAS address is being virtualized. With the route table so established, requests for a virtualized SAS address are routed to a particular one of the one or more physical or virtual Phy associated with the virtualized SAS address in the route table.

Abstract: A method, system and program product for managing assignment of virtual physical addresses. The method includes requesting, using a services function provided by a virtual machine operating system, a MAC address assignment for a real device and searching, in a MAC assignment table created and stored within a virtual memory space, to determine whether or not an explicit MAC address is assigned to the device. If an explicit MAC address is determined to be assigned to the device, retrieving the explicit MAC address upon verifying that the MAC address is not in use by another device and forwarding, using the services function, the explicit MAC address retrieved for assignment to the real device. If an explicit MAC address is not assigned to the device, retrieving an available MAC address from a MAC address pool table and forwarding the available MAC address retrieved for assignment to the real device.

Abstract: A method of rendering magnified pointing indicia including the steps of monitoring application program interface messaging and intercepting a call for a unique system pointer identifier. A stored collection of predefined vector shapes is accessed and from that a predefined vector shape from the collection is selected which is correlated to the current system pointer identifier. A convergence point may be established for maximum pointing indicia magnification in addition to a user-selectable desktop magnification level. The vector shape is scaled in synchronization with the desktop magnification level up to the convergence point whereby the vector shape is no longer scaled up once the convergence point is reached. The scaled vector shape is rasterized and displayed to an end user operating a computer.

Abstract: Various embodiments of the present invention provide systems and methods for out of order memory management. For example, a method for out of order data processing is disclosed. The method includes providing an out of order codeword memory circuit that includes a number of codeword memory locations in a codeword memory area and the same number of index values in an index area. Each of the index values corresponds to a respective one of the codeword memory locations. The methods further include receiving a data set; storing the data set to one of the codeword memory locations; receiving an indication that the data set stored in the one of the codeword memory locations has completed processing; and grouping an index value corresponding to the one of the codeword memory locations with one or more other index values corresponding to unused codeword memory locations.

Abstract: Multiple structured extension definitions can be obtained, each structured extension definition corresponding to one or more categories, and each structured extension definition being written in a software extension language. Data representing one or more registrations maintained in a format native to a registration store can be accessed, and this data analyzed based at least in part on the multiple structured definitions. In other aspects, a structured extension definition written in a software extension language is obtained. The registration store includes registrations stored in a format native to the registration store and different from the software extension language, and the registration store is modified based on the obtained structured extension definition.

Abstract: In a method for writing (S9, S11) of operating data (6) through a writing system (1, 2) comprising a central station (1) and at least one distribution station (2) to a portable data carrier (3) connected with the at least one distribution station (2) within the framework of a production of the data carrier (3) there is generated (S4, S5) an individual addressing for the data carrier (3) connected with the at least one distribution station (2), via which addressing the data carrier (3) is uniquely addressable system-wide upon the writing (S9, S11) of the operating data (6). In doing so, at least a part of the system-wide unique individual addressing can be generated (S4, S5) by the data carrier (3) itself or by the distribution station (2) with which the data carrier (3) is connected.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, manage metadata for virtual volumes. In some implementations, a method and system include defining multiple metadata blocks in a persistent storage, including information that links a virtual address space to the storage system, where the defining includes, for at least one of the multiple metadata blocks, determining multiple output addresses corresponding to the storage system, and writing the multiple output addresses and an identifier corresponding to the multiple metadata blocks in a metadata block in the persistent storage. In some implementations, a method and system include reading the multiple metadata blocks into the memory from the persistent storage, including identifying the metadata block based on the identifier; receiving an input address of the virtual address space; and obtaining a corresponding output address to the storage system using the multiple metadata blocks in the memory.

Abstract: In address generation processors, the start and the end of the processing for address generation need to be controlled in addition to controlling the processing for base address generation. A timing control unit manages control for address conversion on a clock cycle basis. The difference between the processing speed in the address generation processors and the processing speed in the address conversion circuit is absorbed by buffers.

Abstract: In an aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) generating a first command and associated address of a first type that does not indicate a rank of memory targeted by the first command; (2) determining whether the memory includes a plurality of ranks; (3) if the memory includes a plurality of ranks, employing the processor to update the address associated with the first command to indicate a memory rank targeted by the first command; (4) if the memory does not include a plurality of ranks, employing the processor to update the address associated with the first command to indicate the memory does not include a plurality of ranks; and (5) converting the first command and associated updated address to a second command and associated address that are employed to access the memory. Numerous other aspects are provided.

Abstract: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.

Abstract: A system and a method of accessing a memory are described. The system includes a memory, an interface configured to transfer data (e.g. a data packet), an aligner configured to receive the data and to generate aligned data, and a page buffer module configured to store the aligned data and, when the page buffer module is full with aligned data, transferring the aligned data to the memory. The method includes receiving data at an interface, aligning the data to generate aligned data, storing aligned data in a page buffer module configured to store aligned data for a write access and retrieved data from a read access, writing aligned data to a memory, and transferring retrieved data to the interface. Data can be transferred by the interface at a first rate and aligned data can be written to or retrieved from the memory at substantially the first rate.

Abstract: Disclosed herein is a memory controlling device including: an address converting section configured to convert a logical address included in a request issued from a plurality of clients into a physical address of a memory; a request dividing section configured to divide a converted request converted by the address converting section by a command unit for the memory on a basis of the physical address of the converted request; and an arbitrating section configured to perform arbitration on a basis of the physical address indicated in a divided request output from the request dividing section.

Abstract: A data processing system comprises multiple data processing nodes that communicate with one another using the FlexRay protocol. Each respective node works according to a respective schedule based on a repetitive sequence of cycles, each cycle having a sequence of time slots. Each node executes instructions, one per time slot, if any. The instructions are stored in a memory. Each instruction is identified by the relevant cycle number and time slot number in the relevant cycle. Accordingly, the combination of cycle number and slot number identify a memory address. Typical instructions appear more than once in the repetitive sequence of cycles for a node. This temporal pattern of occurrences of the same instruction at a node is used to modify the generation of the memory addresses, so that the same memory address is generated each time the instruction is needed. This makes efficient use of storage space.

Abstract: A software process receives a command initiating creation of a zone naming policy for automatically generating zone names in a storage area network. During creation of a zone naming policy, the software process receives selection of one or more format elements to be used in the zone naming policy. The one or more format elements each identify which corresponding at least one type of characteristic associated with a given zone in the storage area network shall be used to automatically generate a respective zone name for the given zone. For example, the format elements in a zone policy may identify how to generate a respective zone name using identifiers associated with resources associated with the zone. Accordingly, a network manager can create a zone naming policy for automatically generating zone names in a storage area network rather than having to manually create zone names for each created zone.

Abstract: A memory controller connected to memory includes: an address reception unit for receiving an address code externally input together with a command; and a command conversion unit for outputting to the memory an MRS command to change the internal settings of the memory based on the address code when the address code input together with a first command specifies an address space for which the memory is not implemented.

Abstract: A technique to speculatively assign a memory attribute. More specifically, embodiments of the invention include an architecture to assign and issue a speculative memory attribute based on a plurality of translation look-aside buffer (TLB) page attributes concurrently with the determination of the correct memory attribute, such that, in at least one case, determination of the correct memory attribute does not impact performance of a system in which at least one embodiment of the invention is included.

Abstract: An instruction-based programmable memory built-in self test (P-MBIST) circuit and an address generator thereof are provided. The P-MBIST circuit generates control signals according to the decoding of compact test instructions provided by an external automatic test equipment (ATE). The address generator generates memory addresses according to the control signals. The control signals and the memory addresses are sent to an embedded memory to perform the MBIST. The algorithm-specific design of the P-MBIST circuit and the address generator enables them to support multiple test algorithms at full clock speed and occupy smaller chip area.

Abstract: A first address is received and is used to determine a first address range. The first address range includes a second address range and a third address range. If the first address is in the second address range, a fourth address range is determined. The fourth address range is different from the first address range. Information is retrieved from a memory in response to determining that a second address is in the first address range or the fourth address range. If the first address is in the third address range, a fifth address range is determined. The fifth address range is different from the first address range. Other information is retrieved from the memory in response to determining the second address is in the first address range or the fifth address range.

Abstract: An address generator for providing an address to one of a linear block encoder and a soft linear block code decoder comprises a counter to count c, a position of a bit within a codeword of user data and to count r the codeword, where r=floor(c/74), An inner deinterleaver deinterleaves count c counted by the counter and to output c?. A shift circuit shifts the deinterleaved count c? by the inner deinterleaver in accordance with count r counted by the counter and to output c?.

Abstract: For recording or replaying in real-time digital high bandwidth video signals, e.g. HDTV, HD progressive or HD film capture signals, very fast memories are required. For storage of streaming HD video data NAND FLASH memory based systems could be used. Flash memory devices are physically accessed in a page oriented mode. According to the invention, the input data are written in a multiplexed fashion into a matrix of multiple flash devices. A list processing is performed that is as simple and fast as possible, and defect pages of flash blocks of single flash devices are addressed within the matrix architecture. When writing in a sequential manner, the data content for the current flash device page of all flash devices of the matrix is copied to a corresponding storage area in an additional memory buffer. After the current series of pages has been written without error into the flash devices, the corresponding storage area in an additional memory buffer is enabled for overwriting with following page data.

Abstract: A system and method of synchronizing a routing system having an active subsystem actively processing within the routing system and a standby subsystem. The method includes the steps of specifying an address or range of addresses of data to be synchronized within the routing system, detecting a write to main memory of the active subsystem, and comparing an address of the detected write to main memory of the active subsystem with the specified address or range of addresses. Next, the address and data of the detected write to main memory are stored in a First In First Out (FIFO) queue of the active subsystem if the address of the detected write to main memory matches the specified address or range of addresses. The address and data of the detected write to main memory are sent to the standby subsystem where the data and address are written to the main memory of the standby subsystem.

Abstract: A system, method, and module for reducing power states for storage devices and associated logical volumes are disclosed. In one form, a method of altering an operating state of a storage device can include detecting a request to access a first logical volume over an interval. The method can also include determining an association of a storage device to the first logical volume. The method can further include determining if the storage device is operably associated with a second logical volume, and altering an operating state of the storage device in response to detecting the request and determining the association with the second logical volume.

Abstract: A plurality of modes is provided for communicating between a host system and a peripheral storage system controller. A first communication mode may be selected from the plurality of communication modes based on a bit length required to communicate a physical address. During runtime, a switch from the first communication mode to a second communication mode may be performed in order to improve the efficiency of processing address requests at the storage system controller.

Abstract: A host computer communicates with field devices over a wireless network that includes a gateway and a plurality of wireless nodes. At least one of the field devices is associated with each wireless node, and each field device has a unique field device address. The host computer sends control messages to field devices using their field device addresses. The gateway translates the field device address of a control message to a wireless address of the wireless node with which the field device is associated. The gateway sends a wireless message over the network to the wireless node at the wireless address. The message contains the field device address so that, when the wireless message is received and opened, the control message from the host computer can be routed to the intended field device based upon the field device address.

Abstract: A method and apparatus for allocating storage addresses are disclosed. The method includes: receiving a storage address allocation request; searching a level-2 bitmap in a hierarchical bitmap in bidirectional mode; outputting an idle bit according to the result of searching in the level-2 bitmap; obtaining a storage address according to the output idle bit, and allocating the storage address. The apparatus includes: a first receiving module, configured to receive a storage address allocation request; a first searching module, configured to search a level-2 bitmap in a hierarchical bitmap in bidirectional mode for an idle bit, wherein the hierarchical bitmap includes N level-1 bitmaps and the level-2 bitmap; and an allocating module, configured to: obtain a storage address according to the output idle bit in the level-2 bitmap, and allocate the obtained storage address.

Abstract: A method according to one embodiment may include discovering at least one data block comprising logical block address information. The method may also include mapping logical block address information from a first domain into a second domain. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: A search device used to search for a search keyword from an object to be searched based on an automaton generated in accordance with the search keyword, includes: a first memory region; a second memory region; an information generation part that generates third information from first information and second information; a determination part; and a selection part, wherein: a first state corresponding to the first information is read from the first memory region; fourth information and a second state corresponding to the third information are read from the second memory region; the determination part determines whether or not fifth information including the first information and the second information matches with the fourth information; and the selection part selects the first state when not match in the determination and when matches in the determination, selects the second state.

Abstract: A system and a method of accessing a memory are described. The system includes a memory, an interface configured to transfer data (e.g. a data packet), an aligner configured to receive the data and to generate aligned data, and a page buffer module configured to store the aligned data and, when the page buffer module is full with aligned data, transferring the aligned data to the memory. The method includes receiving data at an interface, aligning the data to generate aligned data, storing aligned data in a page buffer module configured to store aligned data for a write access and retrieved data from a read access, writing aligned data to a memory, and transferring retrieved data to the interface. Data can be transferred by the interface at a first rate and aligned data can be written to or retrieved from the memory at substantially the first rate.

Abstract: The invention relates to a microprocessor system (60) for controlling and/or regulating at least partly security-critical processes, which system comprises two central processing units (1, 2) integrated into a chip housing, a first and a second at least one complete memory (7) on the first bus system, and check data in one or more check data memories, said data being related to data of the memory in the first bus system. The check data memory is smaller than the complete memory. The bus systems comprise comparative and/or driver components which facilitate data exchange and/or comparison of data between the two bus systems. The one or more check data memories are arranged on the first bus system. On the second bus system, neither a check data memory nor a memory safeguarding data of the memory on the first bus is used. The invention also relates to the use of the inventive microprocessor system in automotive control devices.

Abstract: One or more methods and/or systems of utilizing a memory external to an integrated circuit chip are presented. In one embodiment, the system comprises an Integrated circuit containing a logic circuitry, a one time programmable memory, a control processor, and a data interface. In one embodiment, a method of storing data into a memory comprises programming one or more bits of a one time programmable memory, generating an Identifier from the integrated circuit chip, and using the identifier to store data within the memory.

Abstract: A method and apparatus for metaphysical address space for holding lossy metadata is herein described. An explicit or implicit metadata access operation referencing data address of a data item is encountered. Hardware modifies the data address to a metadata address including a metaphysical extension. The metaphysical extension overlays one or more metaphysical address space(s) on the data address space. A portion of the metadata address including the metaphysical extension is utilized to search a tag array of the cache memory holding the data item. As a result, metadata access operations only hit metadata entries of the cache based on the metadata address extension. However, as the metadata is held within the cache, the metadata potentially competes with data for space within the cache.

Abstract: A disk formatter includes an address module for creating disk block address data corresponding to a disk sector of a disk drive. A sector write module initiates a physical mode write operation to the disk sector that incorporates the corresponding disk block address data.

Abstract: Embodiments in accordance with the present invention enable a disk drive of an address system to write data normally, wherein track groups of different track widths are discretely disposed on the storage medium in a same disk drive and the dimensional relationship among physical block addresses of a sector is valid for the dimensional relationship among logical block addresses. Track groups are managed corresponding to their respective track width in a disk drive and for disposing successively in a logical block address space the respective track groups located discretely on the physical block address space.

Abstract: Machine-readable media, methods, apparatus and system for managing sectors of a non-volatile memory are described. In some embodiments, a plurality of file segments may be written to a plurality of memory sectors (501), each memory sector of the plurality of memory sectors for each file segment of the plurality of file segments. Then, a plurality of flags may be searched from a first section of a sector table (502), each flag of the plurality of flags corresponding to the each file segment. A section may be selected from a second section and a third section of the sector table, wherein the section may be indicated by the plurality of flags (505,507). A plurality of physical addresses for the plurality of memory sectors may be written to the section (506,508).

Abstract: A processor includes at least one execution unit that executes instructions, at least one register file, coupled to the at least one execution unit, that buffers operands for access by the at least one execution unit, an instruction sequencing unit that fetches instructions for execution by the at least one execution unit, and an address generation accelerator. The address generation accelerator, responsive to an initiation signal received from the instruction sequencing unit, computes and outputs first and second effective addresses of operands of an operation.

Abstract: Techniques are provided for incrementally maintaining an XML index built to access XML data that is encoded in binary XML form. Rather than delete and reinsert index entries of all the nodes of a modified XML document, only the index entries of the affected nodes are modified. Consequently, the order key values stored in the index may become inconsistent with the current hierarchical locations of the nodes to which the order key values correspond. Techniques are described for resolving the inconsistencies, and for addressing additional problems that result when the XML index is path-subsetted.

Abstract: A system and method for generating a real address in data memory in response to a read/write request may include generating an access request to at least one of read and write data to a data memory. A connection ID may be received in association with the access request. This connection ID may include a buffer ID designating a buffer in data memory to which to access the data, and a port ID designating a pattern in which to access the data in the buffer. The method may further include translating the connection ID into a real address of the data memory, and accessing the data in the data memory at a location corresponding to the real address.

Abstract: Provided is a data processing method that may transmit, from a host unit including at least one host to a tiling unit, an input parameter and first data, tile the first data using a predetermined block interleaving scheme to convert the first data to second data, and store the converted second data in a memory unit. The data processing method may transmit, from a host unit including at least one host to an inverse tiling unit, an input parameter and a request signal for first data, extract second data corresponding to the request signal from the memory unit to store at least one second data that is tiled using a predetermined block interleaving scheme, and may transmit, to the host unit, the first data that is converted by inverse tiling the second data. Here, the first data may be in a data structure of a sequential scanning scheme.

Abstract: A task management system in an operating system executes a plurality of tasks in parallel. The task management system includes an execution standby state changer configured to generate a verifier of a task from data stored in a task address space and to store the generated verifier in a verifier storage area, when the task is changed from an executed state to an execution standby state; and an executed state changer configured to generate a verifier of the task from the data stored in the task address space and to verify matching of the generated verifier with the verifier of the task stored in the verifier storage area, when the task is changed from the execution standby state to the executed state.

Abstract: A data-processing unit comprises a register unit (10) comprising a register (20, R0-R3). The data-processing unit further comprises an address-generation unit (30) for generating a memory address to a memory unit (60). The address-generation unit (30) is adapted to fetch, from the register (20, R0-R3), a base address stored in a first portion (20a) of the register (20, R0-R3) and a first offset address stored in a second portion (20b) of the register (20, R0-R3). The base address and the first offset address are represented with fewer bits than the memory address. The address generation unit (30) is adapted to receive a first instruction and, in response thereto, generate a second offset address based on the first offset address, and generate the memory address by adding the base address and the second offset address. A method for generating the memory address is also disclosed.

Abstract: A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.

Abstract: In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write buffer configured to store data being written into the non-volatile memory cell array, and a write address buffer configured to store a write address associated with each data stored in the write buffer. An output circuit is configured to selectively output one of data read from the non-volatile memory array and data from the write buffer. A by-pass control circuit is configured to control the output circuit based on whether an input read address matches a valid write address stored in the write address buffer. An invalidation unit is configured to invalidate an address stored in the write address buffer if the stored write address matches an input write address.

Abstract: Methods and systems for assigning objects to processing units of a cluster of processing units are provided. In one implementation, the objects to be assigned may be sorted by size, which provides a sequence of objects. Starting with the first processing unit, objects may then be assigned in sequential order. This way the loading of the processing units may be balanced.

Abstract: According to one embodiment of the invention, a technique is provided for facilitating the relocation of data from a source page to a destination page in a computing system in which I/O devices may conduct DVMA transactions via an IOMMU. Before the relocation, it is determined whether any devices potentially are accessing the source page. If it is determined that a device potentially is accessing the source page, then the IOMMU's device driver (“bus nexus”) “suspends” the bus. The bus nexus allows any pending memory transactions to finish. While the bus is suspended, the kernel moves the contents of the source page to the destination page. After the kernel has moved the contents, the IOMMU's TLB is updated so that the virtual address that was mapped to the source page's physical address is mapped to the destination page's physical address. The bus nexus “unsuspends” the bus.

Abstract: The invention provides a multi-windows color adjustment system and method that divides the picture frame of a display screen into three or more windows so that the user can compare the color tones of the windows and then select the preferred window. The multi-windows color adjustment system includes a memory read/write controller coupled to an image data input for temporarily storing an input image data and executing read/write control, a window control unit coupled to the memory read/write controller for executing size, data flow and color tone controls of the windows, a line buffer coupled to the memory read/write controller and the window control unit for storing a line data, and a color adjustment unit coupled to the window control unit and the line buffer for executing the processing of color adjustment of the image data in the windows subject to the control of the window control unit.

Abstract: A filer converts a traditional volume to a flexible volume by: creating an aggregate on storage devices other than the storage devices of the traditional volume; on the aggregate, creating a flexible volume large enough to store metadata describing files residing on the traditional volume; on the flexible volume, creating metadata structures that describe the files of the traditional volume, except that the metadata indicates that data blocks and indirect blocks are absent and must be fetched from another location. As the filer handles I/O requests directed to the flexible volume, the filer calculates physical volume block number (PVBN) addresses where the requested blocks would be located in the aggregate and replaces the absent pointers with the calculated addresses. After the absent pointers have been replaced, the filer adds the storage devices of the traditional volume.

Abstract: A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.

Abstract: In a microprocessor having a load/store unit and prefetch hardware, the prefetch hardware includes a prefetch queue containing entries indicative of allocated data streams. A prefetch engine receives an address associated with a store instruction executed by the load/store unit. The prefetch engine determines whether to allocate an entry in the prefetch queue corresponding to the store instruction by comparing entries in the queue to a window of addresses encompassing multiple cache blocks, where the window of addresses is derived from the received address. The prefetch engine compares entries in the prefetch queue to a window of 2M contiguous cache blocks. The prefetch engine suppresses allocation of a new entry when any entry in the prefetch queue is within the address window. The prefetch engine further suppresses allocation of a new entry when the data address of the store instruction is equal to an address in a border area of the address window.

Abstract: A multiprocessor computer system has a plurality of first processors having a first addressable memory space, and a plurality of second processors having a second addressable memory space. The second addressable memory space is of a different size than the first addressable memory space, and the first addressable memory space and second addressable memory space comprise a part of the same common address space.

Abstract: A routing device and associated method for allocating the nodes of a multi-way trie of a forwarding routing table between two or more memory devices is disclosed. In the preferred embodiment, the routing device comprises a routing table for storing a plurality of routes in a multiway trie in a first memory for caching a first set of the plurality of trie nodes and a second memory for caching a second set of the plurality of trie nodes; and a route manager adapted to relocate one or more nodes of the second set from the second memory to the first memory such that the a utilization count for each of the nodes of the first memory is higher than each of the nodes of the second memory.