Abstract: Processing data samples may comprise partitioning the data samples in a first set of data bits and a second set of data bits and utilizing at least some of the first and second set of data bits while operating under a first condition. Only at least some of the first set of data bits may be utilized while operating under a second condition. The first condition may be a normal operating condition, while the second condition may be a performance restricted condition. The first set of data bits may be more significant bits and the second set of bits may be less significant bits. At least some of the first and second set of data bits may be utilized while bandwidth is available. Under the second condition, other values may be substituted for the data values from the second set that were not read in a read operation.

Abstract: The invention provides a communication control method for switching paths at high speed to switch storages without a special path switching means in a host computer, without stopping an application or without changing settings, and a device for realizing the same. The present computer system comprises a host computer 20, a storage devices 10 connected via a network 30 to the host computer 20, and a name server 40, wherein the host computer 20 has a function to search for an alternate path when a defect is discovered in a path used for connection with the storage 10, and the storage device 10 has a target communicating with the host computer 20 through a port, a registration change means for changing a registered address associated with the registration of a migration source target registered in the name server 40 to an address of a migration destination port, and a means for disconnecting all communication means established with the migration source target subsequent to the registration change process.

Abstract: A semiconductor integrated circuit includes a memory, a BIST main circuit and a BIST sub circuit. The BIST sub circuit is to generate a row address pattern or a column address pattern of the memory and includes a boundary address generation circuit for alternately generating a top address and a bottom address of the memory for at least one of the row address pattern and the column address pattern. The BIST main circuit is provided in common with a plurality of memories and the BIST sub circuit is individually provided corresponding to the memories. The boundary address generation circuit includes a top address memory unit for storing the top address and a top/bottom address generation unit for reading out the top address and alternately outputting the top address and the bottom address.

Abstract: A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.

Abstract: An adaptive buffer device includes a plurality of entries each including an address field and a record block, and a control unit for selectively setting each entry to one of a normal status and a transformed status. When the control unit sets a first one of the entries to the normal status, the address field thereof records a first address, and the record block thereof records data corresponding to the first address and data corresponding to addresses adjacent to the first address. When the control unit sets a second one of the entries to the transformed status, the control unit reconfigures the address field and the record block thereof into a plurality of units, each of which includes a second address, data corresponding to the second address, and data corresponding to addresses adjacent to the second address. In addition, an adaptive buffer method is also disclosed.

Abstract: Described are techniques for processing a data operation. A data operation is received at a data storage system. The data operation requests a modification of data stored in the data storage system. A first address is obtained that represents a starting address of the data operation. A calculation is performed representing a boundary condition of the starting address of the data operation. Based on the calculation, it is determined whether the data operation has a starting address which is properly aligned.

Abstract: A method allocates and assigns addresses to nodes in an ad hoc wireless network. A set of potential addresses of nodes in an ad hoc wireless network are defined as having N fields, in which the number of bits in each field is one or more bits. A subset of the set addresses is allocated initially as addresses to be assigned to nodes joining the network, in which each address has N-K fields, where 0<K<N. The size of the subset of addresses is increased adaptively by increasing the number of fields in each address in the subset.

Abstract: An apparatus, system, and method are disclosed for generating a name for a system of devices. An identifier identifies each component in the system. Once each component is identified, information such as the World Wide Name (WWN) of each component is stored in a database. Additional information such as the IP address of each component may also be stored within the database. A comparator then compares a name such as the WWN of each component and selects the name of a selected component based on specified parameters provided by a user. The selected name is modified and then assigned as an identifier of the entire system of devices. The system of devices is thus assigned a unique identifier that remains the same each time those components form a system of devices.

Abstract: Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency.

Abstract: Provided is a pattern matching device comprising memories. On each of the combinations of the values of an N number (N: a natural number) of pattern detection signals outputted from a circuited NFA (Non-deterministic Finite Automaton), the memories store both identifiers indicating patterns corresponding to effective patterns of the N number of pattern detection signals and flags indicating the definitions of the combinations, individually in addresses set according to the combinations. Further comprised are an address creating unit for determining the address of the memory corresponding to the combination of the values of the pattern detection signals, by using the combination of the values of the pattern detection signals outputted from the circuited NFA, and a read control unit for reading the identifiers and the flags stored in the address from the memories while incrementing the addresses determined by the address creating unit, until the flags take a specific value.

Abstract: A program of instruction words is executed with a VLIW data processing apparatus. The apparatus comprises a plurality of functional units capable of executing a plurality of instructions from each instruction word in parallel. The instructions from each of at least some of the instruction words are fetched from respective memory units in parallel, addressed with an instruction address that is common for the functional units. Translation of the instruction address into a physical address can be modified for one or more particular ones of the memory units. Modification is controlled by modification update instructions in the program. Thus, it can be selected dependent on program execution which instructions from the memory units will be combined into the instruction word in response to the instruction address.

Abstract: A system and method for employing memory forensic techniques to determine operating system type, memory management configuration, and virtual machine status on a running computer system. The techniques apply advanced techniques in a fashion to make them usable and accessible by Information Technology professionals that may not necessarily be versed in the specifics of memory forensic methodologies and theory.

Abstract: A computing environment maintains the integrity of data stored in system memory. The system has a memory management unit that maintains a plurality of real page numbers. The system also comprises an address bus in communication with the memory management unit. The address bus comprises a plurality of address lines, wherein a value of at least one address line is set by a real page number from the memory management unit. The system has an operating system that controls memory usage by controlling the real page numbers stored in said page table that is accessed by the memory management unit. At least one security feature such as data encryption is selectively applied to data stored in a page of said memory as enabled by a value of said address line set by said real page number.

Abstract: A storage apparatus is proposed for facilitating wireless communication between a computer device and one or more external portable electronic devices, or between those external devices. The storage apparatus includes a wireless transceiver for entering communication with any of one the devices. When the storage apparatus is communicating with any of the devices, it can transmit to that device any data stored in its memory for transmission to that device. Furthermore, the storage apparatus can receive from that device, and transmit to its memory, data to be relayed to another of the devices.

Abstract: A method of performing a direct memory access has the steps of selecting a peripheral device for performing a direct memory access through a direct memory access controller; providing a partial address by the peripheral device to the direct memory access controller; and forming the source or destination address by combining the partial address with selected bits from a source register within the direct memory access controller.

Abstract: A method for assigning element addresses in an automated data storage library includes determining if a data storage device, such as a tape cartridge, belongs to a particular host's cartridge assignment policy. If so, the data storage device is issued a virtual import/export element address taken from a set of non-common virtual import/export element addresses, if available. If no non-common address is available, then a common virtual import/export element address is assigned to the data storage device. If no addresses, either common or non-common, are available, then the data storage device is queued until an address becomes available.

Abstract: A method of assigning a multi-dimensional physical address to a tape-based data storage device is provided. The method includes accessing a first signal from a first communication path electrically coupled to a first tape-based data storage device, wherein the first signal indicates a physical position of the first tape-based data storage device with respect to a first axis. The method further includes accessing a second signal from a second communication path electrically coupled to the first tape-based data storage device, wherein the second signal is associated with a physical position of the first tape-based data storage device with respect to a second axis.

Abstract: Software transactional memory (STM) primitives are provided that allow the results of prior open calls to be used by subsequent open calls either as-is or through another STM primitive that consumes the results of the previous invocation. The STM primitives are configured to ensure that the address of a shadow copy representing a memory location will not changed across a wide range of operations and thereby enable re-use of the shadow copy.

Abstract: A method and apparatus for hybrid validation for a Software Transaction Memory (STM) is herein described. During execution of a transaction, when acquiring ownership of meta-data associated with a data element, the meta-data is updated with an ownership reference to a transaction to enable efficient subsequent ownership tests. However, during validation, for some conditions, meta-data is updated from the ownership reference to a write entry reference to enable efficient validation.

Abstract: A system for DMA transfer includes a DMA controller, a bus connected to the DMA controller, a bus interface connected to the bus, and a plurality of registers coupled to the bus via the bus interface, wherein the bus interface is configured to allocate the plurality of registers doubly to nonconsecutive addresses and consecutive addresses to allow the DMA controller to access the plurality of registers through the consecutive addresses.

Abstract: Devices, systems and methods of reduced-power memory address generation. For example, an apparatus includes: a carry save adder including at least a first set of adders and a second set of adders, wherein the adders of the first set are able to receive a first number of input bits and to produce a first number of outputs, and wherein adders of the second set are able to receive a second number of input bits and to produce the first number of outputs.

Abstract: To improve snapshot performance and copying performance on a block device level in a capacity of an allocation-on-use volume. Provided is a storage system coupled to a network includes one or more volumes constituted of a plurality of blocks. The plurality of blocks include a first block and a second block, and a physical storage area is allocated to at least one of the plurality of blocks. When it is judged that the physical storage area has not been allocated to the target first block of a received writing request, the storage system writes data to be written by the writing request in the first block without copying data stored in the first block to the second block.

Abstract: In a non-volatile memory storage system such as a flash EEPROM system, a controller switches the manner in which data sectors are mapped into blocks and metablocks of the memory in response to host programming and controller data consolidation patterns, in order to improve performance and reduce wear. Data are programmed into the memory with different degrees of parallelism.

Abstract: A computational system comprising a controller and a multi-plane solid state memory device accessible to the controller is disclosed. The controller is configured to provide access to a virtual block having a virtual block address that represents a first block from a first plane of the multi-plane solid state memory device and represents a second block from a second plane of the multi-plane solid state memory device.

Abstract: A processor for processing data is provided. The processor comprises an address generator, which is operative to generate an address based on a base address and a fractional step (?).

Abstract: A method for establishing a wireless connection between a first wireless device provided in a computer and a second wireless device, wherein group information that identifies the first wireless device is created and set for the first wireless device. The group information is transmitted to the second wireless device and is set for it. The first wireless device creates identification information that identifies the second wireless device with the group information to set it for the second wireless device. The first wireless device uses both of the group information and identification information to specify the second wireless device.

Abstract: A tape library apparatus comprising a plurality of FC drives. A host computer and a fiber channel switch portion are connected with an optical fiber cable through respective fiber channel interfaces. The fiber channel switch portion and FC drives are connected with respective optical fiber cables through respective fiber channel interfaces. A controlling portion and the FC drives are connected with respective -232C cables. Alias WWNNs and alias WWPNs of the FC drives are assigned by the controlling portion through respective RS-232C cables. Data reproduced by the FC drives and data supplied thereto are transmitted to and received from the host computer through, for example, respective optical fiber cables.

Abstract: A memory address decoding method for determining if a given address is located in one of a plurality of sections. Each section has a plurality of memory units and each memory unit has a unique corresponding address, the corresponding address using the binary system. The method includes making the corresponding address in a section with greater size smaller than the corresponding address in a section with smaller size, building a single bit-pattern for each section from all corresponding addresses, and comparing if at least one comparative bit of the given address matches those in any of the bit-patterns so as to determine the given address is located in one of the sections based on the comparison.

Abstract: A system and method to reduce external access to hypervisor interfaces in a computer system, thereby reducing the possibility of attacks. In a preferred embodiment, addresses for calls are used to fill a table, where the addresses are specifically selected for a requesting computer. For example, in one embodiment, a routine searches for the adapter type of a requesting computer and populates the table with calls specific to that type of adapter. Other types of calls are not put in the table. Instead, those calls are replaced by routines that will return an error. In other embodiments, the operating system type is used to determine what addresses are used to populate the table. These and other embodiments are explained more fully below.

Abstract: A method, apparatus and computer program product for file and folder scanning is presented. A host agent uses a scanning policy from a server, and scans the storage for the host system in accordance with the scanning policy. The host system then builds a data summary from the scanning results. The data summary is then provided to the server where it can be used to modify the storage on the host.

Abstract: Systems, methodologies, media, and other embodiments associated with externally trapping transactions are described. One exemplary system embodiment includes an external virtualization logic configured to be operably connected to a processor that does not include internal virtualization support. The example system may include a data store for storing a trappable memory address and a transaction that causes the external virtualization logic to produce a trap.

Abstract: Methods and systems are described for invoking an advice operation associated with a joinpoint. In one embodiment, the method includes identifying, based on a pointcut specification included in an aspect specification, a joinpoint in a machine code program component. The joinpoint includes a machine code instruction. The method further includes identifying, based on an advice specification included in the aspect specification, an advice operation included in a machine code program component. The method still further includes detecting an access to the machine code instruction in the joinpoint for execution by a processor. The method also includes invoking the advice operation in association with detecting the access to the machine code instruction.

Abstract: Computer-implemented systems and methods for handling access to one or more resources. Executable entities that are running substantially concurrently provide access requests to an operating system (OS). One or more traps of the OS are avoided to improve resource accessing performance through use of information stored in a shared locking mechanism. The shared locking mechanism indicates the overall state of the locking process, such as the number of processes waiting to retrieve data from a resource and/or whether a writer process is waiting to access the resource.

Abstract: According to one embodiment, an information processing apparatus includes an information processing apparatus main body, and a nonvolatile semiconductor memory drive which is accommodated in the information processing apparatus main body. The nonvolatile semiconductor memory drive includes a nonvolatile semiconductor memory, an address management table which is indicative of a correspondency between logical block addresses and physical addresses of the nonvolatile semiconductor memory, and a control module. The control module refers to the address management table in response to reception of a read request from the information processing apparatus main body, and outputs data of a predetermined value to the information processing apparatus main body in a case where the physical address corresponding to the logical block address, which is included in the read request, is not stored in the address management table.

Abstract: In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.

Abstract: A system for mapping information addresses in a memory. The system includes a memory wherein each byte is mapped to a plurality of unique addresses and a microprocessor for assigning at least one of the unique addresses to the information. The information can be program code fragments and/or data. Also disclosed is a method for mapping information addresses in a memory utilizing such a system. The method includes mapping each byte of memory into a plurality of unique addresses and assigning at least one of the unique addresses to the information.

Abstract: A portable data storage device includes a first storage unit having a data storing zone and a reserved zone for bad blocks in the first storage unit, and a second storage unit having a look-up table. The look-up table lists a number of configuration modes for the portable data storage device, each defining specific allocation sizes for the reserved zone and the data storing zone. The portable data storage device is configured to use a kth configuration mode. A method for dynamic memory management includes: i) determining a number of the bad blocks assigned to the reserved zone; ii) with reference to the look-up table, determining if this number is greater than a limit associated with the kth configuration mode; and iii) if so, reconfiguring the portable data storage device to use a (k+1)th configuration mode.

Abstract: A system and method to reduce external access to hypervisor interfaces in a computer system, thereby reducing the possibility of attacks. In a preferred embodiment, addresses for calls are used to fill a table, where the addresses are specifically selected for a requesting computer. For example, in one embodiment, a routine searches for the adapter type of a requesting computer and populates the table with calls specific to that type of adapter. Other types of calls are not put in the table. Instead, those calls are replaced by routines that will return an error. In other embodiments, the operating system type is used to determine what addresses are used to populate the table. These and other embodiments are explained more fully below.

Abstract: Disclosed is a multi-channel flash memory system formed by flash memories having pages divided into sectors and accessed by corresponding channels. An interface device is configured to access the flash memories via the channels by a unit of at least one sector, wherein the interface device divides an address into a plurality of addresses of sector unit and controls the divided addresses so as to be jumped by a given size.

Abstract: A Hard Disk Drive (HDD) is provided two FATs and two cluster sizes, a regular cluster and a “Supercluster”. In one example, each Supercluster is the size of four regular clusters. A second Supercluster FAT is added (FAT2) which works in a similar manner to the original FAT (hereinafter FAT1), but instead points to the next Supercluster in the chain. Since there are far fewer Superclusters than clusters, the Supercluster FAT (FAT2) can be stored in a cache memory. When data is streamed to and from the hard drive, it can be streamed to Superclusters and no seeks on the HDD to a FAT are required, as the FAT2 is cached in memory. Access time to and from the hard drive is decreased. The original cluster configuration is still supported. During lulls in system operation, the FAT2 data may be written to the drive and moreover, FAT1 data created and “flushed” to the hard drive.

Abstract: Methods and arrangements to insert values in hash tables are contemplated. Embodiments include transformations, code, state machines or other logic to insert values in a hash table stored in electronic memory by hashing a value to determine a home address of an entry in the hash table, the hash table having a plurality of entries, each entry comprising an address, a value, and a link. The embodiments may include determining whether there is a collision of the value with a value stored in the entry; inserting the value in the entry if there is no collision; and generating the addresses of further entries until an entry is found in which the value can be inserted if there is a collision. The embodiments may include generating a plurality of addresses of entries based upon the address of a previously generated entry.

Abstract: A control machine which uses a data amount stored in an FIFO as a trigger and allows a DMA transfer to be started according to a capacity of the FIFO allows a control machine for preparing for the DMA transfer to start to prepare a command and the like for the DMA transfer. The control machine for preparing for the DMA transfer issues the prepared command to a control machine for transferring DMA data, so that a process according to the command is started. At the time of the DMA transfer, a burden on a host CPU is reduced.

Abstract: The controller of the present invention includes an address management table that stores address information of valid data among the data stored in a flash memory, a status flag stored in the flash memory indicating that the data before rewriting and the data after rewriting are in process of rewriting, and a data rewriting process unit (the data management means) that changes the address information of the valid data from the data before rewriting to the data after rewriting at a given timing. It is thus possible to specify an area in process of rewriting even if the power supply is stopped in process of rewriting. It is also possible to judge the valid data when the process is restarted from the power off and erase the unnecessary data.

Abstract: Methods and systems for processing memory lookup requests are provided. In an embodiment, an address processing unit includes an instructions module configured to store instructions to be executed to complete a primary memory lookup request and a logic unit coupled to the instructions module. The primary memory lookup request is associated with a desired address. Based on an instruction stored in the instructions module, the logic unit is configured to generate a secondary memory lookup request that requests the desired address. In another embodiment, a method of processing memory lookups requests includes receiving a primary memory lookup request that corresponds to a desired memory address and generating a plurality of secondary memory lookup requests.

Abstract: Systems and methods for managing storage virtualization in a storage infrastructure are provided. The method comprises examining storage virtualization configurations across a data storage infrastructure having one or more data storage resources, such that configuration data associated with the storage virtualization configurations applied to the one or more data storage resources is stored in a configuration repository; analyzing the configuration data to detect storage virtualization policy inconsistencies across the data storage infrastructure; reporting potential problems associated with applying the storage virtualization configurations to said one or more data storage resources; and automatically implementing recommendations for corrective action to improve storage virtualization, in response to detecting the virtualization policy inconsistencies.

Abstract: Systems and methods for managing storage virtualization in a storage infrastructure are provided. The method comprises examining storage virtualization configurations across a data storage infrastructure having one or more data storage resources, such that configuration data associated with the storage virtualization configurations applied to the one or more data storage resources is stored in a configuration repository; analyzing the configuration data to detect storage virtualization policy inconsistencies and redundancies across the data storage infrastructure; and reporting potential problems associated with applying the storage virtualization configurations to said one or more data storage resources, in response to detecting the virtualization policy inconsistencies.

Abstract: A semiconductor memory device includes a data storage region which includes a plurality of unit data regions storing data, an information storage region which includes a plurality of unit information regions each storing information related to the data stored in associated one of the unit data regions, and an address generation circuit which generates an address designating one of the unit data regions and one of the unit information regions associated with each other.

Abstract: A network switching device comprises hardware address table storage space, a priority comparison mechanism, and an address table management mechanism. The hardware address table storage space having a number of entries therein. Each one of the entries within the hardware address table storage space includes respective information designating a priority of a respective source network address. The priority comparison mechanism is configured for comparing the priority designating information of the received packet with the priority designating information of at least a portion of the entries within the hardware address table storage space in response to determining that a number of entries within the hardware address table storage space is equal to a capacity of the hardware address table storage space.

Abstract: A system and method for address space layout randomization (“ASLR”) for a Windows operating system is disclosed. The address space layout includes one or more memory regions that are identified and then a particular implementation of the system randomizes the identified memory region in order to prevent any software vulnerabilities.

Abstract: A digital signal processor is adapted to a working RAM, which is capable of storing a plurality of data in a rewritable manner and whose storage area is divided into a plurality of sub-areas that are designated by addresses in read/write operations, wherein an operation circuit performs calculations on the data of the working RAM in accordance with a program, and wherein upon detection of a non-access event in which the program does not need to access the working RAM, a write circuit compulsorily writes ‘0’ into the working RAM with regard to each of the prescribed addresses of the prescribed sub-areas subjected to initialization, which are designated by address data. Thus, it is possible to actualize the selective initialization on the prescribed sub-areas within the working RAM without increasing the scale of the peripheral circuitry, without requiring complicated controls, and without increasing the overall processing time therefor.