Abstract: A translation table entry contains a change recording override field for controlling whether a change bit is to be set on a store or not. Each 4K byte block of main storage has an associated storage key comprising a change bit. The change recording override field controls whether change bit of the storage key associated with the desired 4K byte block of main storage is set to 1 for a store operation.

Abstract: According to one embodiment of the present invention, a method for operating a memory device that includes memory and a processing element includes receiving, in the processing element, a command from a requestor, loading, in the processing element, a program based on the command, the program comprising a load instruction loaded from a first memory location in the memory, and performing, by the processing element, the program, the performing including loading data in the processing element from a second memory location in the memory. The method also includes generating, by the processing element, a virtual address of the second memory location based on the load instruction and translating, by the processing element, the virtual address into a real address.

Abstract: The system utilizes a plurality of layers to provide a robust storage solution. One layer is the RAID engine that provides parity RAID protection, disk management and striping for the RAID sets. The second layer is called the virtualization layer and it separates the physical disks and storage capacity into virtual disks that minor the drives that a target system requires. A third layer is a LUN (logical unit number) layer that is disposed between the virtual disks and the host. By using this approach, the system can be used to represent any number, size, or capacity of disks that a host system requires while using any configuration of physical RAID storage.

Abstract: In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.

Abstract: A first virtual memory address is mapped to a real memory in a memory device, and a second virtual memory address is mapped to the real memory. Here, the first virtual memory address is authorized to modify data in the real memory and the second virtual memory address is not authorized to modify the data in the real memory.

Abstract: A method for assigning data in a plurality of physical storage resources for an information handling system is disclosed. The plurality of physical storage resources includes a first tier and a second tier with a lower performance and cost relative to capacity than the first tier. A tier manager hosted on the information handling system and in electronic communication with the plurality of physical storage resources is configured to: determine a seek distance value, operation rate, operation size value, and elapsed time value for each page; and calculate a relative randomness value for each page using the seek distance value, operation rate, operation size value, and elapsed time value determined for each page. A classification module may assign a physical location for each page such that the relative randomness value for each page in the first tier is greater than the relative randomness value for each page in the second tier.

Abstract: A technique provides multi-tenancy within a data storage apparatus. The technique involves dividing, by processing circuitry, storage units of the data storage apparatus into multiple groups of storage units. The technique further involves forming, by the processing circuitry, segregated slice pools from the multiple groups of storage units. Each segregated slice pool is formed from a different group of storage units. The technique further involves allocating, by the processing circuitry, slices from the segregated slice pools to mutually exclusive sets of virtual storage processors (VSPs) on the data storage apparatus. Each mutually exclusive set of VSPs operates as a separate tenant of the data storage apparatus.

Abstract: The present disclosure relates to a data storage device having a hypervolume accessible by a plurality of servers operating on two or more data storage systems, a first physical volume, associated with the hypervolume, located at a first data storage system, and a second physical volume, associated with the hypervolume, located at a second storage system. The hypervolume directs input/output (I/O) from the servers to a primary physical volume comprising either the first or second physical volume, and the primary physical volume may be changed, transparently to the servers, to the other of the first or second physical volume. The present disclosure, in another embodiment, relates to a method for moving operation of a storage device from one data storage location to a second data storage location. A hypervolume is used to redirect input/output (I/O) from the a plurality of servers from the one physical volume to another.

Abstract: A network file system includes at least one unmodified client and at least one unmodified physical file server (PFS). Each PFS has at least one file that is identified by an associated physical file handle (PFH). The network file system includes virtual file servers (VFSs) in a data path between the client(s) and the PFS(s). The network file system also includes a virtualized name space that is mapped to the PFS(s) and is provided to the client(s) by the VFS(s). The network file system further includes a virtualized ID space that is established in response to a request from a client. Within the ID space, each file is identified by a physical file handle (PFH) on a PFS. The PFH and PFS pair are mapped to provide a virtual file handle (VFH), and the map of the VFHs is allocated among the VFSs.

Abstract: A file system layout apportions an underlying physical volume into one or more virtual volumes (vvols) of a storage system. The underlying physical volume is an aggregate comprising one or more groups of disks, such as RAID groups, of the storage system. The aggregate has its own physical volume block number (pvbn) space and maintains metadata, such as block allocation structures, within that pvbn space. Each vvol has its own virtual volume block number (vvbn) space and maintains metadata, such as block allocation structures, within that vvbn space. Notably, the block allocation structures of a vvol are sized to the vvol, and not to the underlying aggregate, to thereby allow operations that manage data served by the storage system (e.g., snapshot operations) to efficiently work over the vvols. The file system layout extends the file system layout of a conventional write anywhere file layout system implementation, yet maintains performance properties of the conventional implementation.

Abstract: A data storage device includes a NAND flash memory, an executable interface and a controller for receiving, from a host, via the executable interface, an instruction to access the NAND flash memory at a virtual address and for translating the virtual address to a physical address of the volatile memory. Preferably, the controller also provides boot functionality to the host.

Abstract: A method may include receiving, at a first integrated circuit die, a memory transaction having an address from a second integrated circuit die. The method may further include determining, at the first integrated circuit die and based on the address, if the transaction is for the first integrated circuit die and, if so, translating the address. If transaction is for a third integrated circuit die, the transaction may be transmitted, without modification to the address, to the third integrated circuit die. The translation may be based upon a first table with each entry including a first address and a second translated address corresponding to the first address, and a second table with each entry including a first address and an indication if the transaction is to be forwarded without modification to the address.

Abstract: A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A size of a partition control area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster.

Abstract: A system and method of testing, during development, the operation of a clustered storage server system and its associated storage operating system. The system includes at least one host computer having a host operating system, and at least one virtual computer having a simulated storage operating system, at least one simulated disk, a simulated NVRAM, and a simulated flashcard within a guest operating system hosted by the host operating system. The simulated storage operating system represents an actual storage operating system. Facilities of the simulated storage operating system including the simulated disk, the simulated NVRAM, and the simulated flashcard are mapped onto corresponding facilities of the host operating system via virtualization components of the virtual computer so that the simulated storage operating system operates substantially the same as the actual storage operating system on low cost host hardware platforms.

Abstract: A second storage maps a migration source volume to a virtual volume of a migration destination volume according to storage virtualization technology. A host system including a host switches an access path from an access path to the migration source volume to an access path to the migration destination volume. The second storage executes copy processing of migrating, from the migration source volume to the migration destination volume, data in an assigned area of a virtual volume according to thin provisioning of the migration source volume based on the information contained in the first thin provisioning information in the first storage, and copying that data from the migration destination volume to a virtual volume according to thin provisioning of a copy destination volume in the second storage. The second storage associates the virtual volume of the copy destination volume with the migration destination volume in substitute for the original virtual volume.

Abstract: A computing system comprises at least a processing module, a main memory, a memory controller, and a plurality of memory components. A method begins by the memory controller receiving a memory access request regarding a data segment. The method continues with the memory controller interpreting the memory access request to determine whether an error encoding dispersal function of the data segment is applicable. The method continues with the memory controller identifying at least a threshold number of memories based on the memory access request, wherein the threshold number of memories includes at least one of the main memory and/or one or more of the plurality of memory components, when the error encoding dispersal function is applicable. The method continues with the memory controller addressing the at least a threshold number of memories to facilitate the memory access request.

Abstract: Methods for read after write forwarding using a virtual address are disclosed. A method includes determining when a virtual address has been remapped from corresponding to a first physical address to a second physical address and determining if all stores occupying a store queue before the remapping have been retired from the store queue. Loads that are younger than the stores that occupied the store queue before the remapping are prevented from being dispatched and executed until the stores that occupied the store queue before the remapping have left the store queue and become globally visible.

Abstract: Provided are techniques for allocating logical memory corresponding to a logical partition in a computing system; generating a S/W PFT data structure corresponding to a first page of the logical memory, wherein the S/W PFT data structure comprises a field indicating that the corresponding first page of logical memory is a klock page; transmitting a request for a page of physical memory and the corresponding S/W PFT data structure to a hypervisor; allocating physical memory corresponding to the request; and, in response to a pageout request, paging out available logical memory corresponding to the logical partition that does not indicate that the corresponding page is a klock page prior to paging out the first page.

Abstract: An apparatus includes a processor and a volatile memory that is configured to be accessible in an active memory sharing configuration. The apparatus includes a machine-readable encoded with instructions executable by the processor. The instructions including first virtual machine instructions configured to access the volatile memory with a first virtual machine. The instructions including second virtual machine instructions configured to access the volatile memory with a second virtual machine. The instructions including virtual machine monitor instructions configured to page data out from a shared memory to a reserved memory section in the volatile memory responsive to the first virtual machine or the second virtual machine paging the data out from the shared memory or paging the data in to the shared memory. The shared memory is shared across the first virtual machine and the second virtual machine. The volatile memory includes the shared memory.

Abstract: Provided are techniques for allocating logical memory corresponding to a logical partition in a computing system; generating, a S/W PFT data structure corresponding to a first page of the logical memory, wherein the S/W PFT data structure comprises a field indicating that the corresponding first page of logical memory is a klock page; transmitting a request for a page of physical memory and the corresponding S/W PFT data structure to hypervisor, allocating physical memory corresponding to the request; and, in response to a pageout request, paging out available logical memory corresponding to the logical partition that does not indicate that the corresponding page is a klock page prior to paging out the first page.

Abstract: A memory stores first configuration information indicating a plurality of logical storage areas and a first condition defining a state of a storage apparatus as a trigger for the storage apparatus to move data. A CPU acquires: a second condition defining a state of a computer as a trigger for the computer to move a first object, which is stored in a first logical storage area among the plurality of logical storage areas and performed by the computer, to another one of the plurality of logical storage areas; second configuration information associating the first object and the first logical storage area; first state information indicating a state of the plurality of logical storage areas; and second state information indicating a state of the first object. If a state of performing data movement is set, the CPU identifies a cause of the state of performing the data movement.

Abstract: A system and method is illustrated for identifying an Input/Output (I/O) driver module, using a hypervisor, to receive a read command to read a virtual memory page from a remote memory location. Further, the system and method includes reading the remote virtual memory page, using the I/O driver module, into a memory buffer managed by the I/O driver module. Additionally, the system and method includes storing the virtual memory page in the memory buffer to a persistent storage device. The system and method also includes identifying a remote super page, using a hypervisor, the remote super page including a remote sub page. Additionally, the system and method includes identifying a local super page, using the hypervisor, the local super page including a local sub page. Further, the system and method includes swapping the local sub page for the remote sub page, using the hypervisor, the swapping occurring over a network.

Abstract: In a data processing system capable of concurrently executing multiple hardware threads of execution, an intermediate address translation unit in a processing unit translates an effective address for a memory access into an intermediate address. A cache memory is accessed utilizing the intermediate address. In response to a miss in cache memory, the intermediate address is translated into a real address by a real address translation unit that performs address translation for multiple hardware threads of execution. The system memory is accessed with the real address.

Abstract: A data processing apparatus comprises a primary processor, a secondary processor configured to perform secure data processing operations and non-secure data processing operations and a memory configured to store secure data used by the secondary processor when performing the secure data processing operations and configured to store non-secure data used by the secondary processor when performing the non-secure data processing operations, wherein the secure data cannot be accessed by the non-secure data processing operations, wherein the secondary processor comprises a memory management unit configured to administer accesses to the memory from the secondary processor, the memory management unit configured to perform translations between virtual memory addresses used by the secondary processor and physical memory addresses used by the memory, wherein the translations are configured in dependence on a page table base address, the page table base address identifying a storage location in the memory of a set of des

Abstract: The storage system exports logical storage volumes that are provisioned as storage objects. These storage objects are accessed on demand by connected computer systems using standard protocols, such as SCSI and NFS, through logical endpoints for the protocol traffic that are configured in the storage system. Logical storage volumes are created from a logical storage container having an address space that maps to storage locations of the physical data storage units. Each of the logical storage volumes so created has an address space that maps to the address space of the logical storage container. A logical storage container may span more than one storage system and logical storage volumes of different customers can be provisioned from the same logical storage container with appropriate security settings.

Abstract: A method, computer program product and computer system for virtualizing an SAS storage adapter, so as to allow logical partitions of a computer system to share a storage device. The method, computer program product and computer system includes assigning a logical storage adapter to an operating system of each of the logical partitions; creating a mapping from each of the logical partitions to a set of logical blocks in the storage device; and configuring the logical storage adapter using a hypervisor, so that a select partition can access a select set of logical blocks that the select partition is allowed to access.

Abstract: A method and system for managing direct memory access (DMA) in a computer system without a host input/output memory management unit (IOMMU). The computer system hosts virtual machines and allows memory overcommit. The computer receives, from a guest operating system that runs on a virtual machine, a request for mapping a guest address to a bus address. The computer translates the guest address to a host address and pins a memory page containing the host address to keep the memory page in host memory. The host address is then returned to the guest operating system to allow a device to use the host address as the bus address for direct memory access (DMA) to a buffer managed by the guest operating system.

Abstract: A write request that includes a data object is processed. A hash function is executed on the data object, thereby generating a hash value that includes a first portion and a second portion. A hypervisor table is queried with the first portion, thereby obtaining a master storage node identifier. The data object and the hash value are sent to a master storage node associated with the master storage node identifier. At the master storage node, a master table is queried with the second portion, thereby obtaining a storage node identifier. The data object and the hash value are sent from the master storage node to a storage node associated with the storage node identifier.

Abstract: Systems and methods are provided for handling temporary data that is stored in a non-volatile memory, such as NAND flash memory. The temporary data may include hibernation data or any other data needed for only one boot cycle of an electronic device. When storing the temporary data in one or more pages of the non-volatile memory, the electronic device can store a temporary marker as part of the metadata in at least one of the pages. This way, on the next bootup of the electronic device, the electronic device can use the temporary marker to determine that the associated page contains unneeded data. The electronic device can therefore invalidate the page and omit the page from its metadata tables.

Abstract: An object of the present invention is to realize a highly reliable long-life information processor capable of high-speed operation and easy to handle. The processor includes a semiconductor device comprising a nonvolatile memory device including a plurality of overwritable memory cells, and a control circuit device for controlling access to the nonvolatile memory device. The control circuit device sets assignments of second addresses to the nonvolatile memory device independently of first addresses externally supplied, such that the physical disposition of part of the memory cells used for writing of first data to be written externally supplied is one of the first to (N+1)th of every (N+1) memory cells (N: a natural number) at least in one direction.

Abstract: The present invention relates to a coarse-grained reconfigurable array, comprising: at least one processor; a processing element array including a plurality of processing elements, and a configuration cache where commands being executed by the processing elements are saved; and a plurality of memory units forming a one-to-one mapping with the processor and the processing element array. The coarse-grained reconfigurable array further comprises a central memory performing data communications between the processor and the processing element array by switching the one-to-one mapping such that when the processor transfers data from/to a main memory to/from a frame buffer, a significant bottleneck phenomenon that may occur due to the limited bandwidth and latency of a system bus can be improved.

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Abstract: Systems and methods are provided for initiating wear leveling on block-aligned boundaries for non-volatile memories (“NVMs”), such as flash memory. In some embodiments, an electronic device including the NVM may suspend the programming of data upon reaching the end of a dynamic block. The electronic device may then perform wear leveling on a low-cycled block of the NVM. The electronic device may thus be configured to copy static data from the low-cycled block to another block of the NVM. After wear leveling has completed, the memory interface can program a second portion of the data to a new dynamic block of the NVM. This way, the electronic device can improve the efficiency of garbage collection. In addition, the electronic device can decrease the programming time for user generated writes, the wearing of the NVM, and overall power consumption.

Abstract: The storage system exports logical storage volumes that are provisioned as storage objects. These storage objects are accessed on demand by connected computer systems using standard protocols, such as SCSI and NFS, through logical endpoints for the protocol traffic that are configured in the storage system. To facilitate creation and management of logical storage volumes, special application programming interfaces (APIs) have been developed. The special APIs include commands to create a logical storage volume, bind, unbind, and rebind the logical storage volume, extend the size of the logical storage volume, clone the logical storage volume, and move the logical storage volume.

Abstract: A method for facilitating direct memory access in a computing system in response to a request to transfer data is provided. The method comprises selecting a thread for transferring the data, wherein the thread executes on a processing core within the computing system; providing the thread with the request, wherein the request comprises information for carrying out a data transfer; and transferring the data according to the request. The method may further comprise: coordinating the request with a memory management unit, such that virtual addresses may be used to transfer data; invalidating a cache line associated with the source address or flushing a cache line associated with the destination address, if requested. Multiple threads can be selected to transfer data based on their proximity to the destination address.

Abstract: Disclosed is a software architecture supporting a large-capacity collective memory layer in a multi-node system by using a remote direct memory access technique and a software virtualization technique and a computing system performing computing processing by using the architecture. In particular, provided is a software architecture including: a memory region managing module collectively managing a predetermined memory region of a node, a memory service providing module providing a large-capacity collective memory service to a virtual address space in a user process, and a memory sharing support module supporting sharing of the large-capacity collective memory of the multi-node system.

Abstract: A first processing unit and a second processing unit can access a system memory that stores a common page table that is common to the first processing unit and the second processing unit. The common page table can store virtual memory addresses to physical memory addresses mapping for memory chunks accessed by a job of an application. A page entry, within the common page table, can include a first set of attribute bits that defines accessibility of the memory chunk by the first processing unit, a second set of attribute bits that defines accessibility of the same memory chunk by the second processing unit, and physical address bits that define a physical address of the memory chunk.

Abstract: Systems and methods are provided for managing access to registers. In one embodiment, a system may include a processor and a plurality of registers. The processor and the plurality of registers may be integrated into a single device, or may be in separate devices. The plurality of registers may include a first set of registers that are directly accessible by the processor, and a second set of registers that are not directly accessible by the processor. The second set of registers may, however, be accessed indirectly by the processor via the first set of registers. In one embodiment, the first set of registers may include a register for selecting a register bank from the second set of registers, and a register for selecting a particular address within the register bank, to allow indirect access by the processor to the registers of the second set.

Abstract: Various embodiments disclosed herein including systems and methods for improving allocation of computing resources in a virtual machine (VM) environment. Embodiments maintain data relating to how VM image data is stored in storage devices and loaded into volatile memory such as random access memory (RAM). The data is then used to identify common content in the volatile memory that can be shared across VM instances. In some embodiments, multiple VM instances can share at least a portion of a single common VM image loaded into a shared volatile memory.

Abstract: A communication system is applicable to communications between client terminals and a server via the Internet, and includes a communication service unit creating a communication interface and a memory region in response to a communication request from a client terminal via the Internet, starting an application program in the created memory region in response to the communication request, sending contents of the started application program to the client terminal, and updating data in the memory region and sending the updated data to the client terminal when the communication request includes data updating.

Abstract: A system monitors data accesses to specific rows of memory to determine if a row hammer condition exists. The system can monitor accessed rows of memory to determine if the number of accesses to any of the rows exceeds a threshold associated with risk of data corruption on a row of memory physically adjacent to the row with high access. Based on the monitoring, a memory controller can determine if the number of accesses to a row exceeds the threshold, and indicate address information for the row whose access count reaches the threshold.

Abstract: A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component.

Abstract: Systems and methods for accessing a unified translation lookaside buffer (TLB) are disclosed. A method includes receiving an indicator of a level one translation lookaside buffer (L1TLB) miss corresponding to a request for a virtual address to physical address translation, searching a cache that includes virtual addresses and page sizes that correspond to translation table entries (TTEs) that have been evicted from the L1TLB, where a page size is identified, and searching a second level TLB and identifying a physical address that is contained in the second level TLB. Access is provided to the identified physical address.

Abstract: The present disclosure includes methods, devices, and systems for a logical address offset. One method embodiment includes detecting a memory unit formatting operation. Subsequently, in response to detecting the formatting operation, the method includes inspecting format information on the memory unit, calculating a logical address offset, and applying the offset to a host logical address.

Abstract: What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode indicating that a load page table entry address function is to be performed. The machine instruction contains an M field, a first field identifying a first general register, and a second field identifying a second general register. Based on the contents of the M field, an initial origin address of a hierarchy of address translation tables having at least one segment table is obtained. Based on the obtained initial origin address, dynamic address translation is performed until a page table entry is obtained. The page table entry address is saved in the identified first general register.

Abstract: Approaches are described for reducing the number of memory address cache (e.g. TLB) flushes that need to be performed during the course of performing virtualized I/O. A device driver residing in a host domain registers a CPU that will be used for I/O processing and requests the hypervisor to pre-allocate a number of slots in the page tables to map memory pages during I/O operations. Upon receiving an I/O operation, when memory needs to be mapped, the driver provides the hypervisor with information about the registered CPU. The hypervisor uses the pre-allocated page table slots to create the new mapping and flushes the TLB cache corresponding to the CPU that will perform the I/O. The TLB cache belonging to other CPUs may not need to be flushed. The host driver ensures that the mapped memory page is used exclusively on the CPU or performs additional TLB flushes.

Abstract: Incoming files are examined to detect abnormal files. The incoming files may be examined for a weak file structure, such as a weak file format structure or a weak file data structure, to detect abnormal files. A weak file structure includes file structures that do not conform to the file format of the file yet still loadable by a file loader of the file format. The incoming files may also be examined for suspicious loading in memory to detect abnormal files.

Abstract: A storage control apparatus includes a controller configured to control to convert an access to logical volume into an access to associated RAID group in response to an access to the corresponding virtual volume on the basis of access conversion information, monitor frequency of access to each of logical volumes, select a logical volume on the basis of the monitored frequency of access, move data stored in a RAID group corresponding to the selected logical volume to a different RAID group corresponding to a logical volume to be a data shift destination, and update the access conversion information to convert access to the RAID group corresponding to the selected logical volume into access to the different RAID group.

Abstract: A virtual EEPROM driver is simulated for a virtual switch. A write function may be written to a shared memory device and designated as a virtual EEPROM driver. The virtual EEPROM driver may be duplicated into a non-volatile memory providing availability during a boot process.

Abstract: A method processes input-output commands (IOs) in a storage system. The storage system receives an IO including first and second identifiers. The first identifier is used to direct the IO to the storage system. At the storage system, the method retrieves the second identifier from the IO and translates the second identifier to a logical storage volume identifier. Then, the method executes the IO on storage locations referenced by a logical storage volume corresponding to the logical storage volume identifier.