Virtual Addressing Patents (Class 711/203)
  • Patent number: 8914330
    Abstract: A mechanism is provided that aggregates data in a way that permits data to be deleted efficiently, while minimizing the overhead necessary to support bulk deletion of data. A request is received for automatic deletion of segments in a container and a waterline is determined for the container. A determination is made if at least one segment in the container falls below the waterline. Finally, in response to one segment falling below the waterline, the segment from the container is deleted. Each object has an associated creation time, initial retention value, and retention decay curve (also known as a retention curve). At any point, based on these values and the current time, the object's current retention value may be computed. The container system continually maintains a time-varying waterline: at any point, objects with a retention value below the waterline may be deleted.
    Type: Grant
    Filed: June 20, 2005
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Edward Gustav Chron, Frederick Douglis, Stephen Paul Morgan
  • Publication number: 20140365739
    Abstract: Embodiments relate to non-disruptive modification of a device mapper stack. Aspects include receiving the device mapper stack comprising a first device mapper layer having an active mapping table and creating a second device mapper layer having a copy of the active mapping table from the first device mapper layer. Aspects further include creating an inactive mapping table having a desired mapping logic in the first device mapper layer and suspending and resuming an operation of the first device mapper layer. Suspending and resuming causes the active mapping table of the first device mapper layer to be replaced with the inactive mapping table of the first device mapper layer.
    Type: Application
    Filed: June 7, 2013
    Publication date: December 11, 2014
    Inventor: Clement L. Dickey
  • Patent number: 8909898
    Abstract: Embodiments of copy equivalent protection using secure page flipping for software components within an execution environment are generally described herein. An embodiment includes the ability for a Virtual Machine Monitor (VMM), Operating System Monitor, or other underlying platform capability to restrict memory regions for access only by specifically authenticated, authorized and verified software components, even when part of an otherwise compromised operating system environment. In an embodiment, an embedded VM is allowed to directly manipulate page table mappings so that, even without running the VMM or obtaining VMXRoot privilege, the embedded VM can directly flip pages of memory into its direct/exclusive control and back. Other embodiments may be described and claimed.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: December 9, 2014
    Assignee: Intel Corporation
    Inventors: David Durham, Prashant Dewan
  • Patent number: 8909899
    Abstract: What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a frame management instruction is obtained which identifies a first and second general register. The first general register contains a frame management field having a key field with access-protection bits and a block-size indication. If the block-size indication indicates a large block then an operand address of a large block of data is obtained from the second general register. The large block of data has a plurality of small blocks each of which is associated with a corresponding storage key having a plurality of storage key access-protection bits. If the block size indication indicates a large block, the storage key access-protection bits of each corresponding storage key of each small block within the large block is set with the access-protection bits of the key field.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Dan F Greiner, Charles W Gainey, Jr., Lisa C Heller, Damian L Osisek, Timothy J Slegel, Gustav E Sittmann
  • Patent number: 8904146
    Abstract: Described are techniques for performing data storage system management. The data storage system is divided into a plurality of virtual partitions. A plurality of policy sets are specified where each of the policy sets includes one or more policies. One of the plurality of policy sets is assigned to each of the plurality of virtual partitions. Each of the plurality of policy sets includes an access control policy that assigns a portion of data storage of the data storage system as a resource for exclusive use in one of the plurality of virtual partitions that is assigned said each policy set.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: December 2, 2014
    Assignee: EMC Corporation
    Inventor: Gregory W. Lazar
  • Patent number: 8898384
    Abstract: A computerized data storage system includes at least one storage device including a nonvolatile writable medium; a cache memory and a data management controller and a storage port. The storage port is operable to receive a request to read data, and, in response to the request to read data, to send the data stored in the data storing area of the cache memory. The storage port is further operable to receive a request to write data, and, in response to the request to write data, to send the write data to the data storing area of the cache memory. The storage system further includes a thin provisioning controller operable to provide a virtual volume, and a capacity pool. The storage system further includes a data compression controller and a data decompression controller.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: November 25, 2014
    Assignee: Hitachi, Ltd.
    Inventor: Tomohiro Kawaguchi
  • Patent number: 8898493
    Abstract: This application includes systems and techniques that permit computers to remain accessible while in a low-power mode. In some implementations, the technique includes receiving at a first computer, via a computer network, information regarding a second computer transitioning to a low-power mode of operation; receiving at the first computer network communications designated for the second computer; processing at the first computer at least a portion of the network communications on behalf of the second computer without transitioning the second computer out of the low-power mode of operation, where the processing comprises processing the at least a portion of the network communications on behalf of the second computer within a virtual machine corresponding to the second computer; and initiating, via the computer network, a transition of the second computer out of the low-power mode of operation when at least one of the network communications satisfies a predetermined condition.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: November 25, 2014
    Assignee: The Regents of the University of California
    Inventors: Yuvraj Agarwal, Rajesh K. Gupta
  • Patent number: 8898671
    Abstract: Provide is a processor that can maintain a dependency relationship between a plurality of instructions and one read instruction. The processor comprises: a setting unit configured to set, when an instruction that exists at a location ensuring that writing into a memory area has been completed is executed, usage information indicating whether writing into the memory area has been completed such that the usage information indicates that writing into a memory area during execution of one thread has been completed; and a control unit configured to (i) perform execution of a read instruction to read data stored in the memory area when the usage information indicates that writing into the memory area during execution of the one thread has been completed, and (ii) suppress execution of the read instruction when the usage information indicates that writing into the memory area during execution of the one thread has not been completed.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: November 25, 2014
    Assignee: Panasonic Corporation
    Inventor: Hiroyuki Morishita
  • Patent number: 8898427
    Abstract: Embodiments relate to target buffer address region tracking. An aspect includes receiving a restart address, and comparing, by a processing circuit, the restart address to a first stored address and to a second stored address. The processing circuit determines which of the first and second stored addresses is identified as a same range and a different range to form a predicted target address range defining an address region associated with an entry in the target buffer. Based on determining that the restart address matches the first stored address, the first stored address is identified as the same range and the second stored address is identified as the different range. Based on determining that the restart address matches the second stored address, the first stored address is identified as the different range and the second stored address is identified as the same range.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: James J. Bonanno, Brian R. Prasky, Aaron Tsai
  • Patent number: 8898407
    Abstract: A method, article of manufacture, and apparatus for protecting data. In some embodiments, this includes taking a snapshot of a physical volume with a native snapshot program, determining which blocks have changed since a previous snapshot with a change block tracker, creating a child virtual container, populating the child virtual container with the changed blocks, and linking the child virtual container with a parent virtual container.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: November 25, 2014
    Assignee: EMC Corporation
    Inventors: Shankar Balasubramanian, Vladimir Mandic, Sriprasad Bhat Kasargod, Anand Raj
  • Patent number: 8897573
    Abstract: A system and an article of manufacture for de-duplicating virtual machine image accesses include identifying one or more identical blocks in two or more images in a virtual machine image repository, generating a block map for mapping different blocks with identical content into a same block, deploying a virtual machine image by reconstituting an image from the block map and fetching any unique blocks remotely on-demand, and de-duplicating virtual machine image accesses by storing the deployed virtual machine image in a local disk cache.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Han Chen, Alexei A. Karve, Minkyong Kim, Andrzej P. Kochut, Hui Lei, Jayaram Kallapalayam Radhakrishnan, Zhiming Shen, Zhe Zhang
  • Patent number: 8898397
    Abstract: Embodiments of the present invention provide an approach for memory and process sharing via input/output (I/O) with virtualization. Specifically, embodiments of the present invention provide a circuit design/system in which multiple chipsets are present that communicate with one another via a communications channel. Each chipset generally comprises a processor coupled to a memory unit. Moreover, each component has its own distinct/separate power supply. Pursuant to a communication and/or command exchange with a main controller, a processor of a particular chipset may disengage a memory unit coupled thereto, and then access a memory unit of another chipset (e.g., coupled to another processer in the system). Among other things, such an inventive configuration reduces memory leakage and enhances overall performance and/or efficiency of the system.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: November 25, 2014
    Inventor: Moon J. Kim
  • Patent number: 8898426
    Abstract: Embodiments relate to target buffer address region tracking. An aspect includes receiving a restart address, and comparing, by a processing circuit, the restart address to a first stored address and to a second stored address. The processing circuit determines which of the first and second stored addresses is identified as a same range and a different range to form a predicted target address range defining an address region associated with an entry in the target buffer. Based on determining that the restart address matches the first stored address, the first stored address is identified as the same range and the second stored address is identified as the different range. Based on determining that the restart address matches the second stored address, the first stored address is identified as the different range and the second stored address is identified as the same range.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: James J. Bonanno, Brian R. Prasky, Aaron Tsai
  • Patent number: 8898383
    Abstract: A storage controller calculates an access frequency of each logical disk; that is selects a first logical disk device of which the access frequency exceeds a first predetermined value, the first logical disk device being allocated to a first physical disk device; selects a second logical disk device which has the access frequency equal to or less than a second predetermined value, the second logical disk device being allocated to a second physical disk device; and reallocates the first and second logical device; and reallocates the first and second logical devices to the second and the first physical disk device, respectively.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: November 25, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Yasutomo Yamamoto, Akira Yamamoto, Takao Satoh
  • Patent number: 8893143
    Abstract: Methods and systems for implementing virtual processors are disclosed. For example, in an embodiment a processing apparatus configured to act as a plurality of virtual processors includes a first virtual program space that includes a first program execution memory, the first program execution memory including code to run a non-real-time operating system capable of supporting a one or more non-real-time applications, a second virtual program space that includes a second program execution memory, the second program execution memory including code to run one or more real-time processes, and a central processing unit (CPU) configured to operate in a first operating mode and a second operating mode, the CPU being configured to perform operating system and application activities using the first virtual program space for the first operating mode without using the second virtual program space and without appreciably interfering with the one or more real-time processes that are running in the second operating mode.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: November 18, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Timor Kardashov, Maxim Kovalenko, Arie Elias, Guy Ray
  • Patent number: 8886891
    Abstract: Accessing a shared buffer can include receiving an identifier associated with a buffer from a sending process, requesting one or more attributes corresponding to the buffer based on the received identifier, mapping at least a first page of the buffer in accordance with the one or more requested attributes, and accessing an item of data stored in the buffer by the sending process. The identifier also can comprise a unique identifier. Further, the identifier can be passed to one or more other processes. Additionally, the one or more requested attributes can include at least one of a pointer to a memory location and a property describing the buffer.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: November 11, 2014
    Assignee: Apple Inc.
    Inventors: Kenneth Christian Dyke, Jeremy Todd Sandmel, Geoff Stahl, John Kenneth Stauffer
  • Patent number: 8880843
    Abstract: A method for providing redundancy in a virtualized storage system for a computer system is provided. The method includes determining a first set of first logical addresses to provide a virtual storage volume. A redundancy schema is then selected to provide redundancy data for primary data stored in the first set of first logical addresses. A second set of second logical addresses is determined to provide logical storage for the primary data and for the redundancy data. The first set of first logical addresses and the second set of second logical addresses are then mapped and a set of physical storage addresses is selected from a set of physical storage elements. Mapping between the second set of second logical addresses and the set of physical addresses is then performed to provide physical storage for the primary data and the redundancy data stored in the virtual storage volume.
    Type: Grant
    Filed: February 10, 2010
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventor: Mark B. Thomas
  • Patent number: 8880797
    Abstract: A data de-duplication application de-duplicates redundant data on the primary storage read/write pathway of a virtualized server environment. The virtualized server environment comprises one or more server applications operating on a virtualization layer provided on a computer architecture that includes memory (e.g., RAM, cache memory) for temporarily storing data and storage (e.g., disk storage) for persistently storing data. The one or more server applications use the read-write pathway to read data into memory from storage and to write data to storage from memory. The de-duplication application identifies redundant data in memory, storage, or both, and replaces the redundant data with one or more pointers pointing to a single copy of the data. The de-duplication application can operate on fixed or variable size blocks of data and can de-duplicate data either post-process or in-line.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: November 4, 2014
    Assignee: EMC Corporation
    Inventor: Jedidiah Yueh
  • Patent number: 8880776
    Abstract: Systems and methods for accessing data at a data storage device are disclosed. In a particular embodiment, a method includes receiving cluster information at a controller of a data storage device, the data storage device further including a memory, the cluster information being associated with a data file that is stored at the memory. The method also includes accessing the cluster information to locate at least one region of the memory corresponding to the data file. The method further includes accessing data from the data file at the at least one region of the memory that is identified by the cluster information. Accessing of data from the data file includes the controller executing an internal application.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: November 4, 2014
    Assignee: Sandisk IL Ltd.
    Inventors: Eran Shen, Boris Dolgunov
  • Patent number: 8880825
    Abstract: A LUN is provided that can store multiple datasets (e.g., data and/or applications, such as virtual machines stored as virtual hard drives). The LUN is partitioned into multiple partitions. One or more datasets may be stored in each partition. As a result, multiple datasets can be accessed through a single LUN, rather than through a number of LUNs proportional to the number of datasets. Furthermore, the datasets stored in the LUN may be pivoted. A second LUN may be generated that is dedicated to storing a dataset of the multiple datasets stored in the first LUN. The dataset is copied to the second LUN, and the second LUN is exposed to a host computer to enable the host computer to interact with the dataset. Still further, the dataset may be pivoted from the second LUN back to a partition of the first LUN.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: November 4, 2014
    Assignee: Microsoft Corporation
    Inventors: Chris Lionetti, Robert Pike
  • Patent number: 8880812
    Abstract: A serial attached small computer systems interface (SAS) module includes a first port with (i) a first physical layer device and (ii) a first port control module. The first physical layer device communicates with a plurality of initiators. The first port control module comprises a first world wide number (WWN) table. The first WWN table comprises connection rates of the plurality of initiators during communication with the first physical layer device. Each of the connection rates is a last connection rate of a respective one of the plurality of initiators.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: November 4, 2014
    Assignee: Marvell International Ltd.
    Inventors: James A. Walch, Leon A. Krantz
  • Patent number: 8868883
    Abstract: An apparatus comprising an arbiter circuit, a translation circuit and a controller circuit. The arbiter circuit may be configured to generate one or more first control signals and a data write signal in response to an input signal and a read data signal. The translation circuit may be configured to generate a one or more second control signals in response to the one or more first control signals and the write address signal. The controller circuit may be configured to generate an address signal in response to the one or more second control signals.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: October 21, 2014
    Assignee: Ambarella, Inc.
    Inventors: Kathirgamar Aingaran, Leslie D. Kohn, Robert C. Kunz, Jenn-Yuan Tsai
  • Patent number: 8867537
    Abstract: A method for writing information to a first memory location controlled by a first computing system from a second memory location controlled by a second computing system that interfaces with the first computing system via a network connection is provided.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: October 21, 2014
    Assignee: QLOGIC, Corporation
    Inventor: Charles Micalizzi, Jr.
  • Patent number: 8868819
    Abstract: A management system is coupled to a storage system group including a scale-out storage system (a virtual storage system). The management system has storage management information, which includes information denoting, for each storage system, whether or not a storage system is a component of a virtual storage system. The management system, based on the storage management information, determines whether or not a first storage system is a component of a virtual storage system, and in a case where the result of this determination is affirmative, identifies, based on the storage management information, a second storage system, which is a storage system other than the virtual storage system that includes the first storage system, and allows a user to perform a specific operation only with respect to this second storage system.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: October 21, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Kyoko Miwa, Junichi Hara, Masayasu Asano
  • Publication number: 20140310499
    Abstract: A data services module performs log storage operations in response to requests by storing data on one or more storage devices, and appending information pertaining to the requests to a separate metadata log. A log order of the metadata log may correspond to an order in which the requests were received, regardless of the order in which data of the requests are written to the storage devices. The requests may correspond to identifiers of a logical address space. The data services module implements an any-to-any translation layer configured to map identifiers of the logical address space to the stored data. The virtualization module may include a metadata management module configured to checkpoint the translation layer metadata by, inter alia, appending aggregate, checkpoint entries to the metadata log. The data services module may leverage the translation layer between the logical identifiers and underlying storage locations to efficiently implement logical manipulation operations.
    Type: Application
    Filed: April 15, 2014
    Publication date: October 16, 2014
    Inventors: Swaminathan Sundararaman, Nisha Talagala, Sriram Subramanian
  • Patent number: 8856483
    Abstract: Virtual data stores may be sparsely provisioned by virtual data storage services in a manner that controls risk of implementation resource shortages. Relationships between requested data storage space size, data storage server capacity, allocated data storage space size and/or allocated data storage space utilization may be tracked on a per data store, per customer, per data storage server, and/or a per virtual data storage service basis. For each such basis, a set of constraints may be specified to control the relationships. The set of constraints may be enforced during implementation resource allocation, and by migration of data storage space portions to different implementation resources as part of a sparse provisioning load balancing. Sparse provisioning details may be made explicit to virtual data storage service customers to varying degrees including explicit, aggregate on a per customer basis, and aggregate on a per virtual data storage service basis.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: October 7, 2014
    Assignee: Amazon Technologies, Inc.
    Inventors: Roland Paterson-Jones, Sachin Jain, Tate Andrew Certain
  • Patent number: 8856436
    Abstract: According to one embodiment, a method for accessing host data records stored on a VTS system includes receiving a mount request to access at least one host data record on a VTS system, determining a number of host compressed data records per physical block on a sequential access storage medium, determining a PBID that corresponds to the requested at least one host data record, accessing a physical block on the sequential access storage medium corresponding to the PBID, and outputting the physical block without outputting an entire logical volume that the physical block is stored to. In another embodiment, a VTS system includes random access storage, sequential access storage, support for at least one virtual volume, a storage manager having logic for determining a PBID that corresponds to a SLBID, and logic for performing the above described method. Other methods are also described.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventor: Jonathan W. Peake
  • Patent number: 8850110
    Abstract: A virtual tape device includes a storage unit, an instruction unit, and a reading unit. The storage unit stores a plurality of logical volumes. The instruction unit receives a request for mounting a specified logical volume from an information processing apparatus. The instruction unit issues a mount instruction to both a physical tape device communicated to the virtual tape device and a virtual device communicated to the virtual tape device when the specified logical volume is not stored in the storage unit. The mount instruction instructs to mount the specified logical volume. The reading unit reads data of the specified logical volume to the storage unit from a device which outputs a mount completion notification first among both of the devices which have received the mount instruction.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: September 30, 2014
    Assignee: Fujitsu Limited
    Inventors: Fumio Matsuo, Katsuo Enohara, Takaaki Yamato, Nobuyuki Hirashima, Takashi Murayama
  • Patent number: 8850158
    Abstract: Disclosed is an apparatus for processing a remote page fault included in an optional local node within a cluster system configuring a large integration memory (CVM) by integrating individual memories of a plurality of nodes. The apparatus includes a memory including a CVM-map, a node memory information table, a virtual memory area, and a CVM page table, and a main controller mapping the large integration memory to an address space of a process when a user process requests memory allocation.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: September 30, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Eun Ji Lim, Gyu Il Cha, Young Ho Kim, Dong Jae Kang, Sung In Jung
  • Patent number: 8843725
    Abstract: Disclosed is a method and apparatus for a storage system comprising at least one mobile random access storage device capable of storing first or second data. At least one docking station is associated with an address wherein the address is identifiable by at least one host computer. A first and second sub-address is associated with the at least one docking station wherein the first and second sub-addresses are identifiable by the at least one host computer. The first sub-address corresponds to a first virtual device adapted for storing the first data on a first virtual media. The second sub-address corresponds to a second virtual device adapted for storing the second data on a second virtual media wherein the second virtual media is a different media type from the first virtual media.
    Type: Grant
    Filed: September 19, 2005
    Date of Patent: September 23, 2014
    Assignee: Spectra Logic Corporation
    Inventors: Matthew Thomas Starr, Richard Douglas Rector, Nathan Christopher Thompson
  • Publication number: 20140281350
    Abstract: A storage administrator may maintain location information in separate layers. A data storage system may identify the location of particular data by identifying the virtual location of data, such as the logical extent to which the data belongs. Object stores may maintain mappings of virtual locations to physical locations, such as mappings of extent identifiers to virtual storage objects and mappings of virtual storage objects to storage unit locations. When particular data is relocated to a new location, a storage administrator may update mappings used to translate virtual locations to physical locations, such as an extent-object mapping or an object-storage unit mapping. References to the virtual locations, such as references to logical extent identifiers, may not be updated in response to the relocation of data.
    Type: Application
    Filed: March 12, 2014
    Publication date: September 18, 2014
    Applicant: BRACKET COMPUTING, INC.
    Inventors: JASON A. LANGO, JOHN K. EDWARDS, NITIN MUPPALANENI
  • Publication number: 20140281312
    Abstract: A translation system can translate a storage request having multiple fields to a physical address using the fields as keys to traverse a map. By using a map table, multiple storage services can be condensed into a single map traversal. The map can be made of nodes that include one or more node entries. The node entries can be stored in a hashed storage area or sorted storage area of a node. A node entry of root nodes or inner nodes can include a link to a next node. A node entry of a leaf node can include a physical address. Using the request fields as a key to a node, a node entry can be determined. A pointer in a root node entry or inner node entry can be followed to a next node. A physical address in a leaf node can be the translation of the storage request.
    Type: Application
    Filed: November 26, 2013
    Publication date: September 18, 2014
    Applicant: Skyera, Inc.
    Inventors: Radoslav Danilak, Ladislav Steffko, Qi Wu
  • Publication number: 20140281355
    Abstract: Virtual storage pool creation is simplified by allowing a user to specify what devices to include in virtual storage pool by physical location. The virtual storage pool may be automatically generated based on the simplified user specifications. The user may specify the virtual pool configuration in a configuration file. A configuration application generates the virtual storage pool based on the configuration file. The configuration application utilizes the physical locations of block devices contained in the configuration file to generate the pool. As a result, virtual pool configuration and creation is automated, more efficient and is less error prone than previous methods that involve manually linking between physical device locations and computer generated names.
    Type: Application
    Filed: March 29, 2013
    Publication date: September 18, 2014
    Applicant: Silicon Graphics International Corp.
    Inventor: Tan Trieu
  • Publication number: 20140281363
    Abstract: Memory management includes maintaining a first mapping structure for each thread of a multi-threaded process. A second mapping structure is maintained for each core of a multi-core processing device. A global mapping structure for shared memory mappings is maintained. During thread context switches, copying thread context entries without modifying a page-mapping base address register of each core of the multi-core processing device.
    Type: Application
    Filed: August 23, 2013
    Publication date: September 18, 2014
    Inventors: Chen Tian, Daniel G. Waddington
  • Patent number: 8838933
    Abstract: Eager send data communications in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI composed of data communications endpoints that specify a client, a context, and a task, including receiving an eager send data communications instruction with transfer data disposed in a send buffer characterized by a read/write send buffer memory address in a read/write virtual address space of the origin endpoint; determining for the send buffer a read-only send buffer memory address in a read-only virtual address space, the read-only virtual address space shared by both the origin endpoint and the target endpoint, with all frames of physical memory mapped to pages of virtual memory in the read-only virtual address space; and communicating by the origin endpoint to the target endpoint an eager send message header that includes the read-only send buffer memory address.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Blocksome, Joseph D. Ratterman, Brian E. Smith
  • Patent number: 8838935
    Abstract: In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: September 16, 2014
    Assignee: Intel Corporation
    Inventors: Glenn Hinton, Madhavan Parthasarathy, Rajesh Parthasarathy, Muthukumar Swaminathan, Raj Ramanujan, David Zimmerman, Larry O. Smith, Adrian C. Moga, Scott J. Cape, Wayne A. Downer, Robert S. Chappell
  • Patent number: 8838931
    Abstract: Described are techniques for performing storage optimizations in a system. The optimizations may include a data movement optimization. First processing may be performed by a first component to determine whether to automatically perform the data movement optimization for devices included in one or more data storage systems. The first component may be external with respect to the data storage systems and may not be included in any of the data storage systems. As a result of performing the data movement optimization, a first portion of data is automatically moved from a first of the devices to a second of the devices. The first and second devices may have different performance classifications. Additionally, automated discovery processing may be performed to determine performance classifications for devices of the data storage systems and/or determine physical device dependencies.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: September 16, 2014
    Assignee: EMC Corporation
    Inventors: Marik Marshak, Amnon Naamad, Dan Aharoni, Sean Dolan, Ahmet Kirac
  • Patent number: 8838934
    Abstract: A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict. To improve memory performance destructive read operations are used when reading data but the data is written back into the physical memory in a later cycle.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: September 16, 2014
    Assignee: Memoir Systems, Inc.
    Inventors: Sundar Iver, Shang-Tse Chuang
  • Patent number: 8832411
    Abstract: Techniques described enable efficient swapping of memory pages to and from a working set of pages for a process through the use of large writes and reads of pages to and from sequentially ordered locations in secondary storage. When writing pages from a working set of a process into secondary storage, the pages may be written into reserved, contiguous locations in a dedicated swap file according to a virtual address order or other order. Such writing into sequentially ordered locations enables reading in of clusters of pages in large, sequential blocks of memory, providing for more efficient read operations to return pages to physical memory.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: September 9, 2014
    Assignee: Microsoft Corporation
    Inventors: Mehmet Iyigun, Yevgeniy Bak, Landy Wang, Arun U. Kishan
  • Patent number: 8832531
    Abstract: A method for data storage includes, in a memory that includes multiple memory blocks, specifying at a first time a first over-provisioning overhead, and storing data in the memory while retaining in the memory blocks memory areas, which do not hold valid data and whose aggregated size is at least commensurate with the specified first over-provisioning overhead. Portions of the data from one or more previously-programmed memory blocks containing one or more of the retained memory areas are compacted. At a second time subsequent to the first time, a second over-provisioning overhead, different from the first over-provisioning overhead, is specified, and data storage and data portion compaction is continued while complying with the second over-provisioning overhead.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: September 9, 2014
    Assignee: Apple Inc.
    Inventors: Ofir Shalvi, Naftali Sommer, Yoav Kasorla
  • Patent number: 8825966
    Abstract: An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface are some operations performed by the controller. The controller determines a width for a Data bus while assigning a target device address to each of the memory devices.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: September 2, 2014
    Assignee: MOSAID Technologies Incorporated
    Inventor: Peter Gillingham
  • Patent number: 8826440
    Abstract: Among other disclosed subject matter, a computer-implemented method includes initializing a first descriptor table and a second descriptor table. The first descriptor table is associated with a first permission level and the second descriptor table is associated with a second permission level that is different from the first permission level. The first descriptor table and the second descriptor table are associated with a hardware processor and initialized by an operating system kernel. The method also includes providing a memory address associated with the first descriptor table, in response to a descriptor table address request. The descriptor table address request is provided by a software process. The method also includes updating the second descriptor table, in response to an update request.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: September 2, 2014
    Assignee: Google Inc.
    Inventor: Eric R. Northup
  • Patent number: 8825983
    Abstract: Eager send data communications in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI composed of data communications endpoints that specify a client, a context, and a task, including receiving an eager send data communications instruction with transfer data disposed in a send buffer characterized by a read/write send buffer memory address in a read/write virtual address space of the origin endpoint; determining for the send buffer a read-only send buffer memory address in a read-only virtual address space, the read-only virtual address space shared by both the origin endpoint and the target endpoint, with all frames of physical memory mapped to pages of virtual memory in the read-only virtual address space; and communicating by the origin endpoint to the target endpoint an eager send message header that includes the read-only send buffer memory address.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Blocksome, Joseph D. Ratterman, Brian E. Smith
  • Patent number: 8819389
    Abstract: Administering registered virtual addresses in a hybrid computing environment that includes a host computer and an accelerator, the accelerator architecture optimized, with respect to the host computer architecture, for speed of execution of a particular class of computing functions, the host computer and the accelerator adapted to one another for data communications by a system level message passing module, where administering registered virtual addresses includes maintaining, by an operating system, a watch list of ranges of currently registered virtual addresses; upon a change in physical to virtual address mappings of a particular range of virtual addresses falling within the ranges included in the watch list, notifying the system level message passing module by the operating system of the change; and updating, by the system level message passing module, a cache of ranges of currently registered virtual addresses to reflect the change in physical to virtual address mappings.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Archer, Gary R. Ricard
  • Patent number: 8819388
    Abstract: Methods and apparatus for control of On-Die System Fabric (OSF) blocks are described. In one embodiment, a shadow address corresponding to a physical address may be stored in response to a user-level request and a logic circuitry (e.g., present in an OSF) may determine the physical address from the shadow address. Other embodiments are also disclosed.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: August 26, 2014
    Assignee: Intel Corporation
    Inventors: Zhen Fang, Mahesh Wagh, Jasmin Ajanovic, Michael E. Espig, Ravishankar Iyer
  • Patent number: 8812818
    Abstract: A method and apparatus creates and manages persistent memory (PM) in a multi-node computing system. A PM Manager in the service node creates and manages pools of nodes with various sizes of PM. A node manager uses the pools of nodes to load applications to the nodes according to the size of the available PM. The PM Manager can dynamically adjust the size of the PM according to the needs of the applications based on historical use or as determined by a system administrator. The PM Manager works with an operating system kernel on the nodes to provide persistent memory for application data and system metadata. The PM Manager uses the persistent memory to load applications to preserve data from one application to the next. Also, the data preserved in persistent memory may be system metadata such as file system data that will be available to subsequent applications.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: Eric Lawrence Barsness, David L. Darrington, Patrick Joseph McCarthy, Amanda Peters, John Matthew Santosuosso
  • Patent number: 8812775
    Abstract: A memory system, comprises a nonvolatile memory comprising multiple memory cells, and a memory controller configured to control respective cell levels of the memory cells by assigning a logical address of each memory cell to one of multiple address groups according to a frequency with which the logical address has been accessed, determining a cell level for each address group, and controlling each memory cell to have the cell level of the address group to which its logical address is assigned.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: August 19, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Byoung Geun Kim
  • Patent number: 8812449
    Abstract: A storage system having a plurality of storage devices including a first type storage device and a second type storage device, a reliability attribute and/or a performance attribute of the first type storage device being different from a reliability attribute and/or a performance attribute of the second type storage device. The storage system also has a control unit and managing a plurality of virtual volumes. If necessary, a storage area allocated to a first portion of a virtual volume of the plurality of virtual volumes is changed from a first type storage area of the plurality of first type storage areas to a second type storage area of the plurality of second type storage areas while another first type storage area of the plurality of first type storage areas is allocated to a second portion of the virtual volume.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: August 19, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Teiko Kezuka, Akira Murotani, Seiichi Higaki
  • Patent number: 8813076
    Abstract: Various systems, processes, and products may be used to update virtual machines. In particular implementations, a system, process, and product for updating virtual machines may include the ability to determine whether a change to a portion of an operating system for a virtual machine is available and identify a virtual machine using the operating system. The system, process, and product may also include the ability to determine when the virtual machine is modifiable and update the portion of the operating system for the virtual machine when it is modifiable.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ray W. Anderson, James A. Pafumi, Jacob J. Rosales, Vasu Vallabhaneni
  • Patent number: 8812776
    Abstract: A data writing method for a rewritable non-volatile memory module containing physical blocks is provided. The method includes: configuring virtual block address to map to at least a part of the logical blocks; receiving a write command which instructs to write file data to the first virtual block addresses, and the first virtual block addresses are mapped to first logical blocks of the at least the part of the logical blocks. The method further includes: writing the file data into the physical blocks mapped to a plurality of second logical blocks; determining whether a program failure is occurred during the writing period; and if the program failure is not occurred, the first virtual block addresses are remapped to the second logical block. Accordingly, the method can ensure the update completeness of the file data.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: August 19, 2014
    Assignee: Phison Electronics Corp.
    Inventor: Ching-Wen Chang