Abstract: Subject matter disclosed herein relates to performing concurrent memory operations.

Abstract: In a method to accelerate address translation into a physical address, a computer maps a virtual memory area with a large page, the virtual memory area including multiple virtual pages satisfying a predetermined condition and being handled in units of pages, the large page having a larger area than each of the virtual pages, and under a condition in which one of the virtual pages mapped with and included in the large page has a memory protection attribute different from a memory protection attribute of the other virtual page, sets physical memory protection information for protecting a physical page corresponding to the one virtual page having the different memory protection attribute.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

Abstract: Disclosed herein are a method, a system, and a computer-readable recording medium for providing distributed programming environment by using a distributed space. According to an aspect of the present invention, there is provided a method for processing data in distributed environment, the method including: generating a virtual space using resources provided by a plurality of nodes; and reading or writing data from or in the virtual space by a first application, wherein the data are mapped to a specific location region on the virtual space determined according to attributes of the data and the first application performs a reading operation or a writing operation for the data in the location region.

Abstract: A computer system with a memory containing a first guest operating system, including a first portion of the memory and a second guest operating system, including a second portion of the memory. The memory further contains an address exchange module for exchanging memory address handles, a data mover for moving data between the first and second portions of the memory, and an emulated input output memory management unit for controlling the data mover. Instructions in the memory cause the processor to: register accessible memory with the emulated input output memory management unit, write address handles to the address exchange module, read the address handles from the address exchange module, and move the data into the second portion of the memory.

Abstract: A system for identifying an exiting process and removing traces and shadow page table pages corresponding to the process' page table pages. An accessed minimum virtual address is maintained corresponding to an address space. In one embodiment, whenever a page table entry corresponding to the accessed minimum virtual address changes from present to not present, the process is determined to be exiting and removal of corresponding trace and shadow page table pages is begun. In a second embodiment, consecutive present to not-present PTE transitions are tracked for guest page tables on a per address space basis. When at least two guest page tables each has at least four consecutive present to not-present PTE transitions, a next present to not-present PTE transition event in the address space leads to the corresponding guest page table trace being dropped and the shadow page table page being removed.

Abstract: A storage system comprises a storage medium including a plurality of physical storage areas. The storage system controls a host computer to recognize a logical volume having a plurality of virtual storage areas, reads the data from the physical storage area assigned to the virtual storage area of the logical volume, determines whether or not the read data includes only the specific pattern data, and cancels the assignment of the physical storage area to the virtual storage area if the read data includes only the specific pattern data.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for managing metadata for pools of storage disks, are described. In some implementations, a system includes a processor, a memory and a storage system. The storage system contains a storage pool including multiple storage devices. Further, the storage system is configured to store in persistent storage associated with the storage pool a bitmap that is configured to indicate whether metadata blocks corresponding to one or more virtual volumes associated with the storage pool are free or occupied. In addition, the processor is configured to perform operations including accessing at least portions of the bitmap, and managing, based on information from the accessed portions, at least some of the metadata blocks stored in the persistent storage.

Abstract: A system and method for identifying from an address an appropriate target node and a location in that node that holds desired data related to that address is provided. The system and method includes a logical address generator that generates a logical address. The system and method includes a subspace index extraction module that extracts a subspace index from the logical address. The system and method includes a subspace configuration table that retrieves a plurality of parameters of the subspace index to locate the desired data.

Abstract: A system includes a source storage device, a target storage device, a host coupled to the source storage device and the target storage device, and a first migration device coupled to the source storage device and the target storage device. The first migration device includes a first virtual storage device. The first migration device is configured to migrate data from the source storage device to the target storage device, and the first virtual storage device is configured to receive write access requests for the data from the host during the data migration and send the access request to the source storage device and target storage device.

Abstract: A storage system and method is provided including physical storage devices controlled by storage control devices constituting a storage control layer operatively coupled to the physical storage devices and hosts. The storage control layer includes: a first virtual layer interfacing with the hosts, operable to represent a logical address space characterized by logical block addresses and available to said hosts and characterized by an Internal Virtual Address Space (IVAS) and operable, responsive to a configuration or I/O request addressed to the logical block addresses, to translate said logical block addresses into IVAS addresses; and a second virtual layer interfacing with the physical storage devices, operable to represent an available physical space to said hosts and characterized by a Physical Virtual Address Space (PVAS), addresses in PVAS having corresponding address in IVAS. The second virtual layer is operable to translate said respective IVAS addresses into addresses in the physical address space.

Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.

Abstract: A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component.

Abstract: A cache layer leverages a logical address space and storage metadata of a storage layer (e.g., storage layer) to cache data of a backing store. The cache layer maintains access metadata to track data characteristics of logical identifiers in the logical address space, including accesses pertaining to data that is not in the cache. The access metadata may be separate and distinct from the storage metadata maintained by the storage layer. The cache layer determines whether to admit data into the cache using the access metadata. Data may be admitted into the cache when the data satisfies cache admission criteria, which may include an access threshold and/or a sequentiality metric. Time-ordered history of the access metadata is used to identify important/useful blocks in the logical address space of the backing store that would be beneficial to cache.

Abstract: Space sharing between logical volumes is achieved through a technique that enables available storage space to be flexibly consumed and released by the logical volumes. Each logical volume is associated with an address tree that defines how available storage space is consumed by the logical volume. The technique involves receiving an input/output (I/O) operation that specifies a logical address within an address tree associated with the logical volume, parsing the address tree to identify an entry therein, if any, that is associated with the logical address, where the entry stores physical address information that is associated with the logical address. If it is determined that the entry exists, then one or more translated I/O operations are generated based on the physical address information and forwarded to a physical device manager to carry out the translated one or more I/O operations.

Abstract: The storage system exports logical storage volumes that are provisioned as storage objects. These storage objects are accessed on demand by connected computer systems using standard protocols, such as SCSI and NFS, through logical endpoints for the protocol traffic that are configured in the storage system. To facilitate creation and management of logical storage volumes, special application programming interfaces (APIs) have been developed. The special APIs include commands to create a logical storage volume, bind, unbind, and rebind the logical storage volume, extend the size of the logical storage volume, clone the logical storage volume, and move the logical storage volume.

Abstract: A mechanism for determining support criteria for shared libraries based on their priority levels is described. A method of embodiments of the invention includes extracting interface provisioning detail relating to interfaces associated with shared libraries provided by an operating system running on a computer system. The interfaces include application binary interfaces (ABIs). The method further includes detecting interface usage detail associated with the interfaces. The interface usage detail is based on a frequency at which one or more interfaces are used by one or more third-party software programs running on the operating system. The method further includes comparing the interface provisioning detail with the interface usage detail to determine an importance level of each shared library, and analyzing comparison results obtained from the comparison. The analyzing includes assigning a priority level to each shared library based on its importance level.

Abstract: Methods and apparatus for enhanced READ and WRITE operations in a FLASH-based solid state storage system that includes a logical to physical translation table where the logical to physical translation table can include entries associating a logical block address with one or more data identifiers, where each data identifier is associated with a data string.

Abstract: The storage system exports logical storage volumes that are provisioned as storage objects. These storage objects are accessed on demand by connected computer systems using standard protocols, such as SCSI and NFS, through logical endpoints for the protocol traffic that are configured in the storage system. Logical storage volumes are created from a logical storage container having an address space that maps to storage locations of the physical data storage units. Each of the logical storage volumes so created has an address space that maps to the address space of the logical storage container. A logical storage container may span more than one storage system and logical storage volumes of different customers can be provisioned from the same logical storage container with appropriate security settings.

Abstract: Systems and techniques relating to storage technologies are described. A described technique includes operating drives such as a solid state drive (SSD) and a disk drive, where the SSD and the disk drive are virtualized as a single logical drive having a logical address space, where the logical drive maps logical block addresses to the SSD and to the disk drive. The technique includes determining, based on a file to be written to the logical drive, a target logical address that corresponds to one of the SSD and the disk drive, and writing the file to the logical drive at the target logical address to effect storage on one of the SSD and the disk drive.

Abstract: A virtualized storage stack includes logical layers above the physical storage layer. Each logical layer allocates data blocks, and the data block allocation is propagated down to the physical storage layer. To facilitate contiguous storage, each layer of the virtualized storage stack maintains additional metadata associated with data blocks. For each data block, the metadata indicates whether the data block is free, provisioned and includes a tag that indicates when the data block was first written. Data blocks that were first written as part of the same write request share the same tag, and are mostly guaranteed to be physically co-located. Block allocations that reuse data blocks having the same tag are preferred. Such preference increases the likelihood of the blocks being contiguous in the physical storage as these blocks were allocated as part of the same first write.

Abstract: The system utilizes a plurality of layers to provide a robust storage solution. One layer is the RAID engine that provides parity RAID protection, disk management and striping for the RAID sets. The second layer is called the virtualization layer and it separates the physical disks and storage capacity into virtual disks that minor the drives that a target system requires. A third layer is a LUN (logical unit number) layer that is disposed between the virtual disks and the host. By using this approach, the system can be used to represent any number, size, or capacity of disks that a host system requires while using any configuration of physical RAID storage.

Abstract: Method and apparatus for mutably associating logical block addresses to physical blocks. A physical storage space is apportioned into one or more bands. A logical block address (LBA) from a logical space is assigned to one of the bands, and the LBA is mutably associated with a particular physical block (sector) at an associated physical block address (PBA) within the assigned band. Such mutable association preferably includes the writing of user data associated with the LBA to the associated physical sector. During a subsequent operation, user data associated with the LBA can be stored in a second physical sector in the assigned band. The physical storage space preferably comprises a magnetic recording medium, and some or all of the bands preferably utilize overlapping tracks. The logical space is preferably divided into sets of sequential LBAs, with non-adjacent sets assigned to the same band. Map data are used to track sector allocation status in each band.

Abstract: A mechanism for random cache line selection in virtualization systems is disclosed. A method includes maintaining a secondary data structure representing a plurality of memory pages, the secondary data structure indexed by a subset of each memory page, determining an index of a received new memory page by utilizing a subset of the new memory page that is a same size and at a same offset as the subset of each memory page, comparing the index of the new memory page with the indices of the secondary data structure for a match, utilizing a main data structure to perform a full page memory comparison with the new memory page if a match is found in the secondary data structure, and updating at least one of the size of the subset, the number of subsets, and the offsets of the subsets used to index the memory page.

Abstract: Methods and systems for load balancing read/write requests of a virtualized storage system. In one embodiment, a storage system includes a plurality of physical storage devices and a storage module operable within a communication network to present the plurality of physical storage devices as a virtual storage device to a plurality of network computing elements that are coupled to the communication network. The virtual storage device comprises a plurality of virtual storage volumes, wherein each virtual storage volume is communicatively coupled to the physical storage devices via the storage module. The storage module comprises maps that are used to route read/write requests from the network computing elements to the virtual storage volumes. Each map links read/write requests from at least one network computing element to a respective virtual storage volume within the virtual storage device.

Abstract: A semiconductor recording apparatus includes a logical-to-physical conversion table 115 showing correspondence between a physical address of said semiconductor memory and a logical address and writes the table to a flash memory 120. On receiving a write command issued from a host device 200, a block management section 114 selects a physical block with reference to said logical-to-physical conversion table, and updates said logical-to-physical conversion table. A logical-to-physical conversion table initializing section 117 updates a physical address corresponding to each logical address of the logical-to-physical conversion table into an invalid address. Accordingly the apparatus can render the number of rewrites of physical blocks uniform irrespective of writing conditions.

Abstract: Systems and methods for providing additional instructions for supporting efficient memory corruption detection in a processor. A physical memory may be a DRAM with a spare bank of memory reserved for a hardware failover mechanism. Version numbers associated with data structures allocated in the memory may be generated so that version numbers of adjacent data structures are different. A processor determines that a fetched instruction is a memory access instruction corresponding to a first data structure within the memory. For instructions that are not a version update instruction, the processor compares the first version number and second version number stored in a location in the memory indicated by the generated address and flags an error if there is a mismatch. For version update instructions, the processor performs a memory access operation on the second version number with no comparison check.

Abstract: A detection module selects logically adjacent first and second control areas of a cluster. The detection module further determines that the first and second control areas satisfy a migration test wherein the first control area has free space exceeding a free threshold, the free space is at least equal to a space requirement for each second control area control interval, and the second control area has fewer control intervals than a control interval threshold. In addition, a copy module copies each second control area control interval to the first control area in response to determining that the first and second control areas satisfy the migration test.

Abstract: A method and system for improving access to network content are described. Aspects of the disclosure minimize the delay between a navigation event and a network response by prerendering the next navigation event. For example, the method and system may predict a likely next uniform resource locator during web browsing to preemptively request content from the network before the user selects the corresponding link on a web page. The methods and systems describe a variety of manners for prerendering content and managing and configuring prerendering operations.

Abstract: The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands.

Abstract: A file system-aware SSD management system including an SSD management module that incorporates both file system information and information related to the underlying physical solid-state storage media into its operations is described. Also described are related methods for performing data management operations in a file system-aware manner. By incorporating both file system and physical storage information, the system may achieve various advantages over conventional systems, such as enhanced I/O performance, simplified SSD firmware, and extended SSD lifespan. Moreover, by moving solid-state management functions above the firmware level, the system may enable the simultaneous management of a pool of multiple SSDs.

Abstract: An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.

Abstract: A method, article of manufacture, and apparatus for protecting data. In some embodiments, this includes taking a snapshot of a physical volume with a native snapshot program, reading the snapshot block by block, creating a blank virtual container on a deduplicated virtual storage device, and populating the blank virtual container block by block based on reading the snapshot.

Abstract: Embodiments of an invention for generating multiple address space identifiers per virtual machine to switch between protected micro-contexts are disclosed. In one embodiment, a method includes receiving an instruction requiring an address translation; initiating, in response to receiving the instruction, a page walk from a page table pointed to by the contents of a page table pointer storage location; finding, during the page walk, a transition entry; storing the address translation and one of a plurality of address source identifiers in a translation lookaside buffer, the one of the plurality of address source identifiers based on one of a plurality of a virtual partition identifiers, at least two of the plurality of virtual partition identifiers associated with one of a plurality of virtual machines; and re-initiating the page walk.

Abstract: A single application can be executed across multiple execution environments in an efficient manner if at least a relevant portion of the virtual memory assigned to the application was equally accessible by each of the multiple execution environments. A request by a process in one execution environment can, thereby, be directed to an operating system, or other core software, in another execution environment and can be made by a shadow of the requesting process in the same manner as the original request was made by the requesting process itself. Because of the memory invariance between the execution environments, the results of the request will be equally accessible to the original requesting process even though the underlying software that responded to the request may be executing in a different execution environment. A similar thread invariance can be maintained to provide for accurate translation of requests between execution environments.

Abstract: Reliable storage for database management systems (DBMS) running on memory devices such as NAND type flash memory utilizes minimum I/O overhead and provides maximum data durability. A virtual page map is utilized between the flash memory and a page access component to record changes to the DBMS pages and prevent overwriting or data loss. There is no need for journaling and logging, and performance is increased by reducing the write and erase counts on the flash memory. The logical page numbers of the DBMS are mapped to physical page numbers in the page map, such that the virtual page map allocates an available page from the physical pages when changes to a page occur, and the updated information is stored in the allocated page. The allocated page number is mapped to the logical page number of the original page, thus maintaining a modified page representation while preventing physical in-place updates.

Abstract: The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range.

Abstract: Methods and apparatus are disclosed for managing access to data in a data storage system. For example, an apparatus comprises at least one processing platform associated with a distributed virtual infrastructure. The processing platform comprises at least one processing device having a processor coupled to a memory. The processing platform is operative to instantiate a meta data management process that is configured to provide at least one client process with information to allow the client process to perform one or more operations in accordance with one or more data storage devices through a storage area network. The information provided to the client process may comprise one or more data block descriptors. Each of the one or more data block descriptors may comprise path information for at least one of the data storage devices and an offset address in the at least one data storage device.

Abstract: A virtualized storage system comprises at least one host, at least one virtual array, a backend array and a management server. The host requests storage operations to the virtual array, and the virtual array executes storage operations for the host. The backend array, coupled to the virtual array, comprises physical storage for the virtual array. The management server determines the efficiency for the virtual array. The management server determines an input throughput data rate between the host and the virtual array based on storage operations between host and virtual array. The management server also determines an output throughput data rate, from the virtual array to the backend array. The output throughput data rate is based on the storage operations that require access to the backend array. The management server determines the efficiency of the virtual array using the input throughput data rate and the output throughput data rate.

Abstract: A method for making memory more reliable involves accessing data stored in a removable storage device by translating a logical memory address provided by a host digital device to a physical memory address in the device. A logical memory address is received from the host digital device. The logical memory address corresponds to a location of data stored on the removable storage device. A physical memory address corresponding to the local address is determined by accessing a lookup table corresponding to the logical zone.

Abstract: According to one embodiment, a method for a compiler to produce an executable module to be executed by a computer system including a main processor and active memory devices includes dividing source code into code sections, identifying a first code section to be executed by the active memory devices, wherein the first code section is one of the code sections and identifying data structures that are used by the first code section. The method also includes classifying the data structures based on pre-defined attributes, formulating, by the compiler, a storage mapping plan for the data structures based on the classifying and generating, by the compiler, mapping code that implements the storage mapping plan, wherein the mapping code is part of the executable module and wherein the mapping code maps storing of the data structures to storage locations in the active memory devices.

Abstract: In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.

Abstract: A processor includes a CPU core which executes a user program, and a data transfer apparatus. The CPU core stores a transfer request from a user program in a specific area of a main memory, in which the transfer request specifies the virtual addresses of a transfer source and a transfer destination in a memory space allocated to the user program. The data transfer apparatus refers to the specific area of the main memory and acquires a transfer request asynchronously to processing performed by the CPU core. The data transfer apparatus then identifies physical addresses corresponding to virtual addresses specified in the transfer request. After that, the data transfer apparatus transcribes original data stored in a storage area indicated by the physical address of the transfer source, to a storage area in a cache memory related to the virtual address or physical address of the transfer destination.

Abstract: A system, method, and computer-readable storage medium for mapping block numbers within a region to physical locations within a storage system. Block numbers are mapped within a region according to a fractal-based space-filling curve. If the region is not a 2k by 2k square, then the region is broken up into one or more 2k by 2k squares. Any remaining sub-region is centered within a 2k by 2k square, the 2k by 2k square is numbered using a fractal-based space-filling curve, and then the sub-region is renumbered by assigning numbers based on the order of the original block numbers of the sub-region.

Abstract: A method (and structure) of mapping a memory addressing of a multiprocessing system when it is emulated using a virtual memory addressing of another multiprocessing system includes accessing a local lookaside table (LLT) on a target processor with a target virtual memory address. Whether there is a “miss” in the LLT is determined and, with the miss determined in the LLT, a lock for a global page table is obtained.

Abstract: A device identifies, based on a program code instruction, an attempted write access operation to a fenced memory slab, where the fenced memory slab includes an alternating sequence of data buffers and guard buffers. The device assigns read-only protection to the fenced slab and invokes, based on the attempted write access operation, a page fault operation. When a faulting address of the attempted write operation is not an address for one of the multiple data buffers, the device performs a panic routine. When the faulting address of the attempted write operation is an address for one of the multiple data buffers, the device removes the read-only protection for the fenced slab and performs a single step processing routine for the program code instruction.

Abstract: In one embodiment, a system-on-chip (SoC) can be configured to receive a request from a master agent in a fabric coupled to the master agent, send a show command grant to the master agent responsive to selection of the request by the fabric, receive a command portion of a transaction corresponding to the request in the fabric and determine a target agent to receive the transaction based on the command portion, and thereafter send a transaction grant to the master agent for the transaction. Other embodiments are described and claimed.

Abstract: A processor unit removes, responsive to obtaining a new address, an entry from a memory of a type of memory based on a comparison of a performance of the type of memory to different performances, each of the different performances associated with a number of other types of memory.

Abstract: A data storage system and method are disclosed. The data storage system includes a first and a second memory and a memory control unit. The first memory is non-volatile, and the second memory is designed to store dynamic information of the first memory. The memory control unit includes a snapshot module, a recording module and a power-off recovery module, and is operative to handle the data loss of the second memory when an unexpected power-off occurs. When the power of the system is recovered, an initial address stored in the first memory by the snapshot module and link information and updating information recorded in the first memory by the recording module are obtained by the power-off recovery module to recovery the second memory.

Abstract: A method and apparatus for performing a function based on an executable code in response to receiving a request including function parameters are described. The executable code may be validated when loaded in a memory according to a signature statically signed over the executable code. A data location in the memory for storing the function parameters may be determined according location settings included inside the executable code. A target code location for storing a copy of the executable code may be determined based on the location parameters and the determined data location. A function is performed by executing the executable code from the target code location referencing the stored function parameters.