Abstract: A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device configured to store data in a non-volatile state, and a controller configured to control the non-volatile memory device. The controller calculates a new performance level, compares the calculated performance level with a predetermined reference, and determines the calculated performance level as an updated performance level according to the comparison result.

Abstract: A method, apparatus, and a storage system are provided for implementing enhanced indirection update for indirected storage devices. A novel remapping command generated by a host is used to store indirection data. The remapping command enables remapping of a set of Logical Block Addresses (LBAs) to a different set of LBAs. The remapping command includes a source LBA, length and a destination LBA.

Abstract: A storage system has a plurality of flash packages, and a storage controller for receiving a write request from a host and sending a write-data write request based on data conforming to this write request to a write-destination flash package. A virtual capacity, which is larger than the physical capacity of the flash package, is defined in the storage controller. The storage system compresses the write data, and writes the compressed write data to the write-destination flash chip.

Abstract: A distributed storage management apparatus includes a monitoring unit configured to monitor a request pattern of each storage node of a plurality of storage nodes configured to distributively store data and at least one replica of the data; a group setting unit configured to receive a request and classify the plurality of storage nodes into a safe group and an unsafe group based on the monitored request pattern of each storage node; and a request transfer unit configured to transfer the received request to the safe group.

Abstract: A semiconductor storage device (SSD) and a method of throttling performance of the SSD are provided. The method can include includes gathering at least two workload data items related with to a workload of the semiconductor storage device, estimating the workload using the at least two workload data items, and throttling the performance of the semiconductor storage device according to the estimated workload. Accordingly, a workload that the semiconductor storage device will undergo can be estimated.

Abstract: Mixed-granularity higher-level redundancy for NVM provides improved higher-level redundancy operation with better error recovery and/or reduced redundancy information overhead. For example, pages of the NVM that are less reliable, such as relatively more prone to errors, are operated in higher-level redundancy modes having relatively more error protection, at a cost of relatively more redundancy information. Concurrently, blocks of the NVM that are more reliable are operated in higher-level redundancy modes having relatively less error protection, at a cost of relatively less redundancy information. Compared to techniques that operate the entirety of the NVM in the higher-level redundancy modes having relatively less error protection, techniques described herein provide better error recovery. Compared to techniques that operate the entirety of the NVM in the higher-level redundancy modes having relatively more error protection, the techniques described herein provide reduced redundancy information overhead.

Abstract: A data programming method for a data programming device having a non-volatile memory and a volatile memory, the method comprising determining whether data exceeds one page; if the data does not exceed one page and is insufficient for one page, storing the data into the volatile memory; determining whether next data is to be programmed into the same page as the data stored in the volatile memory; if the next data is to be programmed into the same page as the data stored in the volatile memory, programming the data and the next data into the non-volatile memory.

Abstract: A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device, and a controller configured to receive a write command from a host and program and to write data received from the host to the non-volatile memory device in response to the write command. The controller inserts idle time after receiving the write data from the host and/or after programming the write data to the non-volatile memory device.

Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.

Abstract: A mechanism is provided for enabling throttling on average write throughput instead of peak write throughput for solid-state storage devices. The mechanism assures an average write throughput within a range but allows excursions of high throughput with periods of low throughput offsetting against those of heavy usage. The mechanism periodically determines average throughput and determines whether average throughput exceeds a high throughput threshold for a certain amount of time without being offset by periods of low throughput.

Abstract: A method comprises receiving a request to access a memory array having one or more memory erase units with a data area of flash array and with a specific amount of memory which offers small data programming capability, the specific amount of memory configured to be erased simultaneously or sequentially with a main memory block of the memory array; and if the memory access request includes programming small data, then providing access to the specific amount of memory, or if the memory access request does not include programming small data, then providing access to the data area of flash array. The size of the specific amount of memory may be pre-defined, and the specific amount of memory may be a different memory technology.

Abstract: An apparatus, system, and method are disclosed for storage space recovery. A storage division selection module selects a first storage division for recovery. The first storage division comprises a portion of solid-state storage in a solid-state storage device. A data recovery module reads valid data from the first storage division in response to selecting the first storage division for recovery. The data recovery module stores the valid data in a second storage division of the solid-state storage device. The data recovery module passes the valid data through at least a portion of a write data pipeline for the solid-state storage device without passing the valid data to a host device and/or without routing the valid data outside of a solid-state storage controller for the solid-state storage device.

Abstract: In one aspect, a method of writing data in a flash memory system is provided. The flash memory system forms an address mapping pattern according to a log block mapping scheme. The method includes determining a writing pattern of data to be written in a log block, and allocating one of SLC and MLC blocks to the log block in accordance with the writing pattern of the data.

Abstract: A method uses a record of I/O priorities in a determination of a storage medium of a hybrid storage system in which to store a file. The method maintains the record of I/O priorities by assigning an I/O temperature value to each request for access to the file based upon an I/O priority level of the process making the request. The method marks the file as hot if the file temperature value is greater than a threshold value. The method stores files marked as hot in a lower latency storage medium of the hybrid storage medium.

Abstract: A solid state disk (SSD) caches disk-based volumes in a heterogeneous storage system, improving the overall storage-system performance. The hottest data blocks are identified based on two factors: the frequency of access, and temporal locality. Temporal locality is computed using a logarithmic system time. IO latency is reduced by migrating these hottest data blocks from hard-disk-based volumes to the solid-state flash-memory disks. Some dedicated mapping metadata and a novel top-K B-tree structure are used to index the blocks. Data blocks are ranked by awarding a higher current value for recent accesses, but also by the frequency of accesses. A non-trivial value for accesses in the past is retained by accumulating the two factors over many time spans expressed as a logarithmic system time. Having two factors, access frequency and the logarithmic system time, provides for a more balanced caching system.

Abstract: A method includes decreasing a programming step size from a first value to a second value for a block of a memory device. The programming step size is decreased at least partially based on determining that an error count corresponding to the block satisfies a threshold.

Abstract: Various embodiments of the present disclosure are generally directed to the accessing of data in a memory, such as but not limited to a flash memory array. In accordance with some embodiments, a transfer command is received to transfer selected data between a control module and a memory module. The transfer command specifies a target address in the memory module and a sense threshold vector associated with the selected data. The sense threshold vector in the received transfer command is used to sense a programmed state of at least one solid-state memory cell at the target address responsive to the received transfer command. The transfer command may be a read or write command.

Abstract: A file system programs metadata on a non-volatile memory device. The metadata can include data associating files with ranges of logical block addresses. During a garbage collection process, the data can be used to determine portions of physical blocks of the non-volatile memory device that are associated with files that have been deleted. Using the programmed metadata during garbage collection results in erasure of larger portions of blocks and improved wear leveling.

Abstract: A data processing system that includes a host system and an external data storage device with an erase before write memory device thereon can be operated by sending a file delete command from the host to the data storage device for one or more files stored thereon. The file delete command may specify a logical address and data to be invalidated associated with the deleted file. The data storage device may identify one or more units of memory allocation in the erase before write memory as containing invalid data based on the specified logical address and data to be invalidated. The data storage device may maintain a data structure that associates physical addresses for units of memory allocation in the erase before write memory with indications of whether the units of memory allocation contain invalid data. The data structure may be used to mark units of memory allocation associated with deleted files as containing invalid data.

Abstract: A method for securely storing data in a multilevel memory of a portable data carrier. The multilevel memory includes one or several multilevel memory cells (SZ) which can assume respectively at least three levels (E, NE). The at least three levels represent a different data content, regarding which respective levels (E, NE) of a memory cell (SZ) are defined as valid or invalid. The levels (E, NE) of a respective memory cell (SZ) are selectively defined as valid or invalid in dependence on a required security level.

Abstract: An in-vehicle apparatus includes: a flash memory; a memory controller for executing an initialization process; a backup power source; a power source; a controller; and a power source controller. According to incompletion of initialization, the controller executes standby/boot process. According to completion of initialization, the controller executes the boot process. According to reception of data backup instruction, the controller stores data in the memory. The power source controller switches to a trigger standby mode. According to trigger, the power source controller inputs the energization instruction to the power source. According to termination of trigger, the power source controller inputs the data backup instruction to the controller. According to completion of backup, the power source controller halts to input the energization instruction, and switches to the trigger standby mode. According to incompletion of backup, the power source controller resets the switch and the power source.

Abstract: Provided is a flash memory address translation method that may maintain at least one chip that may be divided based on at least one horizontal bank and at least one vertical channel, and may divide the at least one bank by at least one stripe partition, managing an error of a chip without deterioration in a performance of a small writing.

Abstract: A storage device includes a programmable device into which predetermined control data is written, a control data storing unit that stores therein write control data and read control data, the write control data being control data for realizing a function to save data stored in a cache memory into a nonvolatile memory when an abnormal shut-down occurs and the read control data being control data for realizing a function to restore the data saved in the nonvolatile memory into the cache memory when an electric power source is turned on after the abnormal shut-down, a writing unit that, when an electric power source is turned on after occurrence of the abnormal shut-down of the storage device, writes the read control data into the programmable device, and a restoring instructing unit that instructs the programmable device to restore the data saved in the nonvolatile memory into the cache memory.

Abstract: A memory device, comprising a first control input port, a second control input port, a third control input port, a data input port, a data output port, an internal memory and control circuitry. The control circuitry is responsive to a control signal on the first control input port to capture command and address information via the data input port. When the command is a read command, the control circuitry is further responsive to a read control signal on the second control input port to transfer data associated with the address information from the internal memory onto the data output port. When the command is a write command, the control circuitry is responsive to a write control signal on the third control input port to write data captured via the data input port into the internal memory at a location associated with the address information.

Abstract: A storage apparatus includes one or more memory units each having a plurality of memory blocks to store a file having data corresponding to a plurality of clusters, and a controller to store the file in the memory units such that such that the data of at least two sequential addresses of the clusters are stored in the memory blocks of different memory units.

Abstract: Redundant solid-state memory devices are used to enhance the operation of a network storage system. To reduce the likelihood of substantially concurrent failure of two or more such memory devices, write allocation decisions are made so as to influence the wear on the various solid-state memory devices, so that not all of the solid-state memory devices wear out at the same rate. This can be accomplished by skewing the wear caused by erases/writes, across the solid-state memory devices, so that the devices experience unequal wear and, therefore, do not all fail at or approximately at the same time. The roles of the various flash devices are adjusted when a solid-state memory device is replaced, such that subsequent write allocation decisions are based on the maintenance history (e.g., replacement history) of the devices as well as the past write history.

Abstract: The present disclosure includes systems and techniques relating to non-volatile memory. A described system, for example, includes a non-volatile memory structure having a plurality of multi-level memory cells, a processing device, and a controller. The controller is configured to map a first portion of a first set of consecutive bits of a data segment to a first page associated with the plurality of multi-level memory cells, and map a second portion of the first set of consecutive bits of the data segment to a second page associated with the plurality of multi-level memory cells. The first page is associated with bits of a first significance, and the second page is associated with bits of a second significance.

Abstract: The embodiments described herein provide a controller and method for performing a background commands or operations. In one embodiment, a controller is provided with interfaces through which to communicate with a host and a plurality of flash memory devices. The controller contains a processor operative to perform a foreground command received from the host, wherein the processor performs the foreground command to completion without interruption. The processor is also operative to perform a background commands or operations stored in the controller's memory, wherein the processor performs the background command until completed or preempted by a foreground command. If the background command is preempted, the processor can resume performing the background command at a later time until completed.

Abstract: A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system.

Abstract: The present disclosure relates to a data storage system and method that includes at least two solid state devices that can be classified in at least two different efficiency levels, wherein data progression is used to allocate data to the most cost-appropriate device according to the nature of the data.

Abstract: A secure demand paging (SDP) system includes a dynamic random access memory (DRAM), a microprocessor having a secure internal memory and coupled to said DRAM, and a non-volatile memory storing a representation of operations accessible by the microprocessor. The stored representation of operations includes a coded physical representation of operations to configure an SDP space in the DRAM, to organize the SDP space into virtual machine contexts, to organize at least one of the virtual machine contexts into block book keeping blocks and book keeping spaces in the block book keeping blocks, and to execute a secure demand paging process between said secure internal memory and said DRAM.

Abstract: For a storage apparatus where flash memory disks and hard disks coexist, high-density mounting of flash memory modules is achieved. The storage apparatus includes flash memories and a storage controller. A second storage apparatus including magnetic disks is connected to the storage apparatus. The storage controller can form a storage area using a flash memory or a magnetic disk to create a logical volume. When an input/output request is issued from a host computer, if a storage area is formed with a flash memory, the storage controller directly accesses the flash memory to handle the request. When the storage apparatus defines a storage area formed with a flash memory, the storage apparatus defines the storage area by adding up the capacity of a storage area to be provided for the host computer and a substitute area capacity determined in consideration of restrictions on the number deletions of the flash memory.

Abstract: A storage system comprises a plurality of flash packages comprising a plurality of flash chips, and a storage controller for receiving a first write request from a higher-level apparatus and sending a second write request of write data based on data conforming to this first write request to a write-destination flash package, and demonstrates a capacity virtualization function for causing a storage capacity to appear larger than an actual storage capacity for the higher-level apparatus, and for configuring a storage space using page units. The storage system generates a second VOL (logical volume) based on a first VOL, manages a plurality of VOLs comprising the first VOL and one or more second VOLs generated based on the first VOL as a VOL group, and allocates the same page to areas of the same address of the plurality of VOLs configuring the VOL group.

Abstract: In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.

Abstract: A semiconductor storage apparatus including a flash memory which provides a storage area, and a memory controller which controls the reading and writing of data from and to the flash memory, wherein the storage area of the flash memory is configured from a plurality of write areas, and wherein the memory controller divides the data into a size corresponding to the write area, and changes the starting location of writing the data each time the divided data is written into the write area.

Abstract: A data block may be moved between a first medium and a second medium. The movement of the data block involves measuring the access characteristic of the data block as the data block is stored on the first medium. The performance characteristics of the first medium and the second medium are then determined, in which each performance characteristic has a static performance characteristic component and a dynamic performance characteristic component. Alternatively or concurrently, the static performance characteristic components of the first medium and the second medium may be compared, and the dynamic performance characteristic components of the first medium and the second medium are compared. Accordingly, the data block is moved from the first medium to the second medium when at least one of these comparisons indicate that the second medium is more suitable for storing the data block having the access characteristic than the first medium.

Abstract: According to one embodiment, a memory device includes a nonvolatile memory including a plurality of memory cells, and a controller configured to control the nonvolatile memory. At a time of a boot operation, when a request for initialization of the memory device is issued, the controller does not return a response to the request until completion of the initialization, and the controller returns a response to the request when the initialization is completed.

Abstract: A high-speed large-capacity phase-change memory is achieved. A semiconductor device according to the present invention includes: a plurality of memory planes MP; a plurality of storage information register groups SDRBK paired with the plurality of memory planes; and a chip control circuit CPCTL. The plurality of memory planes include a plurality of memory cells. Also, the plurality of storage information register groups temporarily retain information to be stored in the plurality of memory planes. Further, the chip control circuit includes a register which temporarily stores a value indicating volume of the storage information, and a first storage information volume is smaller than a second storage information volume. When the first storage information volume is written, the plurality of memory planes and the plurality of storage information register groups are activated during a first period.

Abstract: In an embodiment, only one sector of a plurality of sectors in a physical block of a plurality of physical blocks has a sector status location configured to store information that indicates a move status of an other sector of the plurality sectors of the physical block of the plurality of physical blocks, where the only one sector of the plurality of sectors in the physical block of the plurality of physical blocks is configured to store a sector of data in addition to the information that indicates the move status.

Abstract: A non-volatile storage system is provided with reduced delays associated with loading and updating a logical-to-physical mapping table from non-volatile memory. The mapping table is stored in a plurality of segments, so that each segment can be loaded individually. The segmented mapping table allows memory access to logical addresses associated with the loaded segment when the segment is loaded, rather than delaying accesses until the entire mapping table is loaded. When loading mapping segments, segments can be loaded according to whether there is a pending command or by an order according to various algorithms.

Abstract: A computer readable medium stores a program causing a computer to execute a process including receiving an instruction for deleting an information group from a first memory; extracting, from the first memory, information regarding information groups having a parent-child relationship with a target information group to be deleted in accordance with the received instruction; extracting a user identification code associated with the target information group from a second memory; storing an identification code of the target information group, the information regarding the information groups, and the extracted user identification code in association with one another in a third memory; deleting the target information group from the first memory; and changing the structure information stored in the first memory to structure information obtained after the target information group has been deleted from the first memory, by changing the child information group as a child of the parent information group.

Abstract: A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group.

Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

Abstract: A data storage system having a slow tier and a fast tier maintains hot data on the fast tier by migrating data from the slow tier to reserve space on the fast tier as data becomes hot over time. The system maintains a reserve space table and performs a mass migration of data from the fast tier to the slow tier. Data migration is frequently unidirectional with data migrating from the slow to the fast tier, reducing overhead during normal operation.

Abstract: A method for performing data shaping is provided. The method is applied to a controller of a Flash memory, where the Flash memory includes a plurality of blocks. The method includes: according to contents of data to be written into or read from the Flash memory, generating/recovering an input seed of at least one randomizer/derandomizer; and utilizing the randomizer/derandomizer to generate a random function according to the input seed, for use of adjusting a plurality of bits of the data bit by bit. An associated memory device and a controller thereof are also provided.

Abstract: A system operation method for controlling a rewritable non-volatile memory module is provided. The rewritable non-volatile memory module includes a plurality of physical blocks. The system operation method includes following steps. A first signal is received from a host system through a host interface. Whether a system setting of the host interface is to be modified is determined. If the system setting is to be modified, a system parameter is read from the physical blocks, and the system setting is modified according to the system parameter. A second signal is transmitted to the host system to establish a connection recognition between the rewritable non-volatile memory module and the host system. Thereby, the settings of transmission between the host system and the rewritable non-volatile memory module are made more flexible.

Abstract: Methods and systems are disclosed herein for storing data in a memory device. Data for multiple pages is written in parallel using plane interleaving. For example, in a four plane write, a first set of four pages are written in the following sequence: 0, 1, 2, 3. A second set of four pages, after plane interleaving, are written in the following sequent: 7, 4, 5, 6. After writing the data, the pages of written data are read, page swapped if necessary, and then written into another portion of memory (such as MLC).

Abstract: A memory device and method for performing a write-abort-safe firmware update are disclosed. In one embodiment, a location in a memory of a memory device for a firmware update is allocated. The firmware update is written into the allocated location in the memory. A pointer is written to the firmware update in a directory, and a pointer is written to the directory in a location in the memory that is read during boot-up. In another embodiment, a block in a memory of a memory device is allocated for updated file system data comprising a firmware update and a directory. The updated file system data is written into the allocated location in the memory. A pointer is written to the firmware update in the directory, and a pointer is written to the updated file system data in a boot block in the memory, wherein the boot block is read during boot-up.

Abstract: A hybrid drive is disclosed comprising a head actuated over a disk, and a non-volatile semiconductor memory (NVSM). A first execution time needed to execute commands in a NVSM command queue is estimated, and a second execution time needed to execute commands in a disk command queue is estimated. An access command is inserted into a selected one of the NVSM command queue and the disk command queue in response to the first and second execution times, and one of the first and second execution times is updated in response to an estimated execution time of the access command.

Abstract: A data processing method for a memory storage apparatus having physical blocks is provided. The method includes: grouping the physical blocks into a data area, a spare area and a system area; configuring a plurality of logical addresses which would be formatted into a file allocation table area having cluster entry fields, a root directory area having directory entry fields and a file area having clusters; storing a communication file from the Kth cluster of the file area; recording a file description block corresponding to the communication file in the Mth directory entry field and storing an end of cluster chain mark in the cluster entry field corresponding to the last cluster of the clusters where the communication file stores, and K and M are positive integers which are larger than one. Accordingly, the method can prevent the communication file from being overwritten after the memory storage apparatus is formatted.