Abstract: According to one embodiment, a method for using flash memory in a storage cache comprises receiving data to be cached in flash memory of a storage cache, at least some of the received data being received from at least one of a host system and a storage medium, selecting a block of the flash memory for receiving the data, buffering the received data until sufficient data has been received to fill the block, and overwriting existing data in the selected block with the buffered data. According to another embodiment, a method comprises receiving data, at least some of the data being from a host system and/or a storage medium, and sequentially overwriting sequential blocks of the flash memory with the received data. Other devices and methods for working with flash memory in a storage cache according to various embodiments are included and described herein.

Abstract: A delete notification can be received at a storage stack filter in a storage stack. It can be determined whether the delete notification applies to an entire storage device. If the delete notification does not apply to the entire storage device, a first set of actions can be taken with the storage stack filter in response to the delete notification. If the delete notification does apply to the entire storage device, a second set of actions can be taken with the storage stack filter in response to the delete notification.

Abstract: In a first aspect, a first method is provided. The first method includes the steps of (1) providing a cache having a plurality of cache entries, each entry adapted to store data, wherein the cache is adapted to be accessed by hardware and software in a first operational mode; (2) determining an absence of desired data in one of the plurality of cache entries; (3) determining a status based on a current operational mode and a value of hint-lock bits associated with the plurality of cache entries; and (4) determining availability of at least one of the cache entries based on the status, wherein availability of a cache entry indicates that data stored in the cache entry can be replaced. Numerous other aspects are provided.

Abstract: A data processing system includes a processor core having an associated upper level cache and a lower level victim cache. In response to a memory access request of the processor core, the lower level cache victim determines whether the memory access request hits or misses in the directory of the lower level victim cache, and the upper level cache determines whether a castout from the upper level cache is to be performed and selects a victim coherency granule for eviction from the upper level cache. In response to determining that a castout from the upper level cache is to be performed, the upper level cache evicts the selected victim coherency granule. In the eviction, the upper level cache reads out the victim coherency granule from the data array of the upper level cache only in response to an indication that the memory access request misses in the directory of the lower level victim cache.

Abstract: Provided a computer program product, system, and method for cache management of tracks in a first cache and a second cache for a storage. The first cache maintains modified and unmodified tracks in the storage subject to Input/Output (I/O) requests. Modified and unmodified tracks are demoted from the first cache. The modified and the unmodified tracks demoted from the first cache are promoted to the second cache. The unmodified tracks demoted from the second cache are discarded. The modified tracks in the second cache that are at proximate physical locations on the storage device are grouped and the grouped modified tracks are destaged from the second cache to the storage device.

Abstract: In one embodiment, a multi-core processor having cores each associated with a cache memory, can operate such that when a first core is to access data owned by a second core present in a cache line associated with the second core, responsive to a request from the first core, cache coherency state information associated with the cache line is not updated. A coherence engine associated with the processor may receive the data access request and determine that the data is of a memory page owned by the first core and convert the data access request to a non-cache coherent request. Other embodiments are described and claimed.

Abstract: Disclosed is a bad block management method of a memory system that includes virtual blocks having a plurality of units and at least one reserved block. The bad block management method includes mapping the virtual blocks and the at least one reserved block onto one physical block in the plurality of physical blocks, determining that a first virtual block in the virtual blocks includes a bad virtual block unit, and replacing the bad virtual block unit in the first virtual block with a first reserved block unit selected from the reserved block units.

Abstract: This storage control apparatus 100 is able sufficiently to manifest the merits of economization of electrical power. The storage control apparatus 100 includes one or more additional storage units 150 which are adapted for the supply of power to them to be turned ON and OFF individually. Each of these additional storage units 150 includes a plurality of storage devices 154 (for example, a plurality of HDDs). When a user actuates a management device 106, and causes one or more RAID groups and a spare HDD for each of these RAID groups to be set within the storage control apparatus 100, an MPU 140 of the storage control apparatus 100 controls the management device 106 to make the user set each RAID group and the spare HDD for it within the same additional storage unit 150.

Abstract: A swapping method performed using a data processing device, which includes a processor including a plurality of cores, the swapping method including searching for an empty page of a swap memory in response to the swap memory being connected to the data processing device, the search being performed by using at least one core of the plurality of cores, selecting a page to be swapped from a main memory of the data processing device, the selection being performed by using the at least one core by accessing a corresponding main memory list among a plurality of main memory lists, and swapping data of the page selected to be swapped to the empty page, the swapping being performed by using the at least one core.

Abstract: Storage servers use a fast, non-volatile or persistent memory to store data until it can be written to slower mass storage devices such as disk drives. If the server crashes before a write can complete, the data remains safely stored in non-volatile memory. If the data cannot be committed to disk when the server reboots (e.g. because the destination mass storage device is unavailable), it is stored in a file. When the disk reappears, the data in the file may be used to restore a file or filesystem on the disk to a consistent state.

Abstract: A method in one embodiment for operating a virtual server supporting at least one Write Once Read Many (WORM) logical data object and at least one read-write logical object includes initializing a logical data object from a common pool of the logical data objects, the logical data object bound with a member of a media type group, the member of the media type group comprising a WORM logical data object and a read-write logical data object; and reusing one of the logical data objects as the member of the media type group without ejection and reinsertion by mounting the logical data object with a write from beginning of logical data object to bind at least one data attribute to the member of the media type group to replace any previous attribute and data associated with the logical data object.

Abstract: A method for deleting a relation between a source and a target in a multi-target architecture is described. The multi-target architecture includes a source and multiple targets mapped thereto. In one embodiment, such a method includes initially identifying a relation for deletion from the multi-target architecture. A target associated with the relation is then identified. The method then identifies a sibling target that inherits data from the target. Once the target and the sibling target are identified, the method copies the data from the target to the sibling target. The relation between the source and the target is then deleted. A corresponding computer program product is also disclosed and claimed herein.

Abstract: Memory management for object oriented applications during run time includes loading an object oriented application into a computer memory. The object oriented application includes a plurality of nodes in a classification tree, the nodes including key value pairs. The nodes are aggregated in the classification tree by a computer. The aggregating includes eliminating redundant keys and creating a composite node. The composite node is loaded into the computer memory. The plurality of nodes in the classification tree are removed from the computer memory in response to loading the composite node into the computer memory.

Abstract: Techniques for directory server integration are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for directory server integration comprising setting one or more parameters determining a range of permissible expiration times for a plurality of cached directory entries, creating, in electronic storage, a cached directory entry from a directory server, assigning a creation time to the cached directory entry, and assigning at least one random value to the cached directory entry, the random value determining an expiration time for the cached directory entry within the range of permissible expiration times, wherein randomizing the expiration time for the cached directory entry among the range of permissible expiration times for a plurality of cached directory entries reduces an amount of synchronization required between cache memory and the directory server at a point in time.

Abstract: Managing access to a cache memory includes dividing said cache memory into multiple of cache areas, each cache area having multiple entries; and providing at least one separate lock attribute for each cache area such that only a processor thread having possession of the lock attribute corresponding to a particular cache area can update that cache area.

Abstract: In one embodiment of the invention, a method is provided for retrieving certain electronic information previously stored on certain storage media after a threshold set in the storage retention criteria has been exceeded in an electronic information storage system that stores electronic information on storage media in accordance with a storage retention criteria is provided. The method includes storing a record in a memory associated with a system manager that assigns the storage retention criteria to the certain electronic data, designating the storage media available for overwrite after the threshold set in the storage retention policy has been exceeded, identifying the certain storage media available for overwrite, and retrieving information from the certain media after the threshold set in the storage retention policy has been exceeded.

Abstract: A method and apparatus for mitigating the performance impact of background or idle time processing during interactive computing sessions. One embodiment of the present invention is a method for mitigating performance impact of background or idle time processing on interactive applications comprising identifying executable and data pages in physical memory that are associated with an interactive application that is temporarily unused and preventing any of the identified executable and data pages from paging out.

Abstract: A system and method for efficiently storing data both on-site and off-site in a cloud storage system. Data read and write requests are received by a cloud data storage system. The cloud storage system has at least three data storage layers. A first high-speed layer, a second efficient storage layer, and a third off-site storage layer. The first high-speed layer stores data in raw data blocks. The second efficient storage layer divides data blocks from the first layer into data slices and eliminates duplicate data slices. The third layer stores data slices at an off-site location.

Abstract: A first acquisition unit acquires each of the resources defined by the scenario, from locations depending on identifiers of the resources. A judging unit judge, when a resource having same identifier and structure as the resource acquired is existent in the cache storage, erases the resource, the identifier thereof, and the receipt time information from the cache storage, and when not existent, stores the acquired resource in association with the identifier thereof and the receipt time information of the bookmark instruction, in the cache storage. A second acquisition, when the identifiers of the resources specified by a first scenario are existent in the cache storage, acquires the resources from the cache storage according to the receipt time information corresponding to the first scenario and identifiers of the resources, and when not existent, acquires the resources from a location depending on the identifiers.

Abstract: Example embodiments described herein may comprise a transfer of firmware execution within a non-volatile memory device to one or more replacement instructions at least in part in response to a match between a code fetch address and an address stored n a trap address register.

Abstract: Memory of a database management system (DBMS) that is running in a virtual machine is managed using techniques that integrate DBMS memory management with virtual machine memory management. Because of the integration, the effectiveness of DBMS memory management is preserved even though the physical memory allocated to the virtual machine may change during runtime as a result of varying memory demands of other applications, e.g., instances of other virtual machines, running on the same host computer as the virtual machine.

Abstract: One or more embodiments comprise control circuitry coupled to one or more memory devices having a number of planes of physical blocks organized into super blocks. The control circuitry can be configured to: determine defective physical blocks among the number of planes; responsive to none of the physical blocks at a particular block position being determined to be defective, assign the physical blocks at the particular block position to a super block; and responsive to one or more of the physical blocks at a particular block position being determined to be defective, assign non-defective physical blocks at the particular block position to a super block and assign a replacement physical block to the super block for the respective defective physical blocks at the particular block position, the replacement physical block selected from a number of physical blocks within a respective plane that includes a respective defective physical block.

Abstract: A recording/reproducing apparatus is configured to record a replacement block by logical overwrite (LOW) for updating data recorded on an information storage medium in a first area of the medium, record a replacement block for replacing a defect block generated on the medium in a second area of the medium, and record a second replacement block for replacement by defect of a first replacement block in the second area if the defect is detected while the first replacement block is being recorded in the first area to perform the logical overwrite of an original block recorded in a predetermined area of the medium, generate a defect list (DFL) entry including location information of the original block and location information of the second replacement block in order to indicate the replacement state, and move location information of the first replacement block in the second replacement block.

Abstract: A memory system including a plurality of ports and a memory core having a plurality of memory banks. Access requests received at the ports are broadcast to the memory banks. Multiple memory banks may be concurrently accessed in response to access requests received on different ports. A memory controller provides the access requests to the memory system, and ensures that a single memory bank is not concurrently accessed by different ports. All access requests are processed with the same latency. If the memory banks include memory cells that must be periodically refreshed, then the memory controller also provides refresh requests to the memory banks. Because multiple memory banks may be concurrently accessed in response to access requests provided on different ports, the memory banks can operate at a lower frequency than the ports.

Abstract: A storage control apparatus of the present invention is able to duplicatively manage data in a cache memory even during maintenance work. When a memory package CMPK3 specified by a user is removed from the apparatus 1 (S2), a microprocessor 2 changes a pair that has been configured using CMPK2 and CMPK3 to a pair of CMPK2 and a free area of a CMPK1. As a result, received data (S5) is respectively written to multiple cache memories (S6, S7), and duplicatively managed.

Abstract: Embodiments of the present invention provide mechanisms for improving storage consumption on a sequential access medium, such as a physical tape, by preferably storing one instance of a data block of a backup data set on the tape media. When another instance of a data block is received having the same pattern as the stored data block, rather than storing the data block itself, a reference to the data block is stored on the sequential access medium. When data are restored, data blocks are cached at a block store on a storage device(s) having a faster seek time than the tape. When a reference to a previously stored data block is read from the tape, rather than re-winding the tape to search for the data block on the tape (which might take a long time to locate), the referenced data block can be found on the storage device having a faster seek time than the tape media.

Abstract: Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests.

Abstract: A first cache simultaneously broadcasts, in a single message, a request for a cache line and a request to accept a future related evicted cache line to multiple other caches. Each of the multiple other caches evaluate their occupancy to derive an occupancy value that reflects their ability to accept the future related evicted cache line. In response to receiving a requested cache line, the first cache evicts the related evicted cache line to the cache with the highest occupancy value.

Abstract: Techniques for using structured virtual registers in embedded systems are described. A virtual register structure definition provides a map of virtual registers within an embedded controller. The virtual registers are externally accessible and correspond to memory locations within the embedded controller. In various embodiments, an embedded controller and/or an external entity may store data in or read data from the virtual registers using the virtual register structure definition. The problems of manual tracking of virtual register addresses and manual transcription of virtual register addresses to program code are ameliorated. When the virtual register map changes, logical references in program code to particular virtual registers need not necessarily be changed.

Abstract: A recording/reproducing apparatus is configured to record a replacement block by logical overwrite (LOW) for updating data recorded on an information storage medium in a first area of the medium, record a replacement block for replacing a defect block generated on the medium in a second area of the medium, and record a second replacement block for replacement by defect of a first replacement block in the second area if the defect is detected while the first replacement block is being recorded in the first area to perform the logical overwrite of an original block recorded in a predetermined area of the medium, generate a defect list (DFL) entry including location information of the original block and location information of the second replacement block in order to indicate the replacement state, and move location information of the first replacement block in the second replacement block.

Abstract: Embodiments of the invention provide methods and apparatus for selectively bypassing cache levels when processing non-reusable transient data in a cache coherent system. To selectively bypass cache levels a page table entry (PTE) mechanism may be employed. To limit the number of PTE bits, the PTE may have a 2-bit “bypass type” field among other attribute bits that index which bits of a Special Purpose Register (SPR) identify the cache levels to be bypassed.

Abstract: A transactional memory system, method and apparatus are disclosed. An embodiment of the method includes attempting to acquire a write lock provided by an implementation of a software transactional memory (STM) system for each of a set of memory locations of the STM; if a write lock is acquired for each of the set of memory locations, comparing the value in each of the set of memory locations to a corresponding expected value; and if the comparing yields the same, predetermined result for each of the set of memory locations, storing in each memory location a corresponding new value. Other embodiments are also described and claimed.

Abstract: An information storage device includes one or more semiconductor memories storing management data accompanying content data and being configured to erase data in units of one block, and a controller setting up, in the one or more semiconductor memories, a working area to temporarily store the management data and a storage area to retain all or part of the management data stored in the working area, writing the management data to the working area while monitoring the free space of the working area, moving the management data stored in the working area to the storage area when the free space of the working area falls below a prescribed value, and erasing the management data stored in the working area after the movement of the management data to the storage area.

Abstract: In an IC card, an operating system manages the access order of each channel for each file using a channel management table. An application controls access to each file based on the access order managed in the channel management table. The channel management table stores, as an access order, an order that each logical channel has set a file in a current state. If current setting by a specific logical channel is canceled, a table updating function deletes the logical channel from the channel management table and moves up the access order of each logical channel next to the deleted logical channel.

Abstract: For each memory location in a set of memory locations associated with a thread, setting an indication associated with the memory location to request a signal if data from the memory location is evicted from a cache; and in response to the signal, reloading the set of memory locations into the cache.

Abstract: Storage servers use a fast, non-volatile or persistent memory to store data until it can be written to slower mass storage devices such as disk drives. If the server crashes before a write can complete, the data remains safely stored in non-volatile memory. If the data cannot be committed to disk when the server reboots (e.g. because the destination mass storage device is unavailable), it is stored in a file. When the disk reappears, the data in the file may be used to restore a file or file system on the disk to a consistent state.

Abstract: Methods and systems provide recognition of a device in a daisy chain cascade configuration. Input circuitry at a device receives an input signal that indicates device configuration following a power-up, reset or other operation of the device. A pulse generator generates a pulse in response to the operation, the pulse occurring while the input signal indicates device configuration. A state latch register stores the state of the input signal in response to the received pulse, thereby storing a state indicating configuration of the respective device. Following this operation, the input circuitry may receive signals unrelated to the device configuration, thereby obviating the need for additional pin assignment.

Abstract: A computer-implemented method for controlling initialization of a fingerprint cache for data deduplication associated with a single-instance-storage computing subsystem may comprise: 1) detecting a request to store a data selection to the single-instance-storage computing subsystem, 2) leveraging a client-side fingerprint cache associated with a previous storage of the data selection to the single-instance-storage computing subsystem to initialize a new client-side fingerprint cache, and 3) utilizing the new client-side fingerprint cache for data deduplication associated with the request to store the data selection to the single-instance-storage computing subsystem. Other exemplary methods of controlling initialization of a fingerprint cache for data deduplication, as well as corresponding exemplary systems and computer-readable-storage media, are also disclosed.

Abstract: Disclosed is a data transfer method of a memory system which includes reading data from a first non-volatile memory having at least one first chip connected to a controller through a first channel; and transferring the read data to a second non-volatile memory having at least one second chip connected to the controller through a second channel, wherein each of the first and second channels has at least one line for activating a corresponding chip, wherein the first and second channels share at least one data line, and wherein data transfer operations in through the first and second channels are performed in response to data strobe signals.

Abstract: A memory device comprises a memory array, a status register coupled with the memory array, and a security register coupled with the memory array and the status register. The memory array contains a number of memory blocks configured to have independent access control. The status register includes at least one protection bit indicative of a write-protection status of at least one corresponding block of the memory blocks that corresponds to the protection bit. The security register includes at least one register-protection bit. The register-protection bit is programmable to a memory-protection state for preventing a state change of at least the protection bit of the status register. The register-protection bit is configured to remain in the memory-protection state until the resetting of the memory device.

Abstract: A flash memory includes a data area in which first and second k-bit data (k is a natural number) are stored; and an additional data area in which a first additional m-bit data (m is a natural number) and a second additional m-bit data used to respectively identify the first and second data are stored. The first additional data and the second additional data have different values.

Abstract: A digital data reproducing apparatus comprising: a reading unit configured to read digital data stored in a recording medium at a speed higher than a reproduction speed to store the digital data into a first memory; an encoding unit configured to store encoded data obtained by encoding the digital data read by the reading unit into a second memory; a reproducing unit configured to reproduce the digital data stored in the first memory at the reproduction speed; and a transferring unit configured to transfer the encoded data stored in the second memory into a third memory different from the second memory.

Abstract: Disclosed is a storage system. A network interface device (NIC) receives network storage commands from a host. The NIC may cache the data to/from the storage commands in a solid-state disk. The NIC may respond to future network storage command by supplying the data from the solid-state disk rather than initiating a network transaction.

Abstract: Method and apparatus for handling data in a data storage device. In accordance with some embodiments, a memory space with a plurality of garbage collection units (GCUs) that are each arranged into pages of memory that store user data identified by logical addresses (LAs) and each GCU has a metadata region that stores metadata that correlates the LAs with physical addresses (PAs). A header region in each page of memory stores a bitmask and a sequence map of the LAs in each page that are used by a log manager to creates a bitmask table stored in a first cache and a hierarchical log stored in a second cache. The bitmask table and hierarchical log are used to determine when the LAs stored in the selected GCU are stale, and update the bitmask for each page in the selected GCU after the stale data has been erased.

Abstract: Embodiments of the present invention provide a mechanism for an operating system and applications to cooperate in memory management. Applications register with the operating system for cooperative memory management. The operating system monitors the memory and determines a memory “pressure” related to the amount of demand for the memory. As the memory pressure increases, the operating system provides a memory pressure signal as feedback to the registered applications. The operating system may send this signal to indicate it is about to commence evicting pages from the memory or when it has commenced swapping out application data. In response to the signal, the registered applications may evaluate the memory pressure, determine which data should be freed, if any, and provide this information back to the operating system. The operating system may then free those portions of memory relinquished by the applications. By releasing data the system may thus avoid swapping and increase its performance.

Abstract: Provided are a method, system, and article of manufacture for performing backup operations for a volume group of volumes. Information on a volume group associating a plurality of volumes and backup settings is maintained. A volume group is selected to which the backup settings apply. A volume group associates hosts and volumes, indicating the hosts that are enabled to access the volumes in the volume group. Automatic backup operations for the selected volume group are invoked to generate backup information for the volume group indicating backups performed with respect to the volumes associated with the volume group, process the backup information for the volume group to determine whether to perform a backup with respect to the volume group according to the backup settings, and backup each volume in the volume group in response to determining to perform the backup operation for the volume group.

Abstract: A multi-stage multiplexing operation that includes combined selection and data alignment or data replication is disclosed. In a particular embodiment, a method includes performing a first stage of a multi-stage multiplexing operation. During the first stage, a first data source is selected from a first plurality of data sources. At least one of a first data alignment operation and a first data replication operation is also performed on first data from the selected first data source during the first stage.

Abstract: In one embodiment, a multi-core processor having cores each associated with a cache memory, can operate such that when a first core is to access data owned by a second core present in a cache line associated with the second core, responsive to a request from the first core, cache coherency state information associated with the cache line is not updated. A coherence engine associated with the processor may receive the data access request and determine that the data is of a memory page owned by the first core and convert the data access request to a non-cache coherent request. Other embodiments are described and claimed.

Abstract: According to the present invention, the size of defect management information is reduced by using a top spare area 102 and middle spare areas 103 in the ascending order of their physical block addresses and spare areas can be expanded more easily by using only the last spare area 104 in the descending order of its physical block addresses.

Abstract: An embodiment of the invention comprises a virtual tape system supporting at least one Write Once Read Many (WORM) logical tape and at least one read-write logical tape, comprising a processor configured to a first task and/or a second task. The first task initializes a new logical data object from a single pool of at least two logical data objects, with the new logical data object bound with a member of a media type group consisting of a WORM data object or a read-write data object. The second task reuses one of the logical data objects without manual ejection and reinsertion. The reuse may include the processor configured to cycle the logical data object through a scratch pool as a selected scratch logical data object and mount the selected scratch logical data object with a write from beginning of tape command to bind at least one data attribute to the WORM data object.