Abstract: While a computer system is in operational state, a network interface controller (NIC) in the computer system may be operable to copy select data to a secondary storage device. The secondary storage device is accessible by the NIC while the computer system is in an offline state or not operational. The NIC may be operable to provide remote accessibility to the copy of the select data stored in the secondary storage device over a network while the computer system is in the offline state and the NIC is supplied with electrical power and active. While the computer system is in the operational state and whenever a change is made to the select data, the NIC is operable to replace the copy of the select data stored in the secondary storage device with an updated copy of the select data based on the change.

Abstract: An embodiment of the invention provides a concrete data type and a method for providing a cached chunked list concrete data type. The method can perform steps including: storing at least one datum in a chunk in a cache line; and setting a lower bit value (LB) in a link/space pointer in the chunk to indicate the empty slots in the chunk.

Abstract: An array of streaming multiprocessors shares data via a shared memory. A flushing mechanism is used to guarantee that data required for dependent computations is available in the shared memory.

Abstract: Provided are an embedded system and a method for relocating memory pages therefor. The embedded system includes a processor, a data relocating circuit for receiving a logical address from the processor, mapping the received logical address to a physical address to locate a valid page in a predetermined bank, and generating a bank power control signal according to whether or not a corresponding memory bank includes valid pages, and a memory including a plurality of memory banks addressed by a physical address outputted from the data relocating circuit and a plurality of switching means for selectively supplying a power voltage to each of memory banks in response to the bank power control signal.

Abstract: A method of memory management is disclosed. The invention increases bank diversity by splitting requests and is also integrated with re-ordering and priority arbitration mechanisms. Therefore, the probabilities of both bank conflicts and write-to-read turnaround conflicts are reduced significantly, so as to increase memory efficiency.

Abstract: An improved system and method enhances performance of updates to sequential block storage of a storage system. A disk-based sort procedure is provided to establish locality among updates (write data) held in a disk-based log, thereby enabling the write data to be efficiently written to home locations on a home location array. As the write data is received, a log manager of the storage system temporarily stores the data efficiently on the disk-based log. As more write data arrives, the log manager sorts the data in the log in accordance with the sort procedure, thus increasing the locality of data when stored on the home location array. When the log approaches capacity, the log manager writes the sorted data to their home locations on the array with high locality and performance.

Abstract: Replacement of a signal address referred to in a sequence program is carried out by storing in advance, before-after replacement information which specifies the relationship between signal addresses before replacement and signal addresses after replacement in a format with a specifying of range. Based on the stored before-after replacement information, all the signal addresses to be replaced are searched for in the editing target sequence program or replacement target symbol information. Replacement of a searched signal address with a corresponding after-replacement signal address is executed in accordance with the before-after replacement information.

Abstract: A method for selectively controlling reutilization of space in a virtual tape system (VTS) having a buffer and a multiple volume tape cartridge includes transferring data volume files to the VTS. The buffer transfers the data making up these files as virtual tape volumes (VTVs) to different locations of the cartridge for storage. A file is selectively designated for the VTS to delete from storage after a date included with the file has elapsed by deleting the VTVs corresponding to the file from the cartridge to reuse space of the cartridge. The method includes detecting if a file transferred as VTVs to the cartridge has been designated for deletion. The VTS is prohibited from deleting the file after the date has elapsed if the file was not designated for deletion and is allowed to delete the file after the date has elapsed if the file was not designated for deletion.

Abstract: In an embodiment, a non-transparent memory unit is provided which includes a non-transparent memory and a control circuit. The control circuit may manage the non-transparent memory as a set of non-transparent memory blocks. Software executing on one or more processors may request a non-transparent memory block in which to process data. The control circuit may allocate a first block, and may return an address (or other indication) of the allocated block so that the software can access the block. The control circuit may also provide automatic data movement between the non-transparent memory and a main memory system to which the non-transparent memory unit is coupled. For example, the automatic data movement may include filling data from the main memory system to the allocated block, or flushing the data in the allocated block to the main memory system after the processing of the allocated block is complete.

Abstract: A system is described for managing memory, the system including, among other things, a memory with logic and a processor configured with the logic to receive an indication of an application state from a plurality of applications in memory and determine which of the plurality of applications to effect removal from the memory based on the received indication.

Abstract: A computer-implemented method, apparatus, and computer program-product for controlling cache. The method includes the steps of assigning a value corresponding to a transaction to a memory object that is created while a computer application is processing the transaction; adding the assigned value as a transaction flag value to a flag area of a cache array in accordance with the storage of the memory object in the cache; registering the corresponding transaction flag value as a victim candidate at the completion of the transaction; and in response to eviction of a cache line, preferentially evicting a cache line having the transaction flag value registered as the victim candidate.

Abstract: Determining and applying a cache replacement policy for a computer application running in a computer processing system is accomplished by receiving a processor core data request, adding bits on each cache line of a plurality of cache lines to identify a core ID of an at least one processor core that provides each cache line in a shared cache, allocating a tag table for each processor core, where the tag table keeps track of an index of processor core miss rates, and setting a threshold to define a level of cache usefulness, depending on whether or not the index of processor core miss rates exceeds the threshold. Checking the threshold and when the threshold is not exceeded, then a shared cache standard policy for cache replacement is applied. When the threshold is exceeded, then the cache line from the processor core running the application is evicted from the shared cache.

Abstract: Where a first computing device is given responsibility for determining whether data that is time stamped by a second computing device is replicated or not, then the first device can compare a time stamp from the second device against a time signal from its own internal clock to determine a delta and use that delta to deduce the correct delta to apply to time stamps associated with later data from the second computing device.

Abstract: A method and apparatus for preventing selection of Deleted (D) members as an LRU victim during LRU victim selection. During each cache access targeting the particular congruence class, the deleted cache line is identified from information in the cache directory. A location of a deleted cache line is pipelined through the cache architecture during LRU victim selection. The information is latched and then passed to MRU vector generation logic. An MRU vector is generated and passed to the MRU update logic, which is selects/tags the deleted member as a MRU member. The make MRU operation affects only the lower level LRU state bits arranged in a tree-based structure state bits so that the make MRU operation only negates selection of the specific member in the D state, without affecting LRU victim selection of the other members.

Abstract: A computer-implemented method for controlling initialization of a fingerprint cache for data deduplication associated with a single-instance-storage computing subsystem may comprise: 1) detecting a request to store a data selection to the single-instance-storage computing subsystem, 2) leveraging a client-side fingerprint cache associated with a previous storage of the data selection to the single-instance-storage computing subsystem to initialize a new client-side fingerprint cache, and 3) utilizing the new client-side fingerprint cache for data deduplication associated with the request to store the data selection to the single-instance-storage computing subsystem. Other exemplary methods of controlling initialization of a fingerprint cache for data deduplication, as well as corresponding exemplary systems and computer-readable-storage media, are also disclosed.

Abstract: Selective durability in a directory database is presented. A directory database that provides durability processing includes a mechanism where selective attributes for directory resources can turn durability processing off. So, when a directory transaction is encountered having a durability processing turned off, the directory database processes that directory transaction without first flushing the directory transaction from memory to storage.

Abstract: A novel and useful mechanism and method for writing data updates to a data cache subsystem of a storage controller. Updates received by the storage controller requiring storage allocation on a repository volume are delayed prior to being written to the data cache subsystem. The delay is based on the storage utilization of the repository volume. As the utilization of the repository volume increases, the cache write delay increases, thereby limiting the possibility that there will still be any updates in the data cache subsystem waiting to be destaged to the repository volume when the repository volume is fully utilized. When the repository volume is fully utilized all writes to the data cache of updates that will cause destage of tracks in the repository volume are stopped, thereby causing an infinite delay.

Abstract: In accordance with one embodiment, an enhanced chip multiprocessor permits an L1 cache to request ownership of a data line from a shared L2 cache. A determination is made whether to deny or grant the request for ownership based on the sharing of the data line. In one embodiment, the sharing of the data line is determined from an enhanced L2 cache directory entry associated with the data line. If ownership of the data line is granted, the current data line is passed from the shared L2 to the requesting L1 cache and an associated enhanced L1 cache directory entry and the enhanced L2 cache directory entry are updated to reflect the L1 cache ownership of the data line. Consequently, updates of the data line by the L1 cache do not go through the shared L2 cache, thus reducing transaction pressure on the shared L2 cache.

Abstract: A method for reallocating blocks in a storage pool involves copying multiple source blocks to multiple replacement blocks, where the source blocks are stored on a source disk in the storage pool, and where the replacement blocks are stored on one or more replacement disks in the storage pool, and generating an indirection object, where the indirection object includes a mapping of locations of the source blocks to locations of the replacement blocks.

Abstract: A method for caching data in a storage system involves receiving a request for a first datum stored on a storage disk, retrieving the first datum from the storage disk when a copy of the first datum is not stored in a main memory and when a copy of the first datum is not stored on an asymmetric cache device (ACD), storing a first copy of the first datum in the main memory, updating a list of data to include the first datum, where each datum in the list of data is a datum for which a copy is stored in the main memory, where the list of data is sorted using a scheme such that a datum at a head of the list of data is most favored by the scheme and a datum at a tail of the list of data is least favored by the scheme, storing, prior to any data being evicted from the main memory, a second copy of the first datum on the ACD, where the first datum is one of a first group of data selected using a head-first search of the list of data, and evicting the first copy of the first datum from the main memory when a first co

Abstract: In a computer system with a disk array that has physical storage devices arranged as logical storage units and is capable of carrying out hardware storage operations on a per logical storage unit basis, data movement operations can be carried out on a per-file basis. A data mover software component for use in a computer or storage system enables cloning and initialization of data to provide high data throughput without moving the data between the kernel and application levels.

Abstract: In some embodiments, a method for controlling a cache having a volatile memory and a non-volatile memory during a power up sequence is provided. The method includes receiving, at a controller configured to control the cache and a storage device associated with the cache, a signal indicating whether the non-volatile memory includes dirty data copied from the volatile memory to the non-volatile memory during a power down sequence, the dirty data including data that has not been stored in the storage device. In response to the received signal, the dirty data is restored from the non-volatile memory to the volatile memory, and flushed from the volatile memory to the storage device.

Abstract: Music can be broadcast from a radio station and recorded onto a cache of a personal electronic device, such as a portable digital music player. The recording can occur such that there is segmenting of music into different cache portions based upon classification. Instead of playing music from the radio station, music can be played from the cache to ensure high quality and desirable variety. Different rules can be used to govern which music is played as well as how music should be removed from the cache. In addition, targeted advertisements can be used that relate to the music in the cache as well as a user location.

Abstract: A data accessing method for accessing data in a plurality of physical page addresses of a plurality of physical blocks in a flash memory chip is provided. The data accessing method includes proving a plurality of logical page addresses for a host system, creating a logical page to physical page mapping table and a physical page to logical page mapping table to record the mapping between the logical page addresses and the physical page addresses. The data accessing method also includes writing data into the physical page addresses, and updating the logical page to physical page mapping table and the physical page to logical page mapping table. The data accessing method further includes determining whether the physical page addresses are valid or invalid based on the logical page to physical page mapping table and the physical page to logical page mapping table.

Abstract: Non-volatile memory array can be recovered after a power loss. In one example, pages of a memory array are scanned to find a first free page after the power loss.

Abstract: A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory, and the second coherency domain includes a coherent second cache memory. The first cache memory within the first coherency domain of the data processing system holds a memory block in a storage location associated with an address tag and a coherency state field. The coherency state field is set to a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is likely cached only within the first coherency domain.

Abstract: Methods and systems provide memory handling for memory systems with mixed volatile and nonvolatile memory types. In various embodiments, the method or system maintains a page table that marks memory pages in nonvolatile memory as write-protected. When a write is attempted to a write-protected page in nonvolatile memory, a fault is generated. In response to the fault, memory contents of the write-protected nonvolatile page are moved to a page location in a volatile memory.

Abstract: A system and method is provided to support immediate freeing of a designated element from memory. Following a process of designating an element for removal from a data-structure, conditional limitations are used to determine if immediate freeing of the element from memory is available. The conditional limitations include determining that the instruction originates from a uniprocessor computer system. In addition, the conditional limitations include a determination as to whether a call_rcu primitive or synchronize_kernel primitive may be omitted, or whether the computer implemented instruction is operating in an interrupt handler. If the conditional limitations are met, the designated element may be immediately freed from memory.

Abstract: Provided are a method, system, and program for forming a consistency group of data. Information is provided on a consistency group relationship indicating a plurality of slave controllers and, for each indicated slave controller, a slave storage unit managed by the slave controller. A command is transmitted to each slave controller in the consistency group relationship to cause each slave controller to transmit data in the slave storage unit to a remote storage in a manner that forms the consistency group. A determination is made as to whether all the slave controllers successfully transmitted the data in the slave storage units that is part of the consistency group to the remote storage.

Abstract: One or more target files are securely erased from a host storage medium such as a disk by overwriting the target files not just with “O's,” “1's” and/or random data, but also (or instead) by overwriting them with portions of other, selected, innocuous files found on the same medium. By booting the host using a secondary, preferably external mechanism, before the host operating system is allowed to load, logging of file accesses and process execution by the host OS is circumvented. Post-replacement fragmentation and defragmentation may also be used to further reduce the detectability of the erasure, and the success of the process may be evaluated using statistical analysis.

Abstract: A memory system is provided comprising a memory controller, a level 1 (L1) cache including L1 tag memory and L1 data memory, a level 2 (L2) cache coupled to the L1 cache, the L2 cache including L2 tag memory having a plurality of L2 tag entries and a L2 data memory having a plurality of L2 data entries. The L2 tag entries are more than the L2 data entries. In response to receiving a tag and an associated data, if L2 tag entries having corresponding L2 data entries are unavailable and if a first tag in a first L2 tag entry with an associated first data in a first L2 data entry has a more recent or duplicate value of the first data in the L1 data memory, the memory controller moves the first tag to a second L2 tag entry that does not have a corresponding L2 data entry, vacates the first L2 tag entry and the first L2 data entry and stores the received tag in the first L2 tag entry and the received data in the first L2 data entry.

Abstract: A processing device employs a stack memory in a region of an external memory. The processing device has a stack pointer register to store a current top address for the stack memory. One of several techniques is used to determine which portion or portions of the external memory correspond to the stack region. A more efficient memory policy is implemented, whereby pushes to the stack do not have to read data from the external memory in to a cache, and whereby pops from the stack do not cause stale stack data to be written back from the cache to the external memory.

Abstract: The present invention provides a system for and a method of data cache management. In accordance with an embodiment, of the present invention, a method of cache management is provided. A request for access to data is received. A sample value is assigned to the request, the sample value being randomly selected according to a probability distribution. The sample value is compared to another value. The data is selectively stored in the cache based on results of the comparison.

Abstract: A microprocessor includes one or more N-way caches and a way prediction logic that selectively enables and disables the cache ways so as to reduce the power consumption. The way prediction logic receives an address and predicts in which one of the cache ways the data associated with the address is likely to be stored. The way prediction logic causes an enabling signal to be supplied only to the way predicted to contain the requested data. The remaining (N?1) of the cache ways do not receive the enabling signal. The power consumed by the cache is thus significantly reduced.

Abstract: One or more multi-level NAND flash cells are operated so as to store only single-level data, and these operations achieve an increased level of charge separation between the data states of the single-level operation by requiring a write to both the upper and lower pages, even though only one bit of data is being stored. That is, the second write operation increases the difference in floating gate charge between the erased state and the programmed state of the first write operation without changing the data in the flash memory cell. In one embodiment, a controller instructs the flash memory to perform two write operations for storing a single bit of data in an MLC flash cell. In another embodiment, the flash memory recognizes that a single write operation is directed a high reliability memory area and internally generates the required plurality of programming steps to place at least a predetermined amount of charge on the specified floating gate.

Abstract: Methods and apparatuses are provided for use with smartcards or other like shared computing resources. A global smartcard cache is maintained on one or more computers to reduce the burden on the smartcard. The global smartcard cache data is associated with a freshness indicator that is compared to the current freshness indicator from the smartcard to verify that the cached item data is current.

Abstract: Provided is a storage control system in which a number of storage controllers are connected, and restored data is forwarded from one storage controller to the other storage controller. This storage control system is configured by a first storage controller and a second storage controller being connected in a mutually communicable manner, and which performs data processing according to a request from a host system, the first storage controller having a virtual volume associated with a logical volume of the second storage controller; a cache memory associated with the virtual volume; and a control unit for controlling the data processing between the cache memory and the virtual volume; wherein the control unit purges the storage area of the cache memory corresponding to the virtual volume accessed by the host system upon storing the restored data of the logical volume in the cache memory.

Abstract: Systems and methods for aggregating transmit completion interrupts for multiple packets are provided. A network device can include a buffer with multiple memory locations capable of temporarily storing a packet being transmitted across the network via the network device and nodes connected to the network device. The network device can include a high watermark for determining when to process transmit completion interrupts. If the number of packets stored in the memory exceeds the high watermark, an aggregated transmit completion interrupt for all of the packets can be processed. Otherwise, the network device waits until sufficient packets are received to reach the high watermark.

Abstract: Methods and systems for simplified error recovery in a SAS device. A SAS device (e.g., a SAS/SSP target device such as a storage device) enhanced in accordance with features and aspects hereof NAKs a received frame that has an error and then NAKS all subsequently received frames, regardless of whether received with or without error, until the connection is closed. The second SAS device (e.g., a SAS/SSP initiator) then performs required error recovery by re-establishing a connection and re-transmitting all previously NAKed frames. The enhanced SAS thereby simplifies logic for error recovery.

Abstract: A method is employed to manage a memory, e.g., a flash memory, including a plurality of paired pages. Each paired page includes a page and a respective risk zone. For each write command, at least one unwritten page is selected for writing new data. For each unwritten page whose risk zone includes at least one written page, each written page is copied or backed up, and the new data is written to the unwritten page. For each unwritten page whose risk zone lacks a written page, the new data is written to the unwritten page. In an embodiment, the written page is copied only if the unwritten page and the written page are operated by different write commands.

Abstract: The invention provides a method for improving frequency-based caching algorithms by maintaining a stable history of evicted items. One embodiment involves a process for caching data in a cache memory including logical pages including, upon detecting that a first page is being evicted from the cache memory, performing an addition process by adding metadata of the first page to a stable history list. Upon detecting a cache miss for a second page, if the stable history list contains metadata for the second page, then removing the second page metadata from the stable history list and applying a promotion determination for the second page to determine a priority value for the second page metadata and placing the second page in the cache memory based on the priority data. Upon detecting that metadata of a third page is to be evicted from the stable history list, applying an eviction determination to evict metadata of the third page from the stable history list based on a predetermined caching rule.

Abstract: A data file on a storage media is processed during playback or execution to identify unreadable data. Replacement data corresponding to the unreadable data is obtained over a communications network, and the replacement data is used to playback or execute the data file as if the data file does not contain any unreadable data.

Abstract: A storage apparatus includes a first storage device that primarily stores data, a second storage device, having a property differing from the first storage device, that secondarily stores the data, and a control device that controls a data migration between the first storage device and the second storage device. The control device includes a storage section that stores attribute information on the data stored in the first storage device, a priority determination section which, based on the attribute information, determines a priority for the data migration from the first storage device to the second storage device, and a data migration section which, based on the priority, causes the data to migrate from the first storage device to the second storage device.

Abstract: A method to perform a least recently used (LRU) algorithm for a co-processor is described, which co-processor in order to directly use instructions of a core processor and to directly access a main storage by virtual addresses of said core processor comprises a TLB for virtual to absolute address translations plus a dedicated memory storage also including said TLB, wherein said TLB consists of at least two zones which can be assigned in a flexible manner more than one at a time. Said method to perform a LRU algorithm is characterized in that one or more zones are replaced dependent on an actual compression service call (CMPSC) instruction.

Abstract: A system for determining a cache line to replace is described. In one embodiment, the system includes a cache comprising a plurality of cache lines. The system further includes an identifier configured to identify a cache line for replacement. The system also includes a control logic configured to determine a value of the identifier selected from an incrementer, a cache maintenance instruction, or remains the same.

Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.

Abstract: An apparatus, system, and method are disclosed for selecting a space efficient repository. A cache receives write data. A destage module destages the data sequentially to a coarse grained repository such as a stride level repository and destages a directory entry for the data to a coarse grained directory such as a stride level directory if the data satisfies a repository policy. In addition, the destage module destages the data to a fine grained repository such as a track level repository overwriting an existing data instance and destages the directory entry to a fine grained directory such as a track level directory if the data does not satisfy the repository policy.

Abstract: Systems and methods for sharing a physical cache among one or more clients in a stream data processing pipeline are described. One embodiment, among others, is directed to a system for sharing caches between two or more clients. The system comprises a physical cache memory having a memory portion accessed through a cache index. The system further comprises at least two virtual cache spaces mapping to the memory portion and at least one virtual cache controller configured to perform a hit-miss test on the active window of the virtual cache space in response to a request from one of the clients for accessing the physical cache memory. In accordance with some embodiments, each of the virtual cache spaces has an active window which has a different size than the memory portion. Furthermore, data is accessed from the corresponding location of the memory portion when the hit-miss test of the cache index returns a hit.

Abstract: The present invention relates generally to a method and system for efficiently identifying a cache entry for cast out in relation to scanning a predetermined sampling subset of pseudo-randomly sampled cached entries and determining a least recently used (LRU) entry from the scanned cached entries subset, thereby avoiding a comprehensive review of all of or groups of the cached entries in the cache at any instant. In one or more implementations, a subset of the data entries in a cache are randomly sampled, assessed by timestamp in a doubly-linked listing and a least recently used data entry to cast out is identified.

Abstract: A method and apparatus for handling reusable and non-reusable code is herein described. Page table entries include code reuse and locality fields to hold hints for associated pages. If a code reuse and locality field holds a non-reusable value to indicate an associated page holds non-reusable code, then an instruction decoded from the associated page is not stored in the trace to obtain maximum efficiency and power savings from the trace cache and decode logic.