Abstract: A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Abstract: A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel.

Abstract: The invention provides techniques for reducing the port pressure of a clustered processor. In an illustrative embodiment, the processor includes multiple clusters of execution units, with each of the clusters having a portion of a register file and a portion of a predicate file associated therewith, such that a given cluster is permitted to write to and read from its associated portions of the register and predicate files. A replication technique in accordance with the invention reduces port pressure by replicating, e.g., a register lock file and a predicate lock file of the processor for each of the clusters. The replicated files vary depending upon whether the technique is implemented with a write-only interconnection or a read-only interconnection.

Abstract: Disclosed is a register file used in a multiprocessor composition composed of a plurality of processor elements, the register file having a plurality of words and being provided for each of the plurality of processor elements, wherein: the plurality of words are divided into a word part that can be simultaneously accessed by some of the plurality of processor elements to use in common with other processor element, and a word part that can be accessed only by its own processor element.

Abstract: A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor.

Abstract: Improved method and apparatus for facilitating fast barrier synchronization in a parallel-processing system. A single input signal and a single output signal, and a single bit of state (“barrier_bit”) is added to each processor to support a barrier. The input and output signal are coupled to a dedicated barrier-logic circuit that includes memory-mapped bit-vector registers to track the “participating” processors and the “joined” processors for the barrier. A “bjoin” instruction executed in a processor causes a pulse to be sent on the output signal, which in turn causes that processor's bit in the dedicated barrier-logic circuit's “joined” register to be set.

Abstract: A general purpose accelerator board and acceleration method comprising use of: one or more programmable logic devices; a plurality of memory blocks; bus interface for communicating data between the memory blocks and devices external to the board; and dynamic programming capabilities for providing logic to the programmable logic device to be executed on data in the memory blocks.

Abstract: A module connection assembly connects modules in a torus configuration that can be changed remotely. In particular, a single module can be added to or deleted from the configuration by remotely switching from conducting paths that provide end-around electrical paths to conducting paths that provide pass-through electrical paths. The assembly includes two backplanes, a first set of module connectors for electrically connecting modules to one of the backplanes, and a second set of module connectors for electrically connecting modules to the other backplane. The assembly further includes configuration controllers. Each configuration controller selects between end-around electrical paths that electrically connect multiple module connectors of the first set to each other, and pass-through electrical paths that electrically connect module connectors of the first set to module connectors of the second set.

Abstract: A processor particularly useful in multimedia applications such as image processing is based on a stream programming model and has a tiered storage architecture to minimize global bandwidth requirements. The processor has a stream register file through which the processor's functional units transfer streams to execute processor operations. Load and store instructions transfer streams between the stream register file and a stream memory; send and receive instructions transfer streams between stream register files of different processors; and operate instructions pass streams between the stream register file and computational kernels. Each of the computational kernels is capable of performing compound vector operations. A compound vector operation performs a sequence of arithmetic operations on data read from the stream register file, i.e., a global storage resource, and generates a result that is written back to the stream register file.

Abstract: A pipelined data processing unit includes an instruction sequencer and n functional units capable of executing n operations in parallel. The instruction sequencer includes a random access memory for storing very-long-instruction-words (VLIWs) used in operations involving the execution of two or more functional units in parallel. Each VLIW comprises a plurality of short-instruction-words (SIWs) where each SIW corresponds to a unique type of instruction associated with a unique functional unit. VLIWs are composed in the VLIW memory by loading and concatenating SIWs in each address, or entry. VLIWs are executed via the execute-VLIW (XV) instruction. The iVLIWs can be compressed at a VLIW memory address by use of a mask field contained within the XV1 instruction which specifics which functional units are enabled, or disabled, during the execution of the VLIW. The mask can be changed each time the XV1 instruction is executed, effectively modifying the VLIW every time it is executed.

Abstract: A parallel processor is provided that includes integrated debugging capabilities. The processor includes a pipelined processing engine, having an array of processing element complex stages, and input and output header buffers. A debug system is provided that, when triggered, may put some or all of the processing element complexes into a debug mode of operation. When a complex is in debug mode, examination of internal stages of the component circuits of the complex may occur, in order to facilitate debugging of software and hardware errors that may occur during operation of the processor.

Abstract: In a SIMD architecture having a two dimensional array of processing elements, where a controller broadcasts instructions to all processing elements in the array, a dynamically reconfigurable switching means useful to connect four of the processing elements in the array into a group in accordance with either the broadcast instruction of the controller or a special communication instruction held in one processing element of the group, the switch includes at least one dataline connected to each processing element in the group. A multiplexer is connected to each data line and to the controller and to a configuration register. It is adapted to load the special communication instruction from the one processing element in the group into a configuration register and to operate in accord with either the broadcast instruction from the controller or the contents of the configuration register to select one of the four data lines as a source of data and applying the data therefrom to a source output port.

Abstract: A single chip application specific integrated circuit (ASIC) which provides a flexible, modular interface between a subsystem and a standard system bus. The ASIC includes a microcontroller/microprocessor, a serial interface for connection to the bus, and a variety of communications interface devices available for coupling to the subsystem. A three-bus architecture, utilizing arbitration, provides connectivity within the ASIC and between the ASIC and the subsystem. The communication interface devices include UART (serial), parallel, analog, and external device interface utilizing bus connections paired with device select signals. A low power (sleep) mode is provided as is a processor disable option.

Abstract: A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Abstract: A processing array including a plurality of processing elements; and an interconnection network connected to all of the processing elements for carrying data messages between the processing elements, wherein each of the processing elements of the plurality of processing elements includes a parity generating circuit for generating a parity bit for a first data message that is transmitted by that processing element over the interconnection network to another processing element among the plurality of processing elements; and a parity checking circuit for checking parity of a second data message as it is received by that processing element over the the interconnection network, the parity checking and parity generating circuits being separate from each other and enabling that processing element to generate parity for the first data message being sent by that processing element while simultaneously checking parity of the second message received by that processing element.

Abstract: An apparatus and method minimizes processing resource of a host system during service of interrupts generated closely in time by at least one peripheral device. The present invention determines, before the end of a prior interrupt service routine for a prior interrupt, a predicted interrupt time point when a subsequent interrupt will be generated by the at least one peripheral device. The host system operates in a polling mode if the predicted interrupt time point is before a predetermined time period after the end of the prior interrupt service routine. Thus, the host system avoids the processing resources needed for context switching time when the subsequent interrupt is generated closely in time from the prior interrupt. The host system operates in an interrupt mode if the predicted interrupt time point is after the predetermined time period after the end of the prior interrupt service routine.

Abstract: An image-forming system is constituted by connecting a plurality of digital copying machines to a communication apparatus so that the digital copying machines can transmit and receive image information with each other. As an instruction for image processing is inputted at any of the digital copying machines, a control section of the digital copying machine outputs the image information to a digital copying machine that is capable of carrying out the image processing. The digital copying machine that is assigned the image processing carries out a predetermined image processing on the image information and returns the processed image information via the communication apparatus. The image information is then visualized by a digital copying machine that receives the image information.

Abstract: A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Abstract: A technique reduces the latency of inter-reference ordering between sets of memory reference operations in a multiprocessor system having a shared memory that is distributed among a plurality of processors that share a cache. According to the technique, each processor sharing a cache inherits a commit-signal that is generated by control logic of the multiprocessor system in response to a memory reference operation issued by another processor sharing that cache. The commit-signal facilitates serialization among the processors and shared memory entities of the multiprocessor system by indicating the apparent completion of the memory reference operation to those entities of the system.

Abstract: A dynamically reconfigurable FPGA includes an array of tiles on a logic plane and a plurality of memory planes. Each tile has associated storage elements on each memory plane, called local memory. This local memory allows large amounts of data to pass from one FPGA configuration (memory plane) to another with no external memory access, thereby transferring data to/from the storage elements in the logic plane at very high speed. Typically, all the local memory can be simultaneously transferred to/from other memory planes in one cycle. Each FPGA configuration provides a virtual instruction. The present invention uses two different types of virtual instructions: computational and pattern manipulation instructions. Computational instructions perform some computation with data stored in some pre-defined local memory pattern. Pattern manipulation instructions move the local data into different memory locations to create the pattern required by the next instruction.

Abstract: A node disjoint path forming method for a hypercube having a damaged node which is capable of using unused nodes (surplus nodes) in an n-number of node disjoint paths each having a length of n with respect to n-dimensional hypercubes more than 4-cube, so that it is possible to obtain an n-number of node disjoint paths each having a length of n even though there are damaged nodes. The method includes the steps of a first step for forming a linear arrangement consisting of an n-number of integers (0, 1, 2, . . .

Abstract: A method of executing coded instructions in a dynamically configurable multiprocessor having shared execution resources including steps of placing a first processor in an active state upon booting of the multiprocessor. In response to a processor create command, a second processor is placed in an active state. When either the first or second processor encounter a cache miss that has to be serviced by off-chip cache the processor requiring service is placed in nap state in which instruction fetching for that processor is disabled. When either the first or second processor encounter a cache miss that has to be serviced by main memory, the processor requiring services I placed in a sleep state by flushing all instructions from the processor in the sleep state and disabling instruction fetching for the processor in the sleep state.

Abstract: An array processor includes processing elements arranged in clusters which are, in turn, combined in a rectangular array. Each cluster is formed of processing elements which preferably communicate with the processing elements of at least two other clusters. Additionally each inter-cluster communication path is mutually exclusive, that is, each path carries either north and west, south and east, north and east, or south and west communications. Due to the mutual exclusivity of the data paths, communications between the processing elements of each cluster may be combined in a single inter-cluster path. That is, communications from a cluster which communicates to the north and east with another cluster may be combined in one path, thus eliminating half the wiring required for the path. Additionally, the length of the longest communication path is not directly determined by the overall dimension of the array, as it is in conventional torus arrays.

Abstract: A configurable computing architecture (10) has its functionality controlled by a combination of static and dynamic control, wherein the configuration is referred to as static control and instructions are referred to as dynamic control. A reconfigurable data path (12) has a plurality of elements including functional units (32, 36), registers (30), and memories (34) whose interconnection and functionality is determined by a combination of static and dynamic control. These elements are connected together, using the static configuration, into a pipelined data path that performs a computation of interest. The dynamic control signals (21) are suitably used to change the operation of a functional unit and the routing of signals between functional units. The static control signals (23) are provided each by a static memory cell (62) that is written by a host (13). The controller (14) generates control instructions (16) that are interpreted by a control path (18) that computes the dynamic control signals.

Abstract: Modules of a data processing system are configured by providing a configuration file that includes configuration file blocks, a respective one of which contains configuration information for a respective one of the modules. A configuration file interface is also provided for each of the modules. A configuration file interface identifies the configuration file block that contains configuration information for the associated module and consumes the configuration block so identified. A pipe serially passes a configuration file block to the configuration file interfaces, until one of the configuration file interfaces identifies a configuration file block. Configuration file blocks continue to be passed until all of the configuration file blocks have been passed to the appropriate configuration file interface.

Abstract: A system and method for generating a program to enable reassignment of data items among processors in a massively-parallel computer to effect a predetermined rearrangement of address bits. The computer has a plurality of processing elements, each including a memory. Each memory includes a plurality of storage locations for storing a data item, each storage location within the computer being identified by an address, comprising a plurality of address bits having a global portion comprising a processing element identification portion and a local portion identifying the storage location within the memory of the particular processing element. The system generates a program to facilitate use of a predetermined set of tools to effect a reassignment of data items among processing elements and storage location to, in turn, effect a predetermined rearrangement of address bits. The system includes a global processing portion and a local processing portion.

Abstract: The present invention relates to multiprocessors which has several microprocessors on a single chip. Efficiency is improved by stripping certain functions that are used less freely from the microprocessor and sharing these functions between several symmetric microprocessors. This method allows each CPU to occupy a smaller area while preserving complete symmetry of capability for software simplification. For example, the shared execution units can include the floating point unit and multimedia execution units.

Abstract: A system interconnect architecture and associated arbitration scheme that provides for the interleaving of multiple accesses to a shared system resource by multiple components on a data block by data block basis. According to one embodiment, an access request is granted "immediately" upon receipt such that the effective access latency between an access request and the transfer of a first data block (e.g. a byte. a word, a long word, and a double long word as determined by the width or throughput of the data path) for the access is the minimum access latency to the shared system resource. If a second access request is received while a first access is being performed, the second access request is granted immediately, and the first and second access are thereafter interleaved such that data blocks of the accesses are alternately transferred by the system interconnect.

Abstract: A system and method which enables a plurality of threads in a multithreaded application to each access per-thread copies of GPIB global variables in a GPIB system. According to the present invention, the plurality of threads use a special set of thread-local GPIB calls to perform the per-thread accesses. Whenever a thread first makes a GPIB call, the GPIB driver software begins maintaining a private copy of all of the GPIB global variables for the respective thread. The driver preferably maintains a separate private copy for each thread. Later, when the thread desires to access a per-thread copy of one or more global variables, the thread uses a thread-local GPIB call to perform the per-thread access. The thread-local functions used to access these per-thread GPIB global variables are ThreadIbsta, ThreadIberr, ThreadIbcnt, and ThreadIbcntl.

Abstract: In a superscalar processor for fetching a prescribed peak number of instructions in parallel in each period until such instructions are fetched to a predetermined peak number, such as ten, an instruction parallel issue and execution administrating device comprises a forward map buffer for a forward map indicative of a result of each instruction for use as an operand by which one of other instructions of the predetermined peak number. The forward map is developed before the result is actually produced and is used, after the actual production, to indicate which one of such results should be used as the operand by the above-mentiond one of the other instructions.

Abstract: A software implementation of a modem, particularly designed to execute on a general purpose host processor, controlled by a non-real-time, multi-tasking operating system (OS), such as the Windows 95 OS. The software modem is scaleable and portable. In this fashion, communication protocols (particularly datapumps) may be easily added to, or removed from, the system, and the modem may be easily adapted for use on other types of processors and operating systems. The controller and datapump portions execute as a plurality of interacting subsystems, each of which can execute at at least one of several priority levels. A HRT level routine is responsible for handling an ASIC that buffers transmit and receive samples destined to and received from the phone lines. A SRT level task includes logic that needs time functionality, but which is not time-critical like the HRT logic. BRT routines execute in an event-driven basis and are used for many controller functions.