Abstract: A memory component, on a single integrated circuit, operated as a slave to an external master, includes a RAM, one or more configuration registers, data formatting logic, and associated control logic. The behavior of the memory component, and in particular the selection of a burst transfer format, is controllable via configuration register bits in the one or more configuration registers. Specifically, based on a format selection specified by the configuration bits, the control logic determines the sequence-length of the data transfers between the RAM and the external master. Other than the sequence-length, the data is not otherwise altered during the data transfers.

Abstract: An electronic queue management system for implementation on a chip. The queue management system comprises a plurality of primitive queue elements each including a register for a next-pointer and a register for a queue number. The next-pointer values may be selected via a register input and can be fed out via a registered output. Such queue elements are associated with a respective entry in a central array which stores the data belonging to the actual request. The separation of the data array and queue elements facilitates queue management as the data amounts are quite large compared to the small amount of data being required for the pre logic of the queue management system. Multiple add requests and multiple remove requests operations for different queue elements may be concurrently achieved in a single cycle.

Abstract: A method and an apparatus for configuration of multiple context processing elements (MCPEs)are described. According to one aspect of the invention, the structure that joins the MCPE cores into a complete array in one embodiment is actually a set of several mesh-like interconnect structures. Each interconnect structure forms a network, and each network is independent in that it uses different paths, but the networks join at MCPE input switches. The network structure of one embodiment of the present invention is comprised of a local area broadcast network (level 1), a switched interconnect network (level 2), a shared bus network (level 3), and a broadcast network. In one embodiment, the level 3 network is used to carry configuration data for the MCPEs while the broadcast network is used to carry configuration data for the level 3 network drivers and switches. In one embodiment, the level 3 network is bidirectional and dynamically routable.

Abstract: To execute all processing in an array section of an array-type processor, each processor must execute processing of different types, i.e., processing of an operating unit and processing of a random logic circuit, which limits its size and processing performance. A data path section including processors arranged in an array are connected via programmable switches to primarily execute processing of operation and a state transition controller configured to easily implement a state transition function to control state transitions are independently disposed. These sections are configured in customized structure for respective processing purposes to efficiently implement and achieve the processing of operation and the control operation.

Abstract: A matrix of routing cells forming a cross-bar decoder (310). Signal triplets are coupled through the cross-bar decoder (310) based on control by a microprocessor. A register (50) provide control signals to the cross-bar decoder (310) to either activate or deactivate routing of the triplet signals through cells of the cross-bar decoder (310). The routing cells are arranged in a matrix of columns and rows. Each row of cells is associated with a common data signal input, and each column of the matrix is associated with a common I/O pin. The cells are individually enabled by the microprocessor so that any data signal can be coupled to any of the I/O pins. In addition to routing data signals through the cells, other signals are also routed through the cells.

Abstract: A multi-processor computer system is described in which transaction processing in each cluster of processors is distributed among multiple protocol engines. Each cluster includes a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture. The interconnection controller in each cluster comprises a plurality of protocol engines for processing transactions. Transactions are distributed among the protocol engines using destination information associated with the transactions.

Abstract: A single-instruction multiple-data (SIMD) array processor providing enhanced data transfer efficiency. The SIMD array processor includes at least one memory and a plurality of mesh-connected processing elements configured in an array. Each processing element in the array includes at least one “narrow” memory buffer, at least one “wide” data register, and at least one “wide” communication register. The narrow memory buffer is adapted to transfer data serially between the memory and the wide data register, the wide data register is adapted to transfer data directly to the wide communication register, and the wide communication register is adapted to transfer data directly to the communication register of a neighboring processing element while the memory buffer is accessing data from the memory.

Abstract: A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading).

Abstract: An associative processor includes a plurality of arrays of content addressable memory (CAM) cells and a plurality of tags registers in a tags logic block. Different tags registers are associated with different CAM cell arrays at will, to support parallel execution of the same or different arithmetical operations on two or more CAM cell arrays, and to support pipelined arithmetical operations by having two CAM cell arrays share a tags register to transfer data from one CAM cell array to another using appropriate compare and write operations. All the CAM cell arrays share the same mask and pattern registers. Preferably, at least one tags register is located physically between two of the CAM cell arrays.

Abstract: An arithmetical device, and an image processing apparatus, able to handle various types of operation, able to easily handle even methods of operation which had not been envisioned at the point of time of development, and having a sufficient drawing capability for drawing in real time in three-dimensional graphics by electrically changing connections among a plurality of operation circuits, that is, an arithmetical device 201 having register files (RF) 2011 and an operation unit pool 2012, wherein the operation unit pool 2012 has at least one operation unit portion 20121 to 20124 for transferring data with the register files 2011 by data buses BS, and each of the operation portions 20121 to 20124 includes a plurality of operation units (adders, multipliers, multipliers/adders, etc.) OP1 to OP8 and a connection circuit network CCN between the register files 2011 and the operation units OP and able to change electrical connection among the operation units OP1 to OP8.

Abstract: The present invention relates to the control of an array of processing elements in a parallel processor using row and column select lines. For each column in the array, a column select line connects to all of the processing elements in the column. For each row in the array, a row select line connecting to all of the processing elements in the row. A processing element in the array may be selected by activation of its row and column select lines.

Abstract: A system and method are disclosed which allow unstored computed results to be accessed without the normal overhead associated with traditional data forwarding and bypass techniques. Through the use of multiplexers and bi-directional OR controllers the unstored data is readily accessible for use before it is stored in a register file. The circuitry used also allows bi-directional travel across a register file or bank as information is passed between the bi directional controllers used. Latches can also be used in the circuitry. Additionally, the features of the invention allow the required number of select signals fed to the multiplexers used to be reduced over conventional methods. These reductions are possible through circuitry disclosed herein.

Abstract: A computer system comprising a first block which includes multiple processing subsystem, a second block which includes multiple processing subsystem, a third block which includes multiple processing subsystem, a fourth block which includes multiple processing subsystem, a first communication and processing subsystem that interconnects subsystem of the first and second blocks, a second communication and processing subsystem that interconnects subsystem of the third and fourth blocks, a third communication and processing subsystem that interconnects subsystem of the first and fourth blocks; and a fourth communication and processing subsystem that interconnects subsystem of the second and third blocks, wherein respective subsystem include a respective processing elements and a respective communication and processing unit interconnecting the respective processing elements.

Abstract: An interface circuit for interfacing one or more compute nodes to a mesh is capable of serving a wide range of MPP systems. The interface circuit includes a first bus interface for interfacing with a first bus, a second bus interface for interfacing with a second bus, and a mesh interface. Control logic is coupled to the first bus interface, the second bus interface, and the mesh interface. The control logic includes circuitry for placing the interface circuit in a first mode in which a compute node resides on the first bus and a second mode in which the compute node resides on the second bus. The first bus may be a split-envelope bus such as the MIPS avalanche bus. The second bus may be a single-envelope bus such as the PCI bus.

Abstract: An asynchronous processor that has reshuffled processes to implement precharge logic.

Abstract: This invention relates to a network of parallel elementary processors, tolerant to the faults of these processors including said elementary processors, spare elementary processors, elements interconnecting these processors and a control unit, and alternately a series of interconnecting element lines and processor lines, each processor being surrounded by four interconnecting elements, the processor lines being elementary processor lines, the last processor line being a line of spare processors, the edge elements of the network being interconnecting elements, wherein the control unit, connected to processors and interconnecting elements, sends instructions to the processors, controls the interconnecting elements, and checks the integrity of these processors.

Abstract: A processor isolation technique enhances debug capability in a highly integrated multiprocessor circuit containing a programmable arrayed processing engine for efficiently processing transient data within an intermediate network station of a computer network. The technique comprises a mechanism for programming a code entry point for each processor of a processor complex utilizing a register set that is accessible via an out-of-band bus coupled to a remote processor of the engine. The programmable entry point mechanism operates in conjunction with a bypass capability that passes transient data through a processor complex that is not functional, not running or otherwise unable to process data. Another aspect of the debug technique involves the ability to override completion control signals provided by each processor complex in order to advance a pipeline of the processing engine.

Abstract: A device for a hierarchical connection of a plurality of functional units in a processor comprises a first connector with at least two inputs and an output, which is adapted for connecting one of the inputs to the output, a second connector with at least one input and an output, which is adapted for connecting the input to the output, and a buffer connected between the output of the second connector and the input of the first connector for buffering, for at least one clock cycle, a signal applicable to the at least one input of the second connector before H is forwarded to a further input of the first connector. The output of the first connector is connected to an input of a first functional unit. An output of a second functional unit is connected to a first input of the at least two Inputs of the first connector. The at least one input of the second connector is connected to a third functional unit.

Abstract: A component architecture for digital signal processing is presented. A two dimensional reconfigureable array of identical processors, where each processor communicates with its nearest neighbors, provides a simple and power-efficient platform to which convolutions, finite impulse response (“FIR”) filters, and adaptive finite impulse response filters can be mapped. An adaptive FIR can be realized by downloading a simple program to each cell. Each program specifies periodic arithmetic processing for local tap updates, coefficient updates, and communication with nearest neighbors. During steady state processing, no high bandwidth communication with memory is required.

Abstract: A common scalar/vector data cache apparatus and method for a scalar/vector computer. One aspect of the present invention provides a computer system including a memory. The memory includes a plurality of sections. The computer system also includes a scalar/vector processor coupled to the memory using a plurality of separate address busses and a plurality of separate read-data busses wherein at least one of the sections of the memory is associated with each address bus and at least one of the sections of the memory is associated with each read-data bus. The processor further includes a plurality of scalar registers and a plurality of vector registers and operating on instructions which provide a reference address to a data word. The processor includes a scalar/vector cache unit that includes a cache array, and a FIFO unit that tracks (a.) an address in the cache array to which a read-data value will be placed when the read-data value is returned from the memory, and (b.

Abstract: A system is described that is broadly directed to a system of integrated circuit components. The system comprises a plurality of nodes that are interconnected by communication links. A random access memory (RAM) is connected to each node. At least one functional unit is integrated into each node, and each functional unit is configured to carry out a predetermined processing function. Finally, each RAM includes a coherency mechanism configured to permit only read access to the RAM by other nodes, the coherency mechanism further configured to permit write access to the RAM only by functional units that are local to the node.

Abstract: Method, system and program storage device are provided for implementing a register pipe between processing engines of a multiprocessor computing system. A register pipe includes at least one first register of a first processing engine and at least one second register of a second processing engine. Data is transferred between the first processing engine and the second processing engine through the register pipe without passing through memory. In one embodiment, general purpose registers within the first processing engine and within the second processing engine are employed to implement the register pipe. A control mechanism is provided within each processing engine to dynamically enable or disable the register pipe coupling any two processing engines of the multiprocessor computer system. A technique for broadcasting to multiple register pipes and for implementing barrier synchronization using a register pipe addressed to a processing engine itself are also provided.

Abstract: A multiprocessor computer system comprises a plurality of processing element nodes and an interconnect network interconnecting the plurality of processing element nodes. An interface circuit is associated with each one of the plurality of processing element nodes. The interface circuit has a lookup table having n-number of routing entries for a given destination node. Each one of the n-number of routing entries associated with a different class of traffic. The network traffic is routed according to the class.

Abstract: An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. A B16×16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The B16×16 tile is a nesting of a B2×2 tile that includes a two by two array of four B1 blocks. The routing resources in the middle level of hierarchy are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. The expressway routing channels M1, M2, and M3 are segmented, and between each of the segments in the expressway routing channels M1, M2, and M3 are disposed extensions that can extend the expressway routing channel M1, M2, or M3 an identical distance along the same direction. The expressway routing channels M1, M2, and M3 run both vertically through every column and horizontally through every row of B2×2 tiles.

Abstract: A surface computer includes an address generator for generating an address for adjusting surface region data concerning at least a storage region and a concurrent computer, provided at a subsequent stage of the address generator, having a plurality of unit computers.

Abstract: A data processor controller comprising a first processor for generating data processor instructions at a first rate and an instruction multiplying circuit for receiving the data processor instructions at the first rate and being a arranged to multiply the instructions and forward the multiplied instructions to a data processor at a second rate substantially greater than the first rate is disclosed. The first processor outputs a stream of compounded data processor instructions and the multiplying circuit separates the compounded instructions into a single stream of individual instructions in a non-compounded format. Multiplication is effectively achieved by repeating both single and blocks of data processor instructions. The effective bandwidth between the first processor and the data processor is multiplied by the multiplying circuit which takes advantage of the different sizes of data pathways available between the first processor and the data processor.

Abstract: A computer system comprising a first block which includes multiple processing subsystem, a second block which includes multiple processing subsystem, a third block which includes multiple processing subsystem , a fourth block which includes multiple processing subsystem, a first communication and processing subsystem that interconnects subsystem of the first and second blocks, a second communication and processing subsystem that interconnects subsystem of the third and fourth blocks, a third communication and processing subsystem that interconnects subsystem of the first and fourth blocks; and a fourth communication and processing subsystem that interconnects subsystem of the second and third blocks, wherein respective subsystem include a respective processing elements and a respective communication and processing unit interconnecting the respective processing elements.

Abstract: Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one evaluation unit is connected to the input of the next evaluation unit. A set of ‘cascade’ connections provides access to the intermediate values. By tapping intermediate values from one processor, and feeding them to the next, a significant emulation speedup is achieved.

Abstract: The present invention provides a new crossbar switch which is implemented by a plurality of parallel chips. Each chip is completely programmable to couple to every node in the system, e.g., from one node to about one thousand nodes (corresponding to present-day technology limits of about one thousand I/O pins) although conventional systems typically support no more than 32 nodes. The crossbar switch can be implemented to support only one node, then one chip can be used to route all 64 bits in parallel for 64 bit microprocessors.

Abstract: A data-processing arrangement comprises a plurality of elementary circuits such as processing circuits [PRC] and memory circuits [MEM]. The data-processing arrangement further comprises a controller [MCP]. The controller [MCP] is programmed to successively apply, in response to a task-initialization data [TID], control data [CD] to different subsets of elementary circuits. This causes the data-processing arrangement to process a block of data [DB] in accordance with a certain data-processing chain [DPC]. Each subset of elementary circuits implements a different element [E] of the data-processing chain [DPC].

Abstract: Irregularities are provided in at least one dimension of a torus or mesh network for lower average path length and lower maximum channel load while increasing tolerance for omitted end-around connections. In preferred embodiments, all nodes supported on each backplane are connected in a single cycle which includes nodes on opposite sides of lower dimension tori. The cycles in adjacent backplanes hop different numbers of nodes.

Abstract: A method and an apparatus for configuring arbitrary sized data paths comprising multiple context processing elements (MCPEs) are provided. Multiple MCPEs may be chained to form wider-word data paths of arbitrary widths, wherein a first ALU serves as the most significant byte (MSB) of the data path while a second ALU serves as the least significant byte (LSB) of the data path. The ALUs of the data path are coupled using a left-going, or forward, carry chain for transmitting at least one carry bit from the LSB ALU to the MSB ALU. The MSB ALU comprises configurable logic for generating at least one signal in response to a carry bit received over the left-going carry chain, the at least one signal comprising a saturation signal and a saturation value. The MCPEs of the data path use configurable logic to manipulate a resident bit sequence in response to the saturation signal transmitted thereby reconfiguring, or changing the operation of, the data path in response to he saturation signal.

Abstract: A method and an apparatus for retiming in a network of multiple context processing elements in a network of multiple context processing elements are provided. A programmable delay element is configured to programmably delay signals between a number of multiple context processing elements of an array without requiring a multiple context processing element to implement the delay. The output of a first multiple context processing element is coupled to a first multiplexer and to the input of a number of serially connected delay registers. The output of each of the serially connected registers is coupled to the input of a second multiplexer. The output of the second multiplexer is coupled to the input of the first multiplexer, and the output of the first multiplexer is coupled to a second multiple context processing element. The first and second multiplexers are provided with at least one set of data representative of at least one configuration memory context of a multiple context processing element.

Abstract: A processing system includes a processor, a memory controller, and a memory subsystem. The memory controller includes a processor interface, a memory data interface, sequential transfer circuitry, and transaction processing logic. Randomly accessed data units of a first size are synchronously exchanged between the memory data interface of the memory controller and the memory subsystem via a transfer sequence comprising a predetermined plurality of sequential transfers of data units of a size smaller than the first size.

Abstract: An indirect VLIW (iVLIW) architecture is described which contains a minimum of two instruction memories. The first instruction memory (SIM) contains short-instruction-words (SIWs) of a fixed length. The second instruction memory (VIM), contains very-long-instruction-words (VLIWs) which allow execution of multiple instructions in parallel. Each SIW may be fetched and executed as an independent instruction by one of the available execution units. A special class of SIW is used to reference the VIM indirectly to either execute or load a specified VLIW instruction (called an “XV” instruction for “eXecute VLIW”, or LV for “Load VLIW”). In these cases, the SIW instruction specifies how the location of the VLIW is to be accessed. Other aspects of this approach relate to the application of data memory addressing techniques for execution or loading of VLIWs that parallel the addressing modes used for data memory accesses.

Abstract: A parallel processor system is constructed to include a pair of parallel buses (2, 3), pipeline buses (9), a plurality of processor nodes (1-1 to 1-N) having functions of carrying out an operation process in response to an instruction and transferring data, cluster switches (5-1 to 5-N, 6-1 to 6-N, 7-1a to 7-La, 7-1b to 7-+b, 8-1a to 8-Ma, 8-1b to 8-(M−1)b) having a plurality of connection modes and controlling connections of the parallel buses, the pipeline buses and the processor nodes, and a switch controller (4) controlling the connection mode of the cluster switches and coupling the processor nodes in series and/or in parallel.

Abstract: Systems and methods are presented to achieve crosstalk-free all-to-all exchange in optical multistage self-routing networks. The approach involves the computation of a Latin square and the subsequent decomposition of its rows to semi-permutations. Processors may then send messages to other processors in accord with these semi-permutations.

Abstract: An object oriented processor array includes a library of functional objects which are instantiated by commands through a system object and which communicate via a high level language. The object oriented processor array may be embodied in hardware, software, or a combination of hardware and software. Each functional object may include a discrete hardware processor or may be embodied as a virtual processor within the operations of a single processor. According to one embodiment, the object oriented processor array is formed on a single chip or on a single processor chip and an associated memory chip. When several objects are instantiated on a single chip, pins may be assigned to each object via a high level command language. Methods and apparatus for allocating memory to instantiated objects are disclosed. Methods and apparatus for scheduling when several virtual processors are embodied within the operations of a single microprocessor are also disclosed.

Abstract: A manifold array topology includes processing elements, nodes, memories or the like arranged in clusters. Clusters are connected by cluster switch arrangements which advantageously allow changes of organization without physical rearrangement of processing elements. A significant reduction in the typical number of interconnections for preexisting arrays is also achieved. Fast, efficient and cost effective processing and communication result with the added benefit of ready scalability.

Abstract: A component architecture for digital signal processing is presented. A two dimensional reconfigureable array of identical processors, where each processor communicates with its nearest neighbors, provides a simple and power-efficient platform to which convolutions, finite impulse response (“FIR”) filters, and adaptive finite impulse response filters can be mapped. An adaptive FIR can be realized by downloading a simple program to each cell. Each program specifies periodic arithmetic processing for local tap updates, coefficient updates, and communication with nearest neighbors. During steady state processing, no high bandwidth communication with memory is required.

Abstract: Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected together. The single physical machine with multiple physical processors and resources is subdivided by software into multiple partitions, each running a distinct copy, or instance, of an operating system. Each of the partitions has access to its own physical resources plus resources designated as shared. The partitioning is performed by assigning all resources with a configuration tree. None, some, or all, resources may be designated as shared among multiple partitions. Each individual operating instance will generally be assigned the resources it needs to execute independently and these resources will be designated as “private.” Other resources, particularly memory, can be assigned to more than one instance and shared.

Abstract: A method and an apparatus for retiming in a network of multiple context processing elements are provided. A programmable delay element is configured to programmably delay signals between a number of multiple context processing elements of an array without requiring a multiple context processing element to implement the delay. The output of a first multiple context processing element is coupled to a first multiplexer and to the input of a number of serially connected delay registers. The output of each of the serially connected delay registers is coupled to the input of a second multiplexer. The output of the second multiplexer is coupled to the input of the first multiplexer, and the output of the first multiplexer is coupled to a second multiple context processing element. The first and second multiplexers are provided with at least one set of data representative of at least one configuration memory context of a multiple context processing element.

Abstract: In a self-configuring store-and-forward computer network, a plurality of processors are each housed in an enclosure having a top surface and a bottom surface. Each processor has an associated block identification number. An array of m by n radially symmetric connectors are arranged on the top surface and on the bottom surface of each enclosure. Each connector has an associated connector identification number. The connectors physically and electronically couple the plurality of processors as a three-dimensional structure. Communications controller in each of the processors exchange the block and connector identification numbers between the processors and a host computer to determine an ordered list of connector numbers that is used to route messages between any of the processors and the host computer.

Abstract: A method for controlling a processor array by a host computer involves creating a graph of a plurality of nodes using a data connection component, configuring a broadcast tree from a spanning tree of the graph, propagating a first command from the host computer to a member of the processor array using the broadcast tree, configuring a reply tree from a spanning tree of the graph, transmitting a response from the member of the processor array to the host computer using the reply tree, and configuring the data connection component to send at least one message selected from the first command and the response on at least one run mode communication path.

Abstract: A method for transferring information within a mesh network that has an array of nodes defined by four quadrants. The method includes the initial step of transferring information from a set of nodes in one quadrant to a set of nodes located in an adjacent quadrant. The transfer of information simultaneously occurs in both a vertical and horizontal direction within the array. Information is then transferred between nodes within the same quadrant and subquadrants.

Abstract: A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading).

Abstract: A system includes a first and second integrated circuit and associated interconnect. The first integrated circuit is a memory component and includes a RAM, one or more configuration registers, and associated control logic. The second integrated circuit is a memory controller that is a master to the memory component. The behavior of the memory component, including selection from a number of different operating modes, is controllable via configuration register mode bits. The various modes include several transfer-length modes, where each mode corresponds to data transfers of a predetermined length. Based on the mode selection specified by the mode bits, the controller determines the length of the data transfers.

Abstract: An Internet imaging device, such as camera, scanner and digital television display, is disclosed. The device combines the advantages of platform-independent page description languages, such as Adobe PostScript 3, with an imaging device that connects directly to remote locations via the Internet. The device outputs image data and image processing commands in a platform-independent page description language via cordless communication such as a cellular phone. The data are transferred directly to remote display units, such as printers and digital televisions, thereby eliminating two personal computers (PCs): one at the input end of the communication and one at the output end. The device taught by the present invention need not include a flash memory or other storage medium, as images are transferred directly when generated.

Abstract: The present invention relates to a node connection apparatus. The 3-link node interconnection apparatus and parallel processing apparatus using the same confirm expanding nodes freely, only using fixed three connecting links, and are suitable to normal packaging method because of easy dividing into 2n (n>1) nodes. The apparatuses comprise the following nodes. The first node has three links connected to other nodes respectively. The second node has three links, one links of them is connected to the first node, and the other two links are in charge of connection of X+ direction, X− direction. The third node has three links, one link of them is connected to the first node, and the other two links are in charge of connection of Y+ direction, Y− direction. The fourth node has three links, one link of them is connected to the first node, and the other two links are in charge of connection of Z+ direction, Z− direction.

Abstract: A common scalar/vector data cache apparatus and method for a scalar/vector computer. One aspect of the present invention provides a computer system including a memory. The memory includes a plurality of sections. The computer system also includes a scalar/vector processor coupled to the memory using a plurality of separate address busses and a plurality of separate read-data busses wherein at least one of the sections of the memory is associated with each address bus and at least one of the sections of the memory is associated with each read-data bus. The processor further includes a plurality of scalar registers and a plurality of vector registers and operating on instructions which provide a reference address to a data word. The processor includes a scalar/vector cache unit that includes a cache array, and a FIFO unit that tracks (a.) an address in the cache array to which a read-data value will be placed when the read-data value is returned from the memory, and (b.