Abstract: A device having a variable output electrical characteristic includes first and second output terminals and a number of switching circuits, each switching circuit having two states. One of the states produces a first electrical effect (such as an increased resistance) between the first and second output terminals, and the other state produces a second electrical effect (such as no change in resistance) between the first and second output terminals. A processor generates control signals that are applied to the switching circuits to place the switching circuits into a desired state such that the variable output characteristic between the first and second terminals is set to a desired value, which may be input from a user.

Abstract: A parallel computer of this invention includes a plurality of memory elements and a plurality of processing elements and each of the processing elements is connected to logically adjacent memory elements. For example, the processing elements which corresponds to a logical position (i, j) is connected to the memory elements which correspond to a plurality of logical positions (i, j), (i, j+1), (i+1, j) and (i+1, j+1). It is preferable if each of the memory elements can be accessed from the exterior. According to this invention, efficient memory access can be made and the parallel processing can be performed at high speed without increasing the hardware amount and making the control operation complicated. Further, the operation speed of the image processing can be enhanced by constructing an image memory by use of a plurality of memory elements and causing the processing element to effect the image processing in a distributed and cooperative manner.

Abstract: A multi-chip module (“MCM”) and methods of operation and manufacture thereof. The MCM includes: (1) a substrate for supporting a plurality of separate integrated circuit (IC) chips thereon, (2) first and second separate IC chips mounted on the substrate, the first separate IC chip including first and second circuit portions coupled together by at least one signal conductor, and (3) interconnecting means that directly couples at least one signal conductor of the first separate IC chip to the second separate IC chip, the interconnecting means bypassing the second circuit portion of the first separate IC chip.

Abstract: Processing element to processing element switch connection control is described using a receive model that precludes communication hazards from occurring in a synchronous MIMD mode of operation. Such control allows different communication topologies and various processing effects such as an array transpose, hypercomplement or the like to be efficiently achieved utilizing architectures, such as the manifold array processing architecture. An encoded instruction method reduces the amount of state information and setup burden on the programmer taking advantage of the recognition that the majority of algorithms will use only a small fraction of all possible mux settings available. Thus, by means of transforming the PE identification based upon a communication path specified by a PE communication instruction an efficient switch control mechanism can be used.

Abstract: A method for exchanging information within a mesh network that has an array of nodes defined by four quadrants. The method includes the initial step of exchanging information from a set of nodes in one quadrant to a set of nodes located in an adjacent quadrant. The exchange of information simultaneously occurs in both a vertical and horizontal direction within the array. Information is then exchanged between nodes within the same quadrant and subquadrants.

Abstract: An associative signal processing apparatus for processing a plurality of samples of an incoming signal in parallel, the apparatus comprising: (a) an array, of processors, each processor including a multiplicity of associative memory cells, the memory cells being operative to perform: (i) compare operations, in parallel, on the plurality of samples of the incoming signal; and (ii) write operations, in parallel, on the plurality of samples of the incoming signal; and (b) an I/O buffer register including a multiplicity of associative memory cells, the register being operative to: (i) input the plurality of samples of the incoming signal to the array of processors in parallel by having the I/O buffer register memory cells perform at least one associative compare operation and the array memory cells perform at least one associative write operation; and (ii) receive, in parallel, a plurality of processed samples from the array of processors by having the array memory cells perform at least one associative compare o

Abstract: Disclosed is a method for all-to-all personalized exchange for a class of multistage interconnecting networks (MINs). The method is based on a Latin square matrix corresponding to a set of admissible permutations of a multistage interconnecting network. Disclosed are first and second methods for constructing a Latin square matrix used in the personalized exchange technique. Also disclosed is a generic method for decomposing all-to-all personalized exchange patterns into admissible permutations to form the Latin square matrix for self-routing networks which are a subclass of the MINs.

Abstract: A multiprocessor system having a total number of available CPUs partitioned into one or more smaller pools of CPUs called servers where the number of CPUs available to a server is reduced below the total number of available CPUs. Software licensing costs are thereby reduced because the number of CPUs available to run the operating system or ISV software has been reduced to the number of CPUs in the pool of the server rather than the total number of available CPUs in the multiprocessor system. In order to enforce the isolation of CPUs required by software licensing, separate identification codes, CPUIDs, that contain unique system serial numbers are assigned to each server in the multiprocessing system. The multiprocessor system has multiple CPUIDs, one for each server (each pool of CPUs that can execute operating systems and ISV software).

Abstract: In a data processing system of the type having multiple processor units coupled to one another by a bus means for interprocessor communications there is provided a fiber optic interconnection system to interconnect the bus means of multiple processor sections to one another, thereby allowing groups of the processor units to be physically spaced from one another. The fiber optic interconnect system includes, for each multiprocessor unit section functions to receive messages communicated on the interprocessor bus of that section for receipt by a destination processor of the other section, format the message for fiber optic transmission, and transmit the message; and circuitry for receiving messages on the fiber optic link, scheduling the message for transmission to the destination processor, and maintaining that scheduling in the face of receipt of another message for the same processor unit.

Abstract: A digital computer comprising a plurality of processors interconnected by a network for transferring messages among the processors. At least one processor generates messages of a configuration type. The network comprises a plurality of nodes interconnected in a tree pattern in a series of levels from a lower leaf level to an upper physical root level, with the leaf nodes connected to the processors. Each of the nodes includes a root flag that can be set or cleared in response to a message of the configuration type to establish the node as a logical root. For each node, if the node is a logical root it transfers messages received from a node at a lower level in the tree back down the tree, but if the node is not a logical root it transfers messages received at a lower level node to a higher level node.

Abstract: A data processing unit comprises an input section 1 for inputting first data from the outside, an operation section 2 for operating the first data inputted therefrom, to generate second data, a memory section 3 for storing the second data, an output section 4 for outputting the second data stored in the memory section to the outside, and a control section 5 for controlling the memory section to enable storing and outputting of the second data.

Abstract: A memory component, on a single integrated circuit, operated as a slave to an external master, includes a RAM, one or more configuration registers, data formatting logic, and associated control logic. The behavior of the memory component, and in particular the selection of a burst transfer format, is controllable via configuration register bits in the one or more configuration registers. Specifically, based on a format selection specified by the configuration bits, the control logic determines the sequence-length of the data transfers between the RAM and the external master. Other than the sequence-length, the data is not otherwise altered during the data transfers.

Abstract: A data processing system comprises a plurality of nodes and a serial data bus interconnecting the nodes in series in a closed loop, for passing address and data information. At least one processing node includes a processor, a printed circuit board and a memory which is partitioned into a plurality of sections, including a first section for directly sharable memory located on the printed circuit board, and a second section for block sharable memory. A local bus connects the processor, block sharable memory and printed circuit board, for transferring data in parallel from the processor to the directly sharable memory on the printed circuit board, and for transferring data from the block sharable memory to the printed circuit board.

Abstract: Selectively distributing a plurality of data items to a plurality of hardware destinations that share a common bus involves, for each one of the data items, determining which of the hardware destinations the data item should be distributed to, wherein at least one of the data items should be distributed to two or more hardware destinations. The data item is then supplied to the common bus and, for each of the hardware destinations to which the data item should be distributed, a corresponding hardware destination signal is generated that causes the data item to be received in the hardware destination from the common bus, wherein for each data item, the corresponding hardware destination signals are generated substantially simultaneously. This may be applied in a number of scenarios, including the distribution of data items to a plurality of processor boards, and to the distribution of data items to a plurality of channels within a single processor board.

Abstract: A parallel computer of this invention includes a plurality of memory elements and a plurality of processing elements and each of the processing elements is connected to logically adjacent memory elements. For example, the processing elements which corresponds to a logical position (i, j) is connected to the memory elements which correspond to a plurality of logical positions (i, j), (i, j+1), (i+1, j) and (i+1, j+1). It is preferable if each of the memory elements can be accessed from the exterior. According to this invention, efficient memory access can be made and the parallel processing can be performed at high speed without increasing the hardware amount and making the control operation complicated. Further, the operation speed of the image processing can be enhanced by constructing an image memory by use of a plurality of memory elements and causing the processing element to effect the image processing in a distributed and cooperative manner.

Abstract: A method/operator is disclosed that modifies dimension structures and relations during processing in a multidimensional data cube. The online “blowup” operator disclosed uses one or more hierarchical structures to expand a hypercube in order to reveal internal connections between attributes in relations associated with the hypercube. The operator is generic and may be applied to any dimension using hierarchical structures to guide the process. Furthermore, it is applicable to any data warehouse design. The methods enable a user, performing multidimensional analysis, to view, online, internal connections between attributes when going from one level to another in the hierarchical structures. Such as when comparing complex health related statistics for individuals across different age periods or for individuals versus their ancestors. The methods disclosed, facilitate OLAP for more complex data than current designs do.

Abstract: A semiconductor integrated circuit having: an internal main bus; first microprocessor and second microprocessor sharing the internal main bus; a first debug serial bus with one end thereof connected to said first microprocessor; a second debug serial bus with one end thereof connected to the second microprocessor; and a debugging module connected to the other ends of the first debug serial bus and second debug serial bus and transferring at least a debugging program and debugging data to the first microprocessor via said first debug serial bus and to the second microprocessor via the second debug serial bus.

Abstract: A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronisation and permit creation of networks of microcomputers with rapid communication between concurrent processes on the same or different microcomputers.

Abstract: A computer system splits a data space to partition data between processors or processes. The data space may be split into sub-regions which need not be orthogonal to the axes defined the data space's parameters, using a decision tree. The decision tree can have neural networks in each of its non-terminal nodes that are trained on, and are used to partition, training data. Each terminal, or leaf, node can have a hidden layer neural network trained on the training data that reaches the terminal node. The training of the non-terminal nodes' neural networks can be performed on one processor and the training of the leaf nodes' neural networks can be run on separate processors. Different target values can be used for the training of the networks of different non-terminal nodes. The non-terminal node networks may be hidden layer neural networks.

Abstract: A parallel computer of this invention includes a plurality of memory elements and a plurality of processing elements and each of the processing elements is connected to logically adjacent memory elements. For example, the processing elements which corresponds to a logical position (i, j) is connected to the memory elements which correspond to a plurality of logical positions (i, j), (i, j+1), (i+1, j) and (i+1, j+1). It is preferable if each of the memory elements can be accessed from the exterior. According to this invention, efficient memory access can be made and the parallel processing can be performed at high speed without increasing the hardware amount and making the control operation complicated. Further, the operation speed of the image processing can be enhanced by constructing an image memory by use of a plurality of memory elements and causing the processing element to effect the image processing in a distributed and cooperative manner.

Abstract: An internal bus system for DFPs and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity. The bus system can transmit data between a plurality of function blocks, where multiple data packets can be on the bus at the same time. The bus system automatically recognizes the correct connection for various types of data or data transmitters and sets it up.

Abstract: An array processor includes processing elements arranged in clusters which are, in turn, combined in a rectangular array. Each cluster is formed of processing elements which preferably communicate with the processing elements of at least two other clusters. Additionally each inter-cluster communication path is mutually exclusive, that is, each path carries either north and west, south and east, north and east, or south and west communications. Due to the mutual exclusivity of the data paths, communications between the processing elements of each cluster may be combined in a single inter-cluster path. That is, communications from a cluster which communicates to the north and east with another cluster may be combined in one path, thus eliminating half the wiring required for the path. Additionally, the length of the longest communication path is not directly determined by the overall dimension of the array, as it is in conventional torus arrays.

Abstract: A memory device which utilizes a plurality of memory modules coupled in parallel to a master I/O module through a bus. Each memory module has independent address and command decoders to enable independent operation. Thus each memory module is activated by commands on the bus only when a memory access operation is performed within the particular memory module. Each memory module has a programmable identification register which stores a communication address of the module. The communication address for each module can be changed during operation of the memory device by a command from the bus. The memory device includes redundant memory modules to replace defective memory modules. Replacement can be carried out through commands on the bus.

Abstract: The multi-processor system comprises a plurality of cell processors for performing data processing, a BCMC for broadcasting broadcast data including data used in data processing to the plurality of cell processors, each of the plurality of cell processors sorts out only data necessary for data processing that is performed by each cell processor from broadcast data broadcasted by BCMC to as to perform data processing. BCMC obtains results of data processing of all cell processors so that they can be supplied to all cell processors as broadcast data, thus making it possible to transmit and receive the results of data processing between the cell processors and perform high-speed data processing as an entire system.

Abstract: A processor is provided with a datapath and control logic to control the datapath to selectively effectuate execution of instructions of multiple ISA. In some embodiments, execution of the instructions of the different ISA are effectuated by selectively executing primitive operations (POP) of different ISA implementing POP collections. In some embodiments, the processor further includes at least one ISA selector accessible to the control logic to facilitate the control logic in controlling the datapath to selectively effectuate execution of the instructions of the different ISA. In some embodiments, the processor further includes an ISA library, storing and supplying, e.g. different collections of primitive operations implementing instructions of the different ISA, and logical to physical mappings of the different ISA.

Abstract: A processing system 2 is described including a processor unit 4 and a memory 6. Diagnostic hardware 10 within the processing system 2 includes a shadow PC register 12 that stores a shadow program counter value following the true program counter value held within a program counter register 8 of the processor unit 4. The diagnostic hardware 10 is responsive to a program counter request signal from an external diagnostic system 14 to transfer a program counter value into a scan chain 16 from where it can be returned to the diagnostic system 14. The operation of the processor unit 4 is independent of any of the diagnostic operations and so true real time operation of the system may be observed and de-bugged.

Abstract: A computer-implemented method and system for graphically displaying at least two edges extending between common points in a graphical structure. A particular implementation relates to the display of execution paths of a computer program component having multiple execution paths so as to allow proper differentiation between the execution paths. The computer program component is processed so as to derive a data structure containing nodes representing all basic blocks thereof, edges representing lines connecting the nodes, and execution paths traversed during operation of the computer program, component. The resulting data structure is displayed graphically in 3-D. In order to allow the execution paths to be distinguished when they pass along the same edge of the graph, different sections of the edge are color coded. This can be done by spatially separating the edges and coloring each edge uniquely; or by dividing each edge into different colored sections in respect of each execution path.

Abstract: The presently preferred embodiment of the invention provides a system in which a plurality of integrated circuits are connected in a multi-dimensional network configuration without requiring an LDT switch. In this configuration, each integrated circuit has more than two LDT Interfaces. For example, integrated circuits with four LDT interfaces are assembled into a two-dimensional mesh. Integrated circuits with four LDT interfaces can also be linked into a PLEX topology.

Abstract: General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based on complex conditions may be avoided and complex conditions can then be used for conditional execution. ACF generation and use can be specified by the programmer. By varying the number of flags affected, conditional operation parallelism can be widely varied, for example, from mono-processing to octal-processing in VLIW execution, and across an array of processing elements (PE)s. Multiple PEs can generate condition information at the same time with the programmer being able to specify a conditional execution in one processor based upon a condition generated in a different processor using the communications interface between the processing elements to transfer the conditions.

Abstract: Processing element to processing element switch connection control is described using a receive model that precludes communication hazards from occurring in a synchronous MIMD mode of operation. Such control allows different communication topologies and various processing effects such as an array transpose, hypercomplement or the like to be efficiently achieved utilizing architectures, such as the manifold array processing architecture. An encoded instruction method reduces the amount of state information and setup burden on the programmer taking advantage of the recognition that the majority of algorithms will use only a small fraction of all possible mux settings available. Thus, by means of transforming the PE identification based upon a communication path specified by a PE communication instruction an efficient switch control mechanism can be used.

Abstract: A single-instruction multiple-data (SIMD) array processor for processing multi-dimensional node meshes that are either elongated or not elongated in at least one coordinate direction. The SIMD array processor includes a plurality of processor arrays interconnected to form an N-dimensional array. Each processor array in the N-dimensional array is connected to 2N data I/O paths for communicating with 2N processor arrays in the N-dimensional array. Each processor array conceptually located at an interior point of the N-dimensional array is connected to 2N dimensionally adjacent processor arrays in the N-dimensional array. Each processor array conceptually located at one of at least one pair of dimensionally opposite boundaries of the N-dimensional array is connected to fewer than 2N dimensionally adjacent processor arrays and at least one processor array conceptually located at the dimensionally opposing boundary.

Abstract: A method for exchanging information within a mesh network that has an array of nodes defined by four quadrants. The method includes the initial step of exchanging information from a set of nodes in one quadrant to a set of nodes located in an adjacent quadrant. The exchange of information simultaneously occurs in both a vertical and horizontal direction within the array. Information is then exchanged between nodes within the same quadrant and subquadrants.

Abstract: An indirect VLIW (iVLIW) architecture is described which contains a minimum of two instruction memories. The first instruction memory (SIM) contains short-instruction-words (SIWs) of a fixed length. The second instruction memory (VIM), contains very-long-instruction-words (VLIWs) which allow execution of multiple instructions in parallel. Each SIW may be fetched and executed as an independent instruction by one of the available execution units. A special class of SIW is used to reference the VIM indirectly to either execute or load a specified VLIW instruction (called an “XV” instruction for “eXecute VLIW”, or LV for “Load VLIW”). In these cases, the SIW instruction specifies how the location of the VLIW is to be accessed. Other aspects of this approach relate to the application of data memory addressing techniques for execution or loading of VLIWs that parallel the addressing modes used for data memory accesses.

Abstract: A method/operator is disclosed that adjusts measurements during processing in a multidimensional data cube. The online “depth-of-field” operator disclosed varies the density of points in a representation of the multidimensional cube. The operator may be applied to any collection of dimensions and relations supported by the dimensions, using hierarchical structures to control the adjustments. It allows one to experiment online with the definition of relations during multidimensional possessing, thereby controlling the output of the synthesizing process. The operator may be used to equate attributes based on their hierarchical positions when processing measurements in a hypercube. Furthermore, it may be used to reveal hidden dependencies between variables when working with measurements with varying levels of granularity.

Abstract: The present invention provides an address resolution method for use in a multiprocessor system with distributed shared memory. The method allows users to change a memory configuration and a system configuration to increase system operation flexibility and to isolate errors. A cell controller indexes into an address resolution table using the high-order part of a processor-specified address. A write protection flag specifies whether to permit write access from other cells. An attempt to write-access a cell inhibited for write access causes a logical circuit to output an access exception signal.

Abstract: A computing system for effecting scientific and technical calculations comprises at least a group of processor modules (1-1 . . . 1-N), a switch (2), an auxiliary switch (3), a group of associative memory modules (4-1 . . . 4-N), a buffering block (5). The computing system provides information processing without any inter-processor exchange, hence, decreasing the time for program processing.

Abstract: An arbitrator provided to a processor element requests the utilization of a bus sends a bus request signal and a bus request value according to a priority level of the processor element to the bus, determines the priority of utilizing the bus in accordance with utilizing situation of the bus and the priority level of the processor element. Since a common bus arbitrating circuit connected to the bus watches the bus and determines a processor element to utilize the bus according to the utilizing situation of the bus and the priority level of the processor elements requesting the utilization of the bus, the bus arbitration can be performed with high speed, and an increase of communication speed between the processor elements through a single bus can be realized.

Abstract: An array processor includes processing elements arranged in clusters which are, in turn, combined in a rectangular array. Each cluster is formed of processing elements which preferably communicate with the processing elements of at least two other clusters. Additionally each inter-cluster communication path is mutually exclusive, that is, each path carries either north and west, south and east, north and east, or south and west communications. Due to the mutual exclusivity of the data paths, communications between the processing elements of each cluster may be combined in a single inter-cluster path. That is, communications from a cluster which communicates to the north and east with another cluster may be combined in one path, thus eliminating half the wiring required for the path. Additionally, the length of the longest communication path is not directly determined by the overall dimension of the array, as it is in conventional torus arrays.

Abstract: A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading).

Abstract: The present invention reduces the processing time required for alltoall communications in a parallel computer. When performing alltoall communications in a parallel computer, the number of transfer data units and the number of computers are used as parameters to select between a method where a temporary work buffer is allocated in the memory of each computer and non-contiguous data is exchanged between computers and a method where data is exchanged between computers without allocating temporary work buffers.

Abstract: A data processing system, circuit arrangement, integrated circuit device, program product, and method selectively prefetch a non-cached target memory address for a branch instruction when the target memory address is in a predetermined portion of a memory address space, e.g., within a predetermined number of cache lines from a branch instruction being processed. By prefetching the non-cached target memory addresses for this subclass of branch instructions, the delays associated with retrieving the target memory addresses from higher order memory are minimized. Moreover, by limiting such prefetching to only this subclass of branch instructions, the frequency of retrieval of unneeded data into the cache is often reduced.

Abstract: A processor capable of executing vector instructions includes at least an instruction sequencing unit and a vector processing unit that receives vector instructions to be executed from the instruction sequencing unit. The vector processing unit includes a plurality of multiply structures, each containing only a single multiply array, that each correspond to at least one element of a vector input operand. Utilizing the single multiply array, each of the plurality of multiply structures is capable of performing a multiplication operation on one element of a vector input operand and is also capable of performing a multiplication operation on multiple elements of a vector input operand concurrently. In an embodiment in which the maximum length of an element of a vector input operand is N bits, each of the plurality of multiply arrays can handle both N by N bit integer multiplication and M by M bit integer multiplication, where N is a non-unitary integer multiple of M.

Abstract: A processor has an improved architecture for multiple-thread operation on the basis of a highly parallel structure including multiple independent parallel execution paths for executing in parallel across threads and a multiple-instruction parallel pathway within a thread. The multiple independent parallel execution paths include functional units that execute an instruction set including special data-handling instructions that are advantageous in a multiple-thread environment.

Abstract: The apparatus has a multiplicity of control modules which are assigned to a multiplicity of processing modules for driving purposes. These separate control modules are driven by a superordinate controller and are synchronized by a common synchronization unit on the basis of, by way of example, handshake lines and semaphores. The effect achieved by such an apparatus is that the transmission bandwidth between an external instruction memory and the large-scale integrated system can be reduced, and the total power loss can be lowered by intermittently disconnecting processing modules which are currently not needed. Furthermore, such an architecture supports the separate development of control programs for the individual control modules.

Abstract: A method for verifying all intermediate results of a set of architected registers at the end of an instruction stream, even if the final values do not depend on the values of all intermediate results, using a single MISR (Multiple Input Shift Register) to generate a signature of all updates to multiple architected registers. Single instructions update multiple registers across multiple machine cycles, and an accumulation register allows order independence of partial results. A register update consists of the data to be written, an address identifying which register is to be updated, and controls to identify if this is the last register update that will be done by the current instruction. For each cycle, logic evaluates the update controls to select what will be gated into the accumulation register and also sets MISR control latches to tell how to update the MISR the next cycle. The latched MISR controls select whether the MISR will clear, hold, or evaluate.

Abstract: A parallel processor apparatus capable of reducing the power consumption when converting serial data to parallel data and, at the same time, capable of improving an operating speed, wherein a data input register for converting serial data to parallel data is divided and data inputting means of a plurality of blocks are constituted and wherein detection circuits for detecting the time of input and the time of output of the pointer data in the data inputting means are provided and switch circuits for connecting the related data inputting means and a serial data input line only for a period from the time of input to the time of output of the pointer data detected by the detection circuit are provided.

Abstract: A method and apparatus for power mode transition in a multi-thread processor. A first indication is issued, including a first identifier associated with a first logical processor in a processor, that the first logical processor has entered a power mode. A second indication is issued, including a second identifier associated with a second logical processor in the processor, that the second logical processor has entered the power mode. The indications may be, for example, stop grant acknowledge special bus cycles indicating that the logical processors have entered a stop grant mode. The processor may be transitioned to a sleep mode when both the first and second indications have been issued.

Abstract: A system for monitoring issuance of interrupt and transaction commands without involving central processor units of computer systems. The system employs a fabric controller to manage transaction commands among and host devices. The system employs an interrupt controller to manage interrupt commands issued by devices. The system further employs a concurrent bridge to support communication between the controllers and at least one host device. With this system, congestion due to control and data traffic is minimized and a more efficient operation of central processor units is achieved.

Abstract: A user-configurable ultra-scalar multiprocessor has a predetermined plurality of distributed configurable signal processors (DCSPs) (1) which are computational clusters that each have at least two sub microprocessors (SMs) (2) and one packet bus controller (PBC) (3) that are a unit group. The DCSPs, the SM and the PBC are connected through local network buses (6). The PBC has communication buses (7) that connect the PBC with each of the SM. The communication buses of the PBC that connect the PBC with each SM have serial chains of one hardwired connection (4) and one programmably switchable connector (5). Each communication bus between the SMs is at least one hardwired connection and two programmably switchable connectors.

Abstract: A programmable interconnect system having a plurality of PICs connected via a plurality of buses where each bus may have two or more branches connecting the PICs is disclosed. Generally speaking, for a system with N PICs, there can be N−1 different type of buses having 2 to N corresponding branches to the N PICs. For example, for a four PIC programmable interconnect system, there can be three types of buses connecting the PICs, a two-branch bus, a three-branch bus, and a four-branch bus. Note that the term “bus” refers to one or more signal paths connecting the PICs. For each type of buses, there can be several layouts.