Abstract: Described are techniques used in dynamically modifying RDF groups. A system call is issued by a host computer system to execute a remote system call on a first data storage system to create, remove, or modify an RDF group between the first data storage system and another data storage system that is remotely connected to the first data storage system in an RDF switched environment. As part of executing the remote system call, data is pushed from the first to the second data storage systems without having an established link between the data storage systems. Each data storage system performs processing to make the necessary modifications in all directors in accordance with the dynamic RDF group. A status indicating success or failure of the remote system call is returned to the host computer system.

Abstract: A customization program for use in customizing a baseboard management controller used for monitoring operation of various computer system components is disclosed. A user interacts with the customization program to customize the baseboard management controller based on a configuration of components specified for the baseboard of the computer system. The customization program provides a user interface having a repository of icons and a design page. The icons represent various components that may be connected, either directly or indirectly, to the baseboard. The design page is used for constructing a model representing the specified configuration of components. As a user drags icons onto the design page, the model is updated to reflect selection of the components corresponding to these icons. Further, the customization program creates a configuration file that identifies and describes each of the selected components.

Abstract: An expanded arithmetic and logic unit (EALU) with special extra functions is integrated into a configurable unit for performing data processing operations. The EALU is configured by a function register, which greatly reduces the volume of data required for configuration. The cell can be cascaded freely over a bus system, the EALU being decoupled from the bus system over input and output registers. The output registers are connected to the input of the EALU to permit serial operations. A bus control unit is responsible for the connection to the bus, which it connects according to the bus register. The unit is designed so that distribution of data to multiple receivers (broadcasting) is possible. A synchronization circuit controls the data exchange between multiple cells over the bus system. The EALU, the synchronization circuit, the bus control unit, and registers are designed so that a cell can be reconfigured on site independently of the cells surrounding it.

Abstract: The present invention provides a method and system of interconnecting L processors of a parallel computer to facilitate torus partitioning, (a) where each of the processors includes a processing unit and a switch, (b) where the switch includes a first external port, a second external port, a third external port, a fourth external port, a first internal port, and a second internal port, (c) where the L processors comprise R non-overlapping partitions, (d) where each of the partitions comprises the processing unit of at least one of the processors, and (e) where L is an integer ?2 and R is an integer ?1. In an exemplary embodiment, the method and system include connecting the L switches of the L processors among the external ports of the L switches in an extended torus architecture and setting the connected L switches thereby interconnecting each of the partitions as a torus.

Abstract: A self-reparable semiconductor includes multiple functional units that perform the same function and that include sub-functional units. The semiconductor includes one or more full or partial spare functional units that are integrated into the semiconductor. If a defect in a sub-functional unit is detected, then that sub-functional unit is switched out and replaced with a sub-functional unit in the full or partial spare functional unit. The reconfiguration is realized with switching devices that are associated with the sub-functional units. Defective functional or sub-functional units can be detected after assembly, during power up, periodically during operation, and/or manually.

Abstract: A novel personal electronic device includes a first (embedded) and second (non-embedded) processors including associated operating systems and functions. In one aspect, the first processor performs relatively limited functions, while the second processor performs relatively broader functions under control of the first processor. Often the second processor requires more power than the first processor and is selectively operated by the first processor to minimize overall power consumption. Protocols for functions to be performed by the second processor may be provided directly to the second processor and processed by the second processor. In another aspect, a display controller is designed to interface with both processors. In another aspect, the operating systems work with one another. In another aspect, the first processor employs a thermal control program. Advantages of the invention include a broad array of functions performed by a relatively small personal electronics device.

Abstract: A system that may optionally be partitioned into multiple domains is disclosed. Each domain is capable of independently powering on, executing a firmware program, and loading an operating system, including a legacy operating system, as well as running an application program that is distinct from programs running on another domain. Interrupts, including boot interrupts, reset handlers, and inter-chassis communications are initialized differently, depending on whether the system is to be partitioned or not. The cost of redundant hardware and/or firmware is substantially avoided, yet the system fully supports multiple domains.

Abstract: The present invention is directed to a system and method for managing allocation of a computer resource to at least one partition of a plurality of partitions of a multiple partition computer system, the system comprising: a plurality of work load managers, with one work load manager associated with each partition of the plurality of partitions, wherein each work load manager determines a resource request value for the computer resource based on at least one priority assigned to its partition associated with the computer resource; and a partition load manager that is operative to form an allocation value for each respective partition based on a respective resource request value; wherein the system apportions the computer resource among the plurality of partitions based on the allocation values.

Abstract: An integrated active memory device includes an array of processing elements coupled to a dynamic random access memory device and to a component supplying instructions to the processing elements. The processing elements are logically arranged in a plurality of logical rows and logical columns. The array is logically folded to minimize the length of the longest path between processing elements by physically interleaving the processing elements so that the processing elements in different logical rows a physically interleaved with each other and the processing elements in different logical columns a physically interleaved with each other.

Abstract: An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). The packet processors (307, 313, 303) include a receive processor (421), a transmit processor (427) and a risc core processor (401), all of which are programmable. The receive processor (421) and the core processor (401) cooperate to receive and route packets being received and the core processor (401) and the transmit processor (427) cooperate to transmit packets. Routing is done by using information from the table look up engine (301) to determine a queue (215) in the queue management engine (305) which is to receive a descriptor (217) describing the received packet's payload.

Abstract: A single chip active memory includes a plurality of memory stripes, each coupled to a full word interface and one of a plurality of processing element (PE) sub-arrays. The large number of couplings between a PE sub-array and its associated memory stripe are managed by placing the PE sub-arrays so that their data paths run at right angle to the data paths of the plurality of memory stripes. The data lines exiting the memory stripes are run across the PE sub-arrays on one metal layer. At the appropriate locations, the data lines are coupled to another orthogonally oriented metal layer to complete the coupling between the memory stripe and its associated PE sub-array. The plurality of PE sub-arrays are mapped to form a large logical array, in which each PE is coupled to four other PEs. Physically distant PEs are coupled using current mode differential logical couplings an drivers to insure good signal integrity at high operational speeds. Each PE contains a small DRAM register array.

Abstract: The multi-processor system comprises a plurality of cell processors for performing data processing, a BCMC for broadcasting broadcast data including data used in data processing to the plurality of cell processors, each of the plurality of cell processors sorts out only data necessary for data processing that is performed by each cell processor from broadcast data broadcasted by BCMC to as to perform data processing. BCMC obtains results of data processing of all cell processors so that they can be supplied to all cell processors as broadcast data, thus making it possible to transmit and receive the results of data processing between the cell processors and perform high-speed data processing as an entire system.

Abstract: A data mining decision tree system that uncovers patterns, associations, anomalies, and other statistically significant structures in data by reading and displaying data files, extracting relevant features for each of the objects, and using a method of recognizing patterns among the objects based upon object features through a decision tree that reads the data, sorts the data if necessary, determines the best manner to split the data into subsets according to some criterion, and splits the data.

Abstract: A center focussed SIMD array system including an SIMD array including a plurality of processing elements arranged in a number of columns and rows and having two mutually perpendicular axes of symmetry defining four quadrants; and a sequencer circuit for moving the data in each element to the next adjacent element towards one axis of symmetry until the data is in the elements along the one axis of symmetry and then moving the data in the elements along the the one axis of symmetry to the next adjacent element towards the other axis of symmetry until the data is at the four central elements at the origin of the axes of symmetry.

Abstract: A method and system are disclosed for pre-loading a hard architected state of a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the processor, a hard architected state, which has been pre-stored in the processor, of a next process is loaded into architected storage locations in the processor. The next process to be executed, and thus its corresponding hard architected state that is pre-stored in the processor, are determined based on priorities assigned to the waiting processes.

Abstract: A system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system is provided. Each processing element node includes at least one processor and memory. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in a cluster. A first set of routers in the scalable interconnect network route messages between the plurality of processing element nodes. One or more metarouters in the scalable interconnect network route messages between the first set of routers so that each one of the routers in a first cluster is connected to all other clusters through one or more metarouters.

Abstract: A processor allocation mechanism for a logically partitionable computer system allows an administrator to specify processing capability allocable to each partition as an equivalent number of processors, where the processing capability may be specified as a non-integer value. This processing capability value is unaffected by changes to the processing capability values of other partitions. The administrator may designate multiple sets of processors, assigning each physical processor of the system to a respective processor set. Each logical partition is constrained to execute in an assigned processor set, which may be shared by more than one partition. Preferably, the administrator may designate a logical partition as either capped, meaning that a partition can not use excess idle capacity of the processors, or uncapped, meaning that it can.

Abstract: A data processing apparatus of the present invention includes a plurality of nodes each of which includes at least one processor and which is divided to a plurality groups, a bus to which the nodes are connected, and memory elements provided in the nodes, respectively. Shared memory areas are provided in the groups, respectively, and the nodes access to the shared memory areas. Another data processing apparatus of the present invention includes a plurality of nodes each of which includes at least one processor, a bus to which the nodes are connected, and memory elements provided in the nodes, respectively. The apparatus has a first element which sets the nodes to clusters.

Abstract: A method of determining whether datapaths executing in a computer program should execute conditional processing block includes determining whether processor enable (PE) states of all of the datapaths are disabled, and branching around the conditional processing if the PE states of all of the datapaths are disabled. Branching is not performed, even if the PE states of all of the datapaths are disabled, if the program is determined to be deterministic. That determination is made by evaluating the state of a deterministic bit. Instructions are also provided for carrying out the determining and branching operations. The instructions may also be combined with operations that maintain the PE states during conditional processing.

Abstract: Described are techniques used in dynamically modifying RDF groups. A system call is issued by a host computer system to execute a remote system call on a first data storage system to create, remove, or modify an RDF group between the first data storage system and another data storage system that is remotely connected to the first data storage system in an RDF switched environment. As part of executing the remote system call, data is pushed from the first to the second data storage systems without having an established link between the data storage systems. Each data storage system performs processing to make the necessary modifications in all directors in accordance with the dynamic RDF group. A status indicating success or failure of the remote system call is returned to the host computer system.

Abstract: Method and apparatus for sending data from one partition to a second partition within a logically partitioned computer. In a data processing system having multiple logical partitions, a send queue is established in the first logical partition, and a receive queue is established in the second logical partition. The send queue is registered in the send queue in a lookup table available to all of the logical partitions. The send queue is registered using as a key the logical partition identification of the first logical partition and the subchannel number (LPAR-ID.SUBCHANNEL#) of the subchannel assigned to the partition. The receive queue is registered in the lookup table using as a key, the internet protocol address of the receive queue in the second partition. A send instruction from the first logical partition is executed which interrogates the lookup table using the LPAR-ID.

Abstract: A method of implementing a scaleable architecture for a communications system is disclosed, based on minimizing a total gate count for the communications system to reduce cost, complexity, etc. The method considers the requirements of particular communications transmission process that is dividable into individual transmission tasks. A computational complexity for each of said N individual transmission tasks respectively, said computational complexity being based on a number of instructions per second (MIPs) required by a computational circuit to perform each of said N individual transmission tasks; a number of gates and/or transistors required to implement each of individual transmission task using a hardware based or software based computing circuit, etc. After determining an effective number of MIPs acheivable by such circuits, the N tasks are allocated in a gate efficient manner for a final design architecture, or for a working implementation in the field.

Abstract: The present invention is capable of placing or loading input data into a 2D or 3D array of processing elements interconnected in a variety of ways, and moving the data around by using a combination of shifts, e.g. north, south, east, west, which can be combined in any desired manner. The exact type and combination of shifts depends upon the particular data manipulation desired. As the sifting proceeds, each processing element is presented with a plurality of different array values. Each processing element can conditionally load any of the values it sees into the output result. The timing of the loading is achieved by monitoring a local counter. In a preferred embodiment, when the value in the local counter is non-positive, the current array value is selected as the final output for the output result. In general, each local counter is initialized to a different positive value and, at certain points in the shifting process, the counter is decremented.

Abstract: An improved logically partitioned data processing system is provided. In one embodiment, the data processing system includes a plurality of hardware devices, including processors, and a plurality of operating systems. Each of the plurality of operating systems executes within a separate partition within the logically partitioned data processing system. A firmware component provides each operating system with a virtualized copy of the hardware devices, thus maintaining separation between each of the logical partitions. The firmware component is implemented as 64-bits, thus allowing each of the processors to execute in 64-bit mode and eliminating the need for virtual address translation from a 32-bit virtual address to a 64-bit physical address.

Abstract: An integrated active memory device includes an array of processing elements coupled to a dynamic random access memory device and to a component supplying instructions to the processing elements. The processing elements are logically arranged in a plurality of logical rows and logical columns. The array is logically folded to minimize the length of the longest path between processing elements by physically interleaving the processing elements so that the processing elements in different logical rows a physically interleaved with each other and the processing elements in different logical columns a physically interleaved with each other.

Abstract: Partitioning a node of a multi-node system into more than one partition is disclosed. First resources of the node are physically partitioned into more than one partition. The first resources physically partitioned to each partition are directly inaccessible by other partitions of the node. Second resources of the node are then internally logically partitioned into the more than one partition. Each second resource internally separates transactions of one partition from transactions of other partitions. Furthermore, the node can be dynamically repartitioned into other partitions, such as a single partition, without having to take the multi-node system down. Operating system (OS) instances of the partitions may have assumptions provided to allow for dynamic partitioning, such as quiescing the processors and/or the input/output components being reconfigured, purging remote cache entries across the entire OS, etc.

Abstract: A method of controlling the enabling of processor datapaths in a SIMD processor during a loop processing operation is described. The information used by the method includes an allocation between the data items and a memory, a size of the array, and a number of remaining parallel passes of the datapaths in the loop processing operation. A computer instruction is also provided, which includes a loop handling instruction that specifies the enabling of one of a plurality of processor datapaths during processing an array of data items. The instruction includes a count field that specifies the number of remaining parallel loop passes to process the array and a count field that specifies the number of serial loop passes to process the array. Different instructions can be used to handle different allocations of passes to parallel datapaths. The instruction also uses information about the total number of datapaths.

Abstract: In an array-type processor in which a multiplicity of processor elements, which each execute data processing in accordance with instruction codes in which data are individually set, are arranged in rows and columns, and in which state control units cause successive transitions of the operating states of this multiplicity of processor elements for each operating cycle by means of contexts that are make up by instruction codes, a plurality of element areas are respectively connected to an equal number of state control units, and state control units that correspond to a prescribed number of operating states that are set to one context temporarily halt the operation of element areas to which the state control unit is connected during operating cycle in which operating states do not occur.

Abstract: According to the present invention, when an interrupt occurs in a computer system running an operating system, control takes a separate code path in the operating system, depending on whether the computer system is in non-partitioned mode or partitioned mode, before converging to a common mode-independent interrupt handler that services the interrupt. Along each separate code path, hardware state of the computer system which is relevant to the processing of the interrupt is changed to a consistent hardware state so that the common mode-independent interrupt handler can run properly in both modes.

Abstract: A highly parallel data processing system includes an array of n processing elements (PEs) and a controller sequence processor (SP) wherein at least one PE is combined with the controller SP to create a Dynamic Merged Processor (DP) which supports two modes of operation. In its first mode of operation, the DP acts as one of the PEs in the array and participates in the execution of single-instruction-multiple-data (SIMD) instructions. In the second mode of operation, the DP acts as the controlling element for the array of PEs and executes non-array instructions. To support these two modes of operation, the DP includes a plurality of execution units and two general-purpose register files. The execution units are “shared” in that they can execute instructions in either mode of operation. With very long instruction word (VLIW) capability, both modes of operation can be in effect on a cycle by cycle basis for every VLIW executed.

Abstract: A single chip active memory includes a plurality of memory stripes, each coupled to a full word interface and one of a plurality of processing element (PE) sub-arrays. The large number of couplings between a PE sub-array and its associated memory stripe are managed by placing the PE sub-arrays so that their data paths run at right angle to the data paths of the plurality of memory stripes. The data lines exiting the memory stripes are run across the PE sub-arrays on one metal layer. At the appropriate locations, the data lines are coupled to another orthogonally oriented metal layer to complete the coupling between the memory stripe and its associated PE sub-array. The plurality of PE sub-arrays are mapped to form a large logical array, in which each PE is coupled to four other PEs. Physically distant PEs are coupled using current mode differential logical couplings an drivers to insure good signal integrity at high operational speeds. Each PE contains a small DRAM register array.

Abstract: A parallel processor and an image processing system incorporating such processor are disclosed. Control signals in the parallel processor are generated by an instruction sequence control unit, and divided into two: global control signals supplied to a local signal generator of arbitrary selected processor element group; and local control signals buffered by the local control signal generator and then supplied exclusively to the processor elements included in arbitrary selected processor element group. This construction of the processor alleviates deterioration in device characteristics and undesirable increase in driving power requirements.

Abstract: A virtual parallel computer is created within a programming environment comprising both shared memory and distributed memory architectures. At run time, the virtual architecture is mapped to a physical hardware architecture. In this manner, a massively parallel computing program may be developed and tested on a first architecture and run on a second architecture without reprogramming.

Abstract: The present invention provides a method for sharing I/O facilities among logical partitions. A remote translation control entry table is created on a hosted partition appearing to own a virtual copy of the I/O facilities to be shared. The remote translation control entry table on the hosted partition is loaded with data from a hypervisor in response to requests made by the OS running in the hosted partition. The hypervisor, in response to requests from the OS running in the hosting partition, copies the data from the remote translation control entry into a standard translation control entry table on the hosting partition owning the physical I/O facilities that target the I/O page buffers of the hosted partition to perform the desired I/O operation. The I/O page buffers of the hosted partition are accessed by the hosting partition's I/O facilities using the data stored in the standard translation control entry table.

Abstract: A method and system for the parallel implementation of protocol engines based on memory partitioning. The method comprises the steps of partitioning a shared memory space into multiple mon-overlapping regions; and for each of the regions, using a respective one protocol engine to handle references to the region, independently of the other protocol engines. Preferably, the memory is partitioned into the non-overlapping regions either by using address interleaving or by using address range registers to identify address ranges for said regions. Also, preferably the protocol engines operate independent of each other and handle accesses to the memory regions in parallel.

Abstract: An apparatus and method for monitoring the state of a computer system running multiple operating systems shared by a partition manager is provided. A dedicated service processor monitors the individual run state condition of a plurality of processors running a plurality of operating systems. The service processor executes a routine to poll a memory location in each processor in the system to determine if the processor has entered an error loop with interrupts disabled. If any one of the plurality of processors are in an error loop, the service processor executes a routine to send a non-maskable interrupt to the looped processor so that the partition manager may regain control of the processor.

Abstract: A partitioner for creating logical partitions allows a user to specify maximum interactive performance in one partition independently of maximum interactive performance of other partitions to arrive at logical partitions that may be much different than the maximum overall interactive performance percentage of the computer system itself. First, the maximum interactive performance for a computer system is specified, and resources are allocated accordingly. Next, logical partitions may be created, which initially reflect the maximum interactive performance for the computer system as a whole. Finally, the maximum interactive performance can be specified for a partition independently of the interactive performance in other partitions. In this manner a computer system that is configured as a server system with low interactive and high batch performance can have two different partitions, one that has very low interactive performance and the other that balances interactive and batch processing.

Abstract: According to a first aspect of the present invention, a data processing system is provided that includes a communication network to which multiple devices are coupled. A first of the multiple devices includes a number of requestors (or queues), which are each permanently assigned a respective one of a number of unique tags. In response to a communication request by a requestor within the first device, a tag assigned to the requestor is transmitted on the communication network in conjunction with the requested communication transaction. According to a second aspect of the present invention, a data processing system includes a cache having a cache directory. A status indication indicative of the status of at least one of a plurality of data entries in the cache is stored in the cache directory. In response to receipt of a cache operation request, a determination is made whether to update the status indication.

Abstract: A method, system, and apparatus for isolating fatal data fetch errors to a single partition within a logically partitioned data processing system. In one embodiment, the logically partitioned data processing system includes a plurality of operating systems and a plurality of processors is provided. Each of the operating systems is assigned to a separate one of a plurality of logical partitions. Each of the processors is assigned to one of the plurality of logical partitions. The logically partitioned data processing system also includes a hypervisor for creating and maintaining separation of the plurality of logical partitions. The hypervisor contains services and functions accessed by each of the logical partitions and, to prevent fatal data fetch errors in one partition from effecting other partitions within the logically partitioned data processing system, the hypervisor includes a plurality of data structure areas.

Abstract: A method, system, and apparatus for recovering form an instruction fetch error is provided. In one embodiment, a data processing system maintains a primary copy and an alternate copy of a set of instructions for a software component. The instructions for performing the processes of the software component are fetched from the primary copy for execution by a processor. A pair of pointers is maintained in each copy identifying the beginning of each copy. Responsive to a determination that an instruction fetch error has been received, a corresponding current instruction in the alternate copy is determined and the software component is restarted by fetching and executing instructions from the alternate copy starting with the corresponding current instruction. The corresponding current instruction is determined by subtracting the beginning address of the copy with the error from the address of the current instruction, then adding the beginning address of the alternate copy.

Abstract: Irregularities are provided in at least one dimension of a torus or mesh network for lower average path length and lower maximum channel load while increasing tolerance for omitted end-around connections. In preferred embodiments, all nodes supported on each backplane are connected in a single cycle which includes nodes on opposite sides of lower dimension tori. The cycles in adjacent backplanes hop different numbers of nodes.

Abstract: Methods, signals, devices, and systems are provided for matching tasks with processing units. A region within a multi-faceted task space is allocated to a processing unit. A point in the multi-faceted task space is assigned to a task. The task is then associated with the processing unit if the region allocated to the processing unit is close to the point assigned to the task. The region allocated to a processing unit may be changed. If no assigned point for a task is sufficiently close to any allocated processing unit region, the task is suspended. Overlapping regions may be assigned to different processing units. In some implementations, the union of the allocated regions covers the task space, while in others it does not. Regions may also be allocated to wait conditions and one or more dimensions of a region may be allocated to conventional processor allocators.

Abstract: In a computer system having a logical-partitioned server, each partition of the server is provided with its own separate lock and access corridor, in addition to a global lock. When the locking of a partition lock is followed by the locking of the global lock, the system is serialized. The partition locks are controlled by system firmware on behalf of an OS isolating each partition; however, the global lock is controlled by the system firmware to be unlocked independent of the lock/unlock status of the partition locks. In this manner, the ability or inability of an OS that issued a machine check interrupt to unlock its partition lock after the machine check analysis is complete is irrelevant; once the machine check analysis is complete, the system firmware unlocks the global lock, giving other partitions access to shared system resources to run their own machine checks.

Abstract: An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. A B16×16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The B16×16 tile is a nesting of a B2×2 tile that includes a two by two array of four B1 blocks. The routing resources in the middle level of hierarchy are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. The expressway routing channels M1, M2, and M3 are segmented, and between each of the segments in the expressway routing channels M1, M2, and M3 are disposed extensions that can extend the expressway routing channel M1, M2, or M3 an identical distance along the same direction. The expressway routing channels M1, M2, and M3 run both vertically through every column and horizontally through every row of B2×2 tiles.

Abstract: Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected together. The single physical machine with multiple physical processors and resources is subdivided by software into multiple partitions, each with the ability to run a distinct copy, or instance, of an operating system. At different times, different operating system instances may be loaded on a given partition. Resources, such as CPUs and memory, can be dynamically assigned to different partitions and used by instances of operating systems running within the machine by modifying the configuration. The partitions themselves can also be changed without rebooting the system by modifying the configuration tree. Each instance keeps track of the CPUs in the system and their respective operational statuses relative to the instance, such as compatibility with the instance, control by the instance, and availability to the instance for SMP processing.

Abstract: Methods and systems consistent with the present invention provide a family of networks ranging from 2 nodes to 16 nodes that can be partitioned in an unconstrained manner. That is, where the number of nodes in one of these networks is N, subnetwork can contain any number of nodes from 1 to N−1 as long as the total number of nodes in both subnetworks equals N. Furthermore, each subnetwork can be partitioned repeatedly until reaching the atomic level (i.e., when the subnetwork contains a single node). In accordance with methods and systems consistent with the present invention, when a network is partitioned, each subnetwork has various desirable properties. For example, the maximum path length between any two nodes in each subnetwork nodes is 3, and each to subnetwork has a set of deadlock-free routings.

Abstract: A procedure and a processor arrangement for parallel data processing in which data are read out from a data memory and are conveyed via a communications unit to processing units for parallel processing. The data are divided into data groups with several elements and are stored in a group memory under a common address. To each data group, a processing unit is allocated, in that at least one element of a data group can be directly linked to the allocated processing unit, directly bypassing the communications unit. In a parallel fashion, a data group is read out from the data memory and is distributed over one or several processing units and is processed in a parallel fashion in the latter.

Abstract: A masterless approach binds multiprocessor building blocks to partitions of a computer system using identifiers and indicators. A number of building blocks communicate among each other to determine a partition to which each building block is to be partitioned. For each unique partition to which one or more of the building blocks is to be partitioned, the building blocks communicate among each other to determine building block uniqueness, and then each of the building blocks joins the partition. The building blocks share with one another their logical port identifiers, which uniquely identify the building block within a partition. A commit indicator of each building block indicates that the building block has committed itself to the partition and that its identifiers cannot be changed.

Abstract: Central processing unit (CPU) resources are managed within a computing environment. When the allocation of CPU resources to a partition of the computing environment is to be adjusted, the allocation is adjusted dynamically. This dynamic adjustment is across at least two partitions of the computing environment. The adjusting includes modifying processor weights associated with the partitions.

Abstract: The invention relates to a method and an apparatus for controlling a digital signal processor having a number of arithmetic units (1a, 1b) which process a program (8). A control unit (5) is provided for independent control of the individual arithmetic units (1a, 1b), which control unit (5) reads and evaluates the flags (9a, 9b) which are specific to the arithmetic units, and deactivates those arithmetic units (1a, 1b) whose associated flag is not set, so that a subroutine is carried out only by those arithmetic units (1a, 1b) whose flags are set.