Abstract: A high-speed rule processing apparatus is disclosed that may be used to implement a wide variety of rule processing tasks such as network address translation, firewall protection, quality of service, IP routing, and/or load balancing. The high-speed rule processor uses an array of compare engines that operate in parallel. Each compare engine includes memory for storing instructions and operands, an arithmetic-logic for performing comparisons, and control circuitry for interpreting the instructions and operands. The results from the array of compare engines is prioritized using a priority encoding system.

Abstract: An SIMD array processor having a scalable and flexible architecture. The SIMD array architecture includes an array of processing elements, a plurality of processor controllers, and at least one other computer system. A system area network interconnects at least one user computer with the processor controllers and the computer system; and, a storage area network interconnects at least one storage device with the processor controllers and the computer system. The SIMD array architecture is adapted to allow different user computers to use different portions of the array of processing elements and/or different processor controllers and computer systems simultaneously. The array of processing elements has a hierarchical structure comprising backplanes, PCB's, ASIC's, and arrays of processing elements. The SIMD array architecture can be scaled by increasing the quantity of backplanes, PCB's, ASIC's, and/or by increasing the size of the arrays of processing elements.

Abstract: A data processing apparatus includes a SIMD (Single Instruction Multiple Data) array (10) of processing elements. The processing elements are operably divided into a plurality of processing blocks, the processing blocks being operable to process respective groups of data items.

Abstract: A manifold array topology includes processing elements, nodes, memories or the like arranged in clusters. Clusters are connected by cluster switch arrangements which advantageously allow changes of organization without physical rearrangement of processing elements. A significant reduction in the typical number of interconnections for preexisting arrays is also achieved. Fast, efficient and cost effective processing and communication result with the added benefit of ready scalability.

Abstract: A data processing unit comprises an input section 1 for inputting first data from the outside, an operation section 2 for operating the first data inputted therefrom, to generate second data, a memory section 3 for storing the second data, an output section 4 for outputting the second data stored in the memory section to the outside, and a control section 5 for controlling the memory section to enable storing and outputting of the second data.

Abstract: The circuit converts data and has at least one programmable mini-processor, a program and data memory as well as a bus controller. For increasing the data throughput, the electronic circuit is integrated on an application-specific integrated circuit.

Abstract: An internal bus system for DFPs and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity. The bus system can transmit data between a plurality of function blocks, where multiple data packets can be on the bus at the same time. The bus system automatically recognizes the correct connection for various types of data or data transmitters and sets it up.

Abstract: General base hypercube transformations using general base perfect shuffles and Kronecker matrix products are applied to the problem of parallel, to massively parallel processing of sparse matrices. The approach is illustrated by applying the hypercube transformations to general base factorizations of generalized spectral analysis transformation matrices. Hypercube transformations lead to optimal scheduling with contention-free memory allocation at any level of parallelism and up to massive parallelism. The approach is illustrated by applying the generalized-parallelism hypercube transformations to factorizations of generalized spectral analysis transformation matrices, and in particular to Generalized Walsh-Chrestenson transformation matrices of which the Discrete Fourier transform and hence the Fast Fourier transform are but a special case.

Abstract: A memory device which utilizes a plurality of memory modules coupled in parallel to a master I/O module through a bus. Each memory module has independent address and command decoders to enable independent operation. Thus each memory module is activated by commands on the bus only when a memory access operation is performed within the particular memory module. Each memory module has a programmable identification register which stores a communication address of the module. The communication address for each module can be changed during operation of the memory device by a command from the bus. The memory device includes redundant memory modules to replace defective memory modules. Replacement can be carried out through commands on the bus.

Abstract: Methods, systems, and articles of manufacture consistent with the present invention provide a development tool that enables computer programmers to design and develop a data flow program for execution in a multiprocessor computer system. The tool displays an interface that enables the programmer to define a region divided into multiple blocks, wherein each block is formed of a set of values associated with a function, and to define sets of the blocks, each block in a set having a state reflected by a designated portion of the program that when executed transforms the values forming the block based on the function. The interface also records any dependencies among the blocks, each dependency indicating a relationship between two blocks and requiring the portion of the program associated with a first block of the relationship to be executed before the portion of the program associated with a second block of the relationship.

Abstract: A method for supporting software partition and dynamic reconfiguration within a non-uniform memory access (NUMA) computer system is disclosed. A NUMA computer system includes multiple nodes coupled to an interconnect. Each of the nodes includes a NUMA bridge, a local system memory, and at least one processor having at least a local cache memory. Multiple groups of software partitions are formed within the NUMA computer system, and each of the software partitions is formed by a subset of the nodes. A destination map table is provided in a NUMA bridge of each of the nodes for keeping track of the nodes within a software partition. A command is forwarded to only the nodes within a software partition.

Abstract: A system for partitioning and allocating individual PCI slots within a Primary Host Bridge (PHB) in a partitioned computer system is provided. An innovative PHB system is included which allows a PCI slot to be dynamically assigned to one or more partitions at a given time, allowing for more efficient allocation of system resources.

Abstract: A parallel processor and an image processing system incorporating such processor are disclosed. Control signals in the parallel processor are generated by an instruction sequence control unit, and divided into two: global control signals supplied to a local signal generator of arbitrary selected processor element group; and local control signals buffered by the local control signal generator and then supplied exclusively to the processor elements included in arbitrary selected processor element group. This construction of the processor alleviates deterioration in device characteristics and undesirable increase in driving power requirements.

Abstract: The present invention, generally speaking, provides a reconfigurable computing solution that offers the flexibility of software development and the performance of dedicated hardware solutions. A reconfigurable processor chip includes a standard processor, blocks of reconfigurable logic (1101, 1103), and interfaces (319a, 319b, 311) between these elements. The chip allows application code to be recompiled into a combination of software and reloadable hardware blocks using corresponding software tools. A mixture of arithmetic cells and logic cells allows for higher effective utilization of silicon than a standard interconnect. More efficient use of configuration stack memory results, since different sections of converted code require different portions of ALU functions and bus interconnect. Many types of interfaces with the embedded processor are provided, allowing for fast interface between standard processor code and configurable “hard-wired” functions.

Abstract: A matrix processor comprises a system with a variable number of buses, each bus having a variable number of processing elements which may operate in parallel. Each bus accesses a port into a memory crossbar and a multiport memory system also accesses crossbar ports. Efficient sharing of bus accesses by processors and synchronization of processors on each bus is accomplished via registers located on the buses, which may be read and written by processors. Interbus synchronization is also accomplished via register accesses. The matrix processor may be configured as a coprocessor or as a stand alone device. A method of synchronizing the processors and buses, performed by at least one processor on at least one bus, includes reading a barrier state of the processors, synchronizing the processing elements on a each bus, reading the barrier state of the buses, and synchronizing each bus.

Abstract: A method and apparatus for providing for serially transmitting partitioning information between system partitions, and between system partitions and the corresponding data processing resources. Serial transmission may allow the partitioning information to be transmitted using a single I/O ASIC pin, and a single PC board trace. In addition to reducing the required number of I/O ASIC pins and PC board traces, the present invention may increase the overall reliability of the partitioning mechanism.

Abstract: The invention provides techniques for reducing the port pressure of a clustered processor. In an illustrative embodiment, the processor includes multiple clusters of execution units, with each of the clusters having a portion of a register file and a portion of a predicate file associated therewith, such that a given cluster is permitted to write to and read from its associated portions of the register and predicate files. A duplicator interconnection technique in accordance with the invention reduces port pressure by providing one or more global move units in the processor. A given global move unit uses an inter-cluster move instruction to copy a value from a portion of the register or predicate file associated with a source cluster to another portion of the register or predicate file associated with a destination cluster.

Abstract: Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected together. The single physical machine with multiple physical processors and resources is subdivided by software into multiple partitions, each with the ability to run a distinct copy, or instance, of an operating system. At different times, different operating system instances may be loaded on a given partition. Resources, such as CPUs and memory, can be dynamically assigned to different partitions and used by instances of operating systems running within the machine by modifying the configuration. The partitions themselves can also be changed without rebooting the system by modifying the configuration tree. CPUs, in particular, may be migrated, or reassigned, from one operating system instance to another, allowing different loads in the system to be accommodated.

Abstract: Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected together. The single physical machine with multiple physical processors and resources is subdivided by software into multiple partitions, each with the ability to run a distinct copy, or instance, of an operating system. At different times, different operating system instances may be loaded on a given partition. Resources, such as CPUs and memory, can be dynamically assigned to different partitions and used by instances of operating systems running within the machine by modifying the configuration. The partitions themselves can also be changed without rebooting the system by modifying the configuration tree. CPUs, in particular, may be migrated, or reassigned, from one partition and operating system instance to another, allowing different loads in the system to be accommodated.

Abstract: A mechanism for performing parallel computations on an emulated spatial lattice by scheduling memory and communication operations on a static mesh-connected array of synchronized processing nodes. The lattice data are divided up among the array of processing nodes, each having a memory and a plurality of processing elements within each node. The memory is assumed to have a hierarchical granular structure that distinguishes groups of bits that are most efficiently accessed together, such as words or rows. The lattice data is organized in memory so that the sets of bits that interact during processing are always accessed together. Such an organization is based on mapping the lattice data into the granular structure of the memories in a manner that has simple spatial translation properties in the emulated space. The mapping permits data movement in the emulated lattice to be achieved by a combination of scheduled memory access and scheduled communication.

Abstract: An architecture combining an associative processor memory array and a random access memory is provided. This combination architecture enables utilizing the parallel processing abilities of the associative processor memory array while storing temporary results and parameters in the random access memory for a fully programmable, low-cost die suitable for consumer electronics applications. Parallel communication between thousands of memory words in the associative memory array and the random access memory is provided via logic hardware operative as source and destination for associative search and modify (compare and write) processing operations and also operative to read and write thousands of data elements from and to the random access memory. The tags register also serves as a communication bus for parallel communication between associative memory words.

Abstract: An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a rectangular array of processing elements and a controller. The apparatus offers a number of techniques for shifting image data within the array. A first technique, the ROLL option, simultaneously shifts image planes in opposite directions within the array. A second technique, the gated shift option, makes a normal shift of an image plane to neighboring PEs conditional, for each PE, upon a value stored in a pattern register of each PE. A third technique, the carry propagate option, combines the computations from multiple PEs in order to complete an n-bit operation in fewer than n clocks by forming “supercells” within the array. The apparatus also includes a multi-bit X Pattern register and a multi-bit Y Pattern register.

Abstract: A microprocessor, comprising a first set of functional units capable of performing parallel data operations, a second set of functional units capable of performing parallel data operations, and a data interconnection path connecting the first and second functional units.

Abstract: A manifold array topology includes processing elements, nodes, memories or the like arranged in clusters. Clusters are connected by cluster switch arrangements which advantageously allow changes of organization without physical rearrangement of processing elements. A significant reduction in the typical number of interconnections for preexisting arrays is also achieved. Fast, efficient and cost effective processing and communication result with the added benefit of ready scalability.

Abstract: A single chip application specific integrated circuit (ASIC) which provides a flexible, modular interface between a subsystem and a standard system bus. The ASIC includes a microcontroller/microprocessor, a serial interface for connection to the bus, and a variety of communications interface devices available for coupling to the subsystem. A three-bus architecture, utilizing arbitration, provides connectivity within the ASIC and between the ASIC and the subsystem. The communication interface devices include UART (serial), parallel, analog, and external device interface utilizing bus connections paired with device select signals. A low power (sleep) mode is provided as is a processor disable option.

Abstract: A parallel processing system or processor has a computing architecture including a plurality of execution units to repeatedly distribute instruction streams within the processor via corresponding buses, and a series of processing units to access the buses and selectively execute the distributed instruction streams. The execution units each retrieve an instruction stream from an associated memory and place the instruction stream on a corresponding bus, while the processing units individually may select and execute any instruction stream placed on the corresponding buses. The processing units autonomously execute conditional instructions (e.g., IF/ENDIF instructions, conditional looping instructions, etc.), whereby an enable flag within the processing unit is utilized to indicate occurrence of conditions specified within a conditional instruction and control selective execution of instructions in response to occurrence of those conditions.

Abstract: An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a rectangular array of processing elements and a controller. The apparatus offers a number of techniques for shifting image data within the array. A first technique, the ROLL option, simultaneously shifts image planes in opposite directions within the array. A second technique, the gated shift option, makes a normal shift of an image plane to neighboring PEs conditional, for each PE, upon a value stored in a mask register of each PE. A third technique, the carry propagate option, combines the computations from multiple PEs in order to complete an n-bit operation in fewer than n clocks by forming "supercells" within the array. The apparatus also includes a multi-bit X Pattern register and a multi-bit Y Pattern register.

Abstract: A vector processor architecture provides vector registers of fixed size having data elements of programmable size and type. The type and size for data elements are defined by instructions which manipulate operands associated with the vector registers. The data size defined by an instruction determines the number of the data elements in a vector register and the number of parallel operations performed to complete the instruction. One embodiment of the invention supports 8-bit, 9-bit, 16-bit, and 32-bit data element sizes of integer type for all sizes and floating point data type for the 32-bit data elements.

Abstract: A byte accessible memory interface circuit using a reduced set of memory control signals. The present invention includes an interface circuit having a reduced set of memory control signals for performing word length reads and writes to an external memory module containing a plurality of integrated circuit (IC) memory chips. The interface circuit contains a respective multiplexer and a respective register circuit for each byte of the word length data. The multiplexers select a byte of data from either an on-chip data bus or from a bus carrying data read from the external memory module. To perform a full length word write, the data from the on-chip bus is loaded into the registers (via the multiplexers) and then written to the memory module. To perform a partial length word write, a pre-read operation is performed at the target address and a word length data is loaded into the registers. The new data is then received over the on-chip data bus and routed by the multiplexers into the byte locations to be changed.

Abstract: A system for compiling a computer program to implement parallel image processing on a computer having a plurality of arithmetic processors. The program is analyzed to determine whether it contains a parallel image processing identifier, and if so, a plurality of parallel image processing execution codes are generated for use by the arithmetic processors. Thereby, allowing image processing to be conducted at an increased speed.

Abstract: A parallel computer system capable of arbitrarily selecting nodes participating in barrier synchronization while enabling an arbitrary number of node groups to independently execute a process requiring the barrier synchronization. A communication network for the parallel computer system includes a plurality of routing controllers. Each routing controller has a register for setting a predetermined number of receipts of barrier synchronization request messages from other routing controllers, a destination to which the barrier synchronization request message is transmitted, and a destination to which a barrier synchronization establishment message is transmitted.