Abstract: A programmable logic device (PLD) includes programmable logic circuitry and a bridge circuitry. The bridge circuitry includes a first interface circuitry and a first signal select circuitry. The first signal select circuitry couples to the first interface circuitry and the programmable logic circuitry. The bridge circuitry further includes an information interchange circuitry. The first signal select circuitry is configured to selectably provide a communication path between the information interchange circuitry and either the programmable logic circuitry or the first interface circuitry.

Abstract: A design apparatus for designing a configurable processor for an application, includes an analysis unit that analyzes the content of a program to be executed by the processor; a hardware extension unit that searches the program for a part of the program allowing hardware extension in accordance with the analysis results by the analysis unit and generates hardware extension information for the searched part; an extension instruction definition unit that searches the program for a part allowing use of an extension instruction in accordance with the analysis results by the analysis unit and generates definition of an extension instruction for the searched part; and a performance estimation unit that estimates whether or not the performance of the processor satisfies a target performance using at least one of the hardware extension information generated by the hardware extension unit and the definition of the extension instruction generated by the extension instruction definition unit.

Abstract: A configurable processor module accelerator using a programmable logic device is described. According to one embodiment, the accelerator module includes a circuit board having coupled thereto a first programmable logic device, a controller, and a first memory. The first programmable logic device has access to a bitstream which is stored in the first memory. Access to the bitstream by the first programmable logic device is controlled by the controller. The bitstream is capable of being instantiated in the first programmable logic device using programmable logic thereof to provide at least a transport interface for communication between the first programmable logic device and one or more other devices associated with the motherboard using the microprocessor interface.

Abstract: An integrated circuit having computational elements. As least one of the computational elements has a fixed architecture. An interconnection network is coupled to a first group of the computational elements to configure the first group for a first operation. An interconnection network is coupled to a second group of computational elements to configures the second group for a second operation.

Abstract: A programmable digital signal processor including a clustered SIMD microarchitecture includes a plurality of accelerator units, a processor core and a complex computing unit. Each of the accelerator units may be configured to perform one or more dedicated functions. The processor core includes an integer execution unit that may be configured to execute integer instructions. The complex computing unit may be configured to execute complex vector instructions. The complex computing unit may include a first and a second clustered execution pipeline. The first clustered execution pipeline may include one or more complex arithmetic logic unit datapaths configured to execute first complex vector instructions. The second clustered execution pipeline may include one or more complex multiplier accumulator datapaths configured to execute second complex vector instructions.

Abstract: Operating code fixes are supplied to multiple processors utilizing the same operating code by storing the correction code fixes in a central RAM, and distributing the code fixes over a dedicated code fix bus to a local cache for each processor. The first processor encountering a code fix requests the code fix from the RAM, which then distributes the code fix over the code fix bus to all of the local caches which are automatically updated with the new code. The system is particularly applicable to an integrated circuit having multiple processors fabricated on a chip, wherein the RAM is on-chip and is connected to an off-chip EEPROM that loads corrected code fixes to the on-chip RAM at power-up.

Abstract: A microprocessor architecture including a finite state machine in combination with a microcode instruction cache for executing microinstructions. Microinstructions which would normally result in small sequences of high-repetition looped operations are implemented in a finite state machine (FSM). The use of the FSM is more energy-efficient than looping instructions in a cache or register set. In addition, the flexibility of a cache, or other memory oriented approach, in executing microcode instructions is still available. A microinstruction is identified as an FSM operation (as opposed to a cache operation) by an ID tag. Other fields of the microinstruction can be used to identify the type of FSM circuitry to use, direct configuration of a FSM to implement the microinstruction, indicate that certain fields are to be implemented in one or more FSMs and/or in memory-oriented operations such as in a cache or register.

Abstract: A digital logic unit can be reconfigured and includes: a plurality of logic cells (19, 26) that have configurable properties; a memory (13) with a plurality of microprograms (14, 16) that contains information on the functionality of a plurality of logic cells (19, 26), at least one of the microprograms (14, 16) being reprogrammable depending on a certain application at least during the current operation of the logic unit; elements for selecting at least one microprogram (14, 16); and elements for configuring logic cells corresponding to the functionality information of the selected microprogram (14, 16) at least during the current operation of the logic unit.

Abstract: A non-volatile memory system is presented having a boot code section, wherein the size of the boot code section may be programmably selected. One embodiment of the non-volatile memory system includes a memory array, a logic unit, a control unit, and a program store. The memory array includes multiple non-volatile memory cells (e.g., flash EEPROM cells). The memory array is divided into memory blocks of equal size. A number of the memory blocks are allocated for boot code storage, forming a boot code section of the memory array. The control unit controls storage of data within and retrieval of data from the memory array. The control unit includes a configuration register having a boot code section size field. The contents of the boot code section size field determine the number of memory blocks making up the boot code section. The logic unit is coupled between the control unit and the memory array, and receives address, data, and control signals from an external source.

Abstract: A method and apparatus for processing data within a programmable gate array comprise a first fixed logic processor and a second fixed logic processor that are embedded within the programmable gate array and detect a custom operation code. The processing continues when a fixed logic processor provides an indication of the custom operational code to the programmable gate array. The processing continues by having at least a portion of the programmable gate array, which is configured as a dedicated processor, performing a fixed logic routine upon receiving the indication from the fixed logic processor.

Abstract: An integrated circuit device with a data processing block is provided, the data processing block including a plurality of operation units that are arranged in a matrix, a plurality of first wire sets that extend in a first direction in the matrix and transfer input data of each operation unit, a plurality of second wire sets that extend in a second direction in the matrix and transfer output data of each operation unit, and a plurality of switching units that are arranged at each intersection between the first and second wire sets and can select and connect any wire in the first wire sets and any wire in the second wire sets. The plurality of operation units include a plurality of types of operation units with different data paths that are suited to special-purpose, processing, with an arrangement of operation units of the same type in the first direction or the second direction being formed in at least part of the data processing block.

Abstract: On-the-fly reconfiguration of a secured CPLD. In one embodiment, a CPLD includes a novel security circuit that provides two different security control signals: an EEPROM/SRAM security signal and an EEPROM security override signal. The EEPROM/SRAM security signal prevents reading from both the EEPROM and the SRAM, and also prevents writing to the EEPROM. The EEPROM security override signal enables reading and writing for the EEPROM even when otherwise disabled by the EEPROM/SRAM security signal, but is active only when a specific set of conditions are met. These conditions can include, for example, the application of a sufficiently long erase pulse to the EEPROM array. Thus, the security on the EEPROM array is overridden only after the configuration data set stored in the EEPROM array has been erased. Reading from the SRAM is not enabled by the EEPROM security override signal. Therefore, the configuration data set is not compromised.

Abstract: A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, includes the steps of configuring the co-processor to implement an instruction set comprising one or more co-processor instructions, issuing a co-processor instruction to the co-processor, and determining whether the instruction is implemented in the co-processor. For an instruction not implemented in the co-processor instruction set, raising a stall signal to delay the main processor, determining whether there is enough space in the co-processor for the non-implemented instruction, and if there is enough space for said instruction, reconfiguring the instruction set of the co-processor by adding the non-implemented instruction to the co-processor instruction set. The stall signal is cleared and the instruction is executed.

Abstract: A re-configurable, streaming vector processor (100) is provided which includes a number of function units (102), each having one or more inputs for receiving data values and an output for providing a data value, a re-configurable interconnection switch (104) and a micro-sequencer (118). The re-configurable interconnection switch (104) includes one or more links, each link operable to couple an output of a function unit (102) to an input of a function unit (102) as directed by the micro-sequencer (118). The vector processor may also include one or more input-stream units (122) for retrieving data from memory. Each input-stream unit is directed by a host processor and has a defined interface (116) to the host processor. The vector processor also includes one or more output-stream units (124) for writing data to memory or to the host processor. The defined interface of the input-stream and output-stream units forms a first part of the programming model.

Abstract: A multiple level routing architecture for a programmable logic device having logical blocks, each logical block comprising a plurality of cells, with a first level routing resources coupling the cells of logical blocks. A second level routing resources coupling the first level routing resources through tab networks; each tab network comprises a first plurality of switches coupling the first level routing resources to an intermediate tab and the intermediate tab coupling the second level routing resources through a second plurality of switches, each switch may comprise an additional buffer. Repeated applications of tab networks provide connections between lower level routing resources to higher level routing resources.

Abstract: A method for programming of a plurality of programmable devices arranged in a JTAG boundary scan chain takes advantage of knowledge of a target system. The method speeds device programming and reduces system memory requirements. Raw data is extracted from high-level files. The raw data is stored in the target system. JTAG boundary scan chain information is coded into device programming software. Alternatively, the JTAG chain information is stored as data in the target system. The device programming software treats JTAG I/O registers of the programmable devices as concatenated shift registers. Data packets are assembled that include, for example, a byte of programming information, for each of the devices. The packets are shifted through into the JTAG chain. Bytes of the packet are aligned with, and loaded into, respective devices. Optionally, the validity of data loaded is checked by comparing it to the stored raw data. Invalid data is reprogrammed.

Abstract: A reduced instruction set computer architecture implemented on a field programmable gate array includes a parallel bit shifter capable of reversible shifts and bit reversals, a Reed-Muller Boolean unit coupled to the parallel bit shifter and an immediate instruction function using a half-word literal field in an instruction word that impacts a whole word logically through a combination of modes that variously manipulates the distribution of a set of literal bits of the half-word literal field across the instruction word.

Abstract: To obtain a correct vector address even if an interrupt occurs during erasing or programming of the data in a built-in ROM 18 by moving a part of a built-in RAM 13 to a vector address area by a bus controller 27. Thereby, a microcomputer is prevented from running away and the safety of a system is improved at the time of on-board programming of the built-in ROM 18.

Abstract: An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). The packet processors (307, 313, 303) include a receive processor (421), a transmit processor (427) and a risc core processor (401), all of which are programmable. The receive processor (421) and the core processor (401) cooperate to receive and route packets being received and the core processor (401) and the transmit processor (427) cooperate to transmit packets. Routing is done by using information from the table look up engine (301) to determine a queue (215) in the queue management engine (305) which is to receive a descriptor (217) describing the received packet's payload.

Abstract: A programmable logic device (PLD) includes programmable logic circuitry and a bridge circuitry. The bridge circuitry includes a first interface circuitry and a first signal select circuitry. The first signal select circuitry couples to the first interface circuitry and the programmable logic circuitry. The bridge circuitry further includes an information interchange circuitry. The first signal select circuitry is configured to selectably provide a communication path between the information interchange circuitry and either the programmable logic circuitry or the first interface circuitry.

Abstract: Programmable on-chip identification circuitry and associated method are disclosed that provide integrated circuits with the ability to select and report from multiple different vendor and system identification configurations. The integrated circuit device includes programmable circuitry that utilizes vendor identification, system identification, configuration or other device information provided or selected at least in part based upon selection information from a source external to the integrated circuit. The selection information may be provided through one or more externally generated digital and/or analog control signals that are then processed within the integrated circuit device to select, access and utilize desired identification information stored in an on-chip database.

Abstract: A useful semiconductor processing device (LSI) is capable of implementing the precise setting of signals at the final stage of user system development and enabling the user to build a logic circuit in the device in a very short time. The LSI includes a CPU, a flash memory which is a nonvolatile memory, a programmable logic which is a SRAM-type field programmable gate array, and a configuration circuit which implements the logic circuit configuration operation. At the event of power-on reset, logic building data stored in the flash memory is transferred to the programmable logic to establish a logic circuit in it under control of the configuration circuit, so that the logic circuit built in the programmable logic can be used immediately after the power-on reset of the device.

Abstract: A programmable logic device which incorporates an innovative routing hierarchy consisting of the multiple levels of routing lines, connector tab networks and turn matrices, enables an innovative, space saving floor plan to be utilized in an integrated circuit implementation, and is particularly efficient when an SRAM is used as the configuration bit This floor plan is a scalable block architecture in which each block connector tab networks of a 2×2 block grouping is arranged as a mirror image along the adjacent axis relative to each other. Furthermore, the bidirectional input/output lines are provided as the input/output means for each block are oriented only in two directions (instead of the typical north, south, east and west directions) such that the block connector tab networks for adjacent blocks face each other in orientation. This orientation and arrangement permits blocks to share routing resources. In addition, this arrangement enables a 4×4 block grouping to be scalable.

Abstract: An improved method of upgrading the firmware of an electronic device is disclosed. The method is executed over a communications link. The method includes compression of a portion of the new firmware, but does not require the device to have any pre-existing decompression algorithms built into it. A system and device capable of executing the method is also disclosed.

Abstract: A method and configuration system are used for producing an application-specific functional module from a predefined functional module for a programmable controller. In this context, a marking device is useable to mask out subfunctions of the predefined functional module, so that just the software code for those subfunctions which is required in order to satisfy the functionality of the application-specific functional module are readable into the programmable controller. In this case, it is simultaneously necessary to ensure that only that software code which is not imperatively required for calculating a result for at least one of the unmarked subfunctions is masked out and is therefore not read in.

Abstract: The invention relates to a microprocessor having a plurality of components which are selected from registers (14,16), arithmetic logic units (30,32), memory (36,38), input/output circuits and other similar components where the plurality of components are interconnected in a manner which allows connection between some of the components to be varied under program control.

Abstract: Methods and structures for efficiently implementing an accumulator-based load-store CPU architecture in a programmable logic device (PLD). The PLD includes programmable logic blocks, each logic block including function generators that can be optionally programmed to function as lookup tables or as RAM blocks. Each element of the CPU is implemented using these logic blocks, including an instruction register, an accumulator pointer, a register file, and an operation block. The register file is implemented using function generators configured as RAM blocks. This implementation eliminates the need for time-consuming accesses to an off-chip register file or to a dedicated RAM block.

Abstract: A microcomputer with a built-in flash memory is obtained in which the flash memory can be properly rewritten with a rewrite program kept placed on the flash memory and without requiring additional complicated control circuitry. On accepting an erase/write command which constitutes a rewrite command, a flash memory module (2) outputs to a flash memory control circuit (3) a ready status signal RYIBY indicative of a busy state during execution of the series of processing. When the ready status signal RYIBY indicates the busy state, the flash memory control circuit (3) outputs a hold signal HOLD at active “H,” in order to inhibit a CPU (1) from accessing the flash memory module (2). When the ready status signal RYIBY has recovered the ready state, the flash memory control circuit (3) outputs the hold signal HOLD at “L” to allow the CPU (1) to access the flash memory module (2).

Abstract: A storage unit stores ranges of devices allocated for each sequence program. A device range checking unit sequentially extracts device notations indicating consecutive areas and commands specifying consecutive devices present in a sequence program, expands devices of the corresponding consecutive areas, and checks whether or not devices of consecutive areas are within a range of devices stored in the storage unit. The device range checking unit sequentially extracts device notations indicating consecutive areas and commands specifying consecutive devices present in a sequence program, expands devices of the corresponding consecutive areas, and checks whether or not devices of consecutive areas are within a range of devices stored in the storage unit.

Abstract: In a logic integrated circuit such as an FPGA, a controller reads in an instruction, and then directly transmits ON/OFF information for each of bits composing microcode included in the instruction, to registers and data memories that are allocated to each of the bits through control lines, to thereby control the registers and data memories. Thus, processing executed by the controller is simplified in this construction. This allows makings the controller having a simple structure, thereby making it possible to construct a simple CPU core on the logic integrated circuit such as the FPGA, decreasing a space of analytic logic, and eliminating necessity for re-integrating a hardware circuit every time the logic is renewed.

Abstract: The invention relates to a method and arrangement for programming and verifying EEPROM pages and a corresponding computer software product and a corresponding computer-readable storage medium, which can be used in particular to speed up the programming into the EEPROM of large amounts of data or code, such as occurs for example when smart cards are being personalized. The invention relates to an arrangement that sets up a DMA connection between EEPROM and RAM—not including the core of the microcontroller involved—and makes possible automatic programming of data blocks of random length from the RAM to the EEPROM including the verification of the programming operation against the original data in the RAM under the control of the EEPROM logic.

Abstract: An apparatus comprising a microcontroller configured to (i) send or receive data over one or more data lines when in a first mode and (ii) be programmed through said data lines when in a second mode.

Abstract: A system, such as a complex computer system, incorporates several programmable logic devices coupled to load their configuration code from associated EEPROMs; typically this load is automatic on powerup. The EEPROMs connect to one of several serial busses, typically JTAG busses, connecting the EEPROMs with a common configuration logic. A processor is configured to write programmable logic configuration code from its memory through the common configuration logic and over the serial busses into the EEPROMs. The processor is also capable of connecting to a network and fetching configuration code for writing to the EEPROMs.

Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.

Abstract: A semiconductor integrated circuits can send and receive signals to and form a configuration memory. The semiconductor integrated circuits is provided therein wiht an instruction memory, an instruction storage portion that stores reserved instructions as F instructions, and stores the substantially equivalent processing contents to the F instructions as substitute instructions for processing by the CPU, a pre-fetch portion, a history storage portion, a diagnosing portion for diagnosing the types of instructions, a reprogramming control portion for reprogramming the instructions, a CPU, an FPGA, a configuration data memory, a built-in memory, and a configuration data tag. When the configuration data of the F instruction does not exist in the FPGA, the substantially equivalent processing by FPGA is executed by the CPU by making use of the substitute instructions.

Abstract: A method and apparatus for processing data within a programmable gate array begins when a fixed logic processor that is embedded within the programmable gate array detects a custom operation code. The processing continues when the fixed logic processor provides an indication of the custom operational code to the programmable gate array. The processing continues by having at least a portion of the programmable gate array, which is configured as a dedicated processor, performing a fixed logic routine upon receiving the indication from the fixed logic processor.

Abstract: A customizable logging and content management system for indexing multimedia, including a synchronized timer object that provides a time reference upon request in connection with the media, and a logger object that logs predefined events that occur in the media by associating the events with respective time references from the timer object. A video server is provided that captures and digitally stores events logged by the logging application as media segments, and a search and retrieval engine is provided that enables that media segments to be located, retrieved and viewed based on the indexes. The system includes a graphical user interface generator that enables customized user interfaces and logging databases to be created from database tables for use in the logging application.

Abstract: A programmable address arithmetic unit and method for use on microprocessors, microcontrollers, and digital signal processors is described. The addressing arithmetic unit incorporates a programmable logic array or other programmable device coupled to address registers and the instruction stream, the address unit being responsive to commands in the processor's instruction set. A first set of instructions control the initialization and configuration of the address arithmetic unit logic. A second set of instructions reference operands using one or more addressing modes that calculate the operand's effective address using the logic programmed by said first set of instructions.

Abstract: A non-volatile memory system is presented having a boot code section, wherein the size of the boot code section may be programmably selected. One embodiment of the non-volatile memory system includes a memory array, a logic unit, a control unit, and a program store. The memory array includes multiple non-volatile memory cells (e.g., flash EEPROM cells). The memory array is divided into memory blocks of equal size. A number of the memory blocks are allocated for boot code storage, forming a boot code section of the memory array. The control unit controls storage of data within and retrieval of data from the memory array. The control unit includes a configuration register having a boot code section size field. The contents of the boot code section size field determine the number of memory blocks making up the boot code section. The logic unit is coupled between the control unit and the memory array, and receives address, data, and control signals from an external source.

Abstract: In an integrated circuit, an FPGA (2) has functions of a CPU core (5), and includes a user's circuit and so forth. This configuration allows the number of implemented components such as peripheral circuit chips to be decreased, and cost to be reduced. The integrated circuit is configured such that the CPU core (5), peripheral circuits thereof, and a system bus (8) are stored as logic data in a PROM (3), and the FPGA (2) performs functions as the CPU core (5), peripheral circuits (6) (7), and system bus (8) based on the logic data. Therefore, the CPU core (5), peripheral circuits (6) (7), and system bus (8) which have desired functions can be obtained according to contents of the logic data stored in the PROM (3). Further, a user can readily extend and change functions of the CPU core (5) by retrofitting a separate circuit to the system bus (8).

Abstract: Flash memory device capable of interpreting a write cycle and one or more subsequent write cycles as a generic command that includes one or more specific flash memory commands. The flash memory device includes a state machine capable of identifying the generic command, writing the specific flash memory commands to a buffer, and sequentially retrieving, interpreting and executing the buffered flash memory commands. The state machine can be configured as a microcontroller executing a state machine algorithm, and can be reprogrammed to correct design errors or to add new functionality to the flash memory device. The state machine algorithm can be stored in the flash memory device, and updated to interpret the same write cycle data in different ways. Accordingly, new functionality can be developed for the state machine long after its silicon has been designed and developed.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Abstract: An integrated circuit device and associated method are disclosed utilizing on-chip programmable circuitry that receives and stores vendor identification information, in particular, for devices meeting operational requirements of the Audio CODEC '97 Component Specification. The programmable circuitry allows for vendor ID information for multiple device configurations and/or multiple vendor supplied devices to be accurately reported to external devices. In particular, direct-access-arrangement (DAA) circuitry is disclosed having such on-chip programmable circuitry that may be loaded with vendor identification information at least in part from an external source. The external source may in turn be programmable circuitry, such as a EEPROM.

Abstract: A CAN device that supports a plurality n (where n≧3) of message objects, including a plurality of registers associated with each message object, including at least one object match ID register that contains a multi-bit object match ID field, and at least one object mask register that contains a multi-bit object mask field; and, a CAN/CAL module that processes incoming messages. The CAN/CAL module assembles a multi-bit screener ID from selected bits of each incoming message to be acceptance filtered, compares the bits comprising the screener ID with corresponding bits of the object match ID field associated with each of at least designated ones of the plurality n of message objects, disregarding any bits of each object match ID field that are masked by corresponding bits of the associated object mask field, and then determines whether any of the comparisons results in a match.

Abstract: A data processing system having a user configurable memory controller, one or more local block RAMs, one or more global block RAMs and a processor core can be configured in a single field programmable gate array (FPGA). The address depth of the global block RAMs and the number of wait states can be selected by a user, and they can be set either prior to configuration of the FPGA or programmed using instructions of the processor core. The number of wait states of the local block RAM is also user selectable. An algorithm that can optimize the address depth and the number of wait states to achieve a performance level is also disclosed. The present invention can be applied to designs having separate instruction and data sides.

Abstract: An electronic control apparatus for vehicles has at least two microcomputers, each having a non-volatile flash memory which stores a vehicle control program and data. Each microcomputer is reset when an abnormality is detected. Each microcomputer is applied with an identification signal indicative of a main one or sub one. When a data rewriting instruction is applied from an external writing device, one microcomputer which receives the identification signal indicative of the main one operates to release the other microcomputer from the reset condition after an elapse of a delay time period. A new control program and data transmitted from the external writing device is written into the corresponding flash memory in place of the previously stored control program and data.

Abstract: A computer system includes a Flash or other nonvolatile memory. A program(s) to coordinate data transfers is loaded into a volatile system memory to transfer data from an external device to the Flash memory. The data transferred from the external device to the Flash memory can be transferred to a previously unused portion of the Flash memory, or alternatively can overwrite a previously used portion of the Flash memory. According to one aspect of the invention, the data is transferred from the external device to the volatile system memory and then from the volatile system memory to the Flash memory, allowing additional verification steps to help insure that the data is transferred intact. According to another aspect of the invention, data is copied from the external device to the Flash memory on a portion by portion basis, leaving a set of critical portions to be transferred last.

Abstract: A central processor-coprocessor assembly comprising an assembler software tool for extending the base central processor tasks into at least one coprocessor. What is important is that the assembler software tool does not need to be rebuilt when changes are made to the coprocessor elements. The invention allows assembly time extension of a base core language processing (CLP) programming model, without the need to rebuild the assembler tool itself. The assembler tool comprises a set of commands which enable the central processor to manipulate the coprocessor registers, and a coprocessor execute instruction, which initiates command processing on the coprocessor. The present invention simplifies the maintenance of the assembler tool through multiple hardware revisions by enabling hardware designers to update their coprocessor definition files to reflect new or modified coprocessors.

Abstract: A flash memory rewriting circuit capable of rewriting a flash ROM without Presenting any problem from the viewpoint of security of programs. In a transfer Program storing region of the flash ROM is stored a program to activate a CPU of a microcontroller and to transfer a rewriting data from external devices to peripherals. On a mask ROM is written, in a fixed manner, a program to activate a CPU and to write the rewriting data on a region other than the flash ROM. Because the program stored in the transfer program storing region is installed by users, no on except user can read or rewrite the program.

Abstract: A reconfigurable chip is described using a reconfigurable functional unit including a shifter unit, arithmetic logic unit and multiplexers. The data path units are interconnected to other data path units. The interconnection is preferably done by transferring word length data. The shifter allows for the word length data to be adjusted for use in the arithmetic logic unit. In a preferred embodiment the reconfigurable functional units are controlled by reconfigurable functional unit instructions. The reconfigurable functional unit instructions preferably are stored in a reconfigurable functional unit instruction memory which is addressed by a state machine on the chip.