Abstract: An integrated programmed logic circuit for performing complementary hardware and software based logic functions includes multiple programmed circuit portions. The portion programmed for performing the software based logic functions is programmably configured in a circuit configuration which includes and changes among multiple operation configuration states in accordance with its execution of its instructions. The portion programmed for performing the hardware based logic functions is programmably configured in a circuit configuration which remains in a single operation configuration state prior to, during and subsequent to its processing of data. Hence, the division of processing, i.e., hardware based and software based, can be designed as most appropriate for the particular application, e.g., more hardware based and less software based processing when speed is more important, and more software based and less hardware based processing when processing flexibility is more important.

Abstract: A method and apparatus for storing a value in a non-volatile memory device is disclosed. The non-volatile memory device includes a plurality of address pins for concurrently receiving the respective bits of an address value while the non-volatile memory device is in a parallel interface mode. In response to one or more signals, the non-volatile memory device is transitioned to a serial interface mode to enable a serial input. A sequence of bits is received in the non-volatile memory device via the serial input. The first portion of the sequence of bits represents a store command and a second portion of the sequence of bits represents a data value. The data value represented by the second portion of the sequence of bits is then stored in the non-volatile memory device in response to the store command represented by the first portion of the sequence of bits.

Abstract: A digital signal processing device (e.g., DSP), employed by electronic musical instruments and the like, is designed to perform a variety of digital signal processings. The digital signal processing device contains an arithmetic unit which is configured by at least an adder and a multiplier. There are provided first and second microprograms, each of which consists of microinstructions and each of which is designed to perform a specific kind of digital signal processing. The first and second microprograms are alternatively selected in accordance with a preset sequence of processing; and consequently, data supplied to the arithmetic unit are changed in response to the microprogram selected. Thus, the arithmetic unit performs arithmetical operations, using the data selectively supplied thereto, in accordance with the microprogram selected. By changing the sequence of processing, it is possible to easily change a manner of digital computing performed by the digital signal processing device.

Abstract: An in-system programming/erasing/verifying structure for non-volatile programmable logic devices includes a data input pin, a data output pin, an instruction register, a plurality of data registers including an ISP register, wherein said instruction register and said plurality of data registers are coupled in parallel between said data input pin and said data output pin, and a controller for synchronizing said instruction register and said plurality of data registers. The ISP register includes: an address field, a data field, and a status field. An ISP instruction need only be entered once to program/erase the entire device. Specifically, the address/data packets can be shifted back to back into the ISP register without inserting multiple instructions between each packet at the data input pin, thereby dramatically decreasing the time required to program/erase the entire device in comparison to known ISP methods. Furthermore, the invention provides an efficient method for providing the status (i.e.