Abstract: A programmable arithmetic and logic unit (ALU) comprising a plurality of data selectors, the data selectors having corresponding data input lines; a plurality of ALU function input lines wherein the number of ALU function input lines is equal to the number of data input lines on each of the data selectors, and each ALU function input line corresponds to one data input line on each of the data selectors; wherein each of the data input lines of each of the data selectors is connected to the corresponding data input lines of each of the other data selectors and to the corresponding ALU function input line.

Abstract: A system method and computer program for smart card with memory is disclosed. A very low cost approach two embodiment is disclosed, making use of a microcontroller with a FLASH memory or a WORM memory. An approach two programming a flash memory under the control of instructions within that memory itself is disclosed. Utilizing the invention it is possible to build smart cards at a low cost them heretofore.

Abstract: There is provided a copying system for copying information recorded on a first recording medium onto a second recording medium. The first recording medium is recorded with copying control information for representing conditions for permitting copying of the information recorded on the first recording medium, the copying control information being multiplexed within the information recorded on the first recording medium.

Abstract: A system for handling a power supply interruption in a non-volatile memory (10) is disclosed that includes a status indicator set (20) for each sector (16) of a non-volatile memory array (14). The status indicator set (20) is operable to indicate a status for the sector (16) and is independently erasable from the sector (16). A state machine (30) is operable to perform operations on the sectors (16). The state machine (30) is also operable to adjust the status indicator set (20) for a sector (16) prior to performing an operation on the sector (16) to indicate an interruption status and to adjust the status indicator set (20) for the sector (16) after completing the operation to indicate a completed status. Status indicator set (20) preferably includes alternatively employed active indicator sub-sets and erase indicator sub-sets.

Abstract: A digital signal processing device applicable to a signal processing system using a CPU is mainly configured by an external memory and a digital signal processor (i.e., DSP), which are connected together using a data bus and an address bus. The external memory stores multiplier data and coefficient data as well as basic instructions. In the DSP, an ALU calculates addresses for accessing the external memory via the address bus. A bus control unit identifies the multiplier data, coefficient data and basic instructions respectively, which are read from the external memory. The DSP performs calculations containing multiplication using the multiplier data and coefficient data. The DSP is controlled in operations in response to a CPU mode and a DSP mode, one of which is selected by decoding the basic instruction(s) identified by the bus control unit. At the CPU mode, the basic instructions of sixteen bits are subjected to coding to produce high-speed instructions of thirty-two bits for controlling the DSP.

Abstract: In accordance with the present invention, an FPGA input/output buffer including a tristate enable register is provided. A bus line provides the FPGA output through a tristate buffer to the pad or pin. A register controls the state of the tristate buffer. A register for providing an input signal from the pad or pin may also be provided. By placing an address on address lines controlling the register clocks, any selected one of the input/output buffers can be accessed. In one embodiment, separate addresses are provided for loading a tristate control value into the output control register and for loading data into the input register.

Abstract: A single chip microcomputer 1 internally includes a flash memory 2, a communication port 5, a CPU 4, an internal ROM 3, and a programming control circuit 6. The flash memory 2 includes, as a paired area, a first area A for storing a program, and a second area B for indicating a write inhibition flag, a read inhibition flag and an erase inhibition flag, which are management information for managing the first area A. When the CPU receives a programming request from an external device, the CPU refers to the management information stored in the second area B to determine whether or not a programming of the first area A should be executed. Thus, the single chip microcomputer can easily manage the writing, reading and erasing to the flash memory provided with a security measure, and on the other hand, can have a security of the degree sufficient to protect the copy right.

Abstract: An EEPROM is incorporated in a single chip microcomputer for storing programmed instruction codes, and is tested before separation of a semiconductor wafer into semiconductor chips, wherein pads used in the EEPROM test are arranged along an edge of the semiconductor chip so as to permit an external tester to concurrently bring two rows of probes into contact therewith, thereby improving the testability.

Abstract: A control unit that includes a processor having at least a first chip select output and a second chip select output. A signal provided by the first chip select output is activated during a normal operating mode of the control unit, and a signal provided by the second chip select output is activated during an application mode of the control unit. The control unit also includes a RAM memory having a chip select input for selecting the RAM memory and having a memory area for use as an application memory. A combination element electrically couples the signal provided by the first chip select output and the signal provided by the second chip select output to the chip select input of the RAM memory such that the signal provided by the first chip select output and the signal provided by the second chip select output do not have a perturbing effect on each other.

Abstract: A communications socket between a logic simulator and a system for generating input stimuli based on the current state of the logic simulator is provided. Input stimuli to the logic simulator for use in implementing a particular circuit design simulation are calculated by interfacing an input program which models the function of the circuit being designed with the logic simulator. The lines in this input program are converted by an adaptive vector generator into communications signals which are understandable by the logic simulator so that the desired simulation may take place. The input program thus enables the adaptive vector generator to behaviorally model complex logical systems that the logic simulator model is only a part of and allows for more accurate and detailed simulation. The adaptive vector generator does this by determining the next input vector state in accordance with the present state of the logic simulator model as received from the communications socket.

Abstract: A programmable logic device which incorporates an innovative routing hierarchy consisting of the multiple levels of routing lines, connector tab networks and turn matrices, enables an innovative, space saving floor plan to be utilized in an integrated circuit implementation, and is particularly efficient when an SRAM is used as the configuration bit. This floor plan is a scalable block architecture in which each block connector tab networks of a 2×2 block grouping is arranged as a mirror image along the adjacent axis relative to each other. Furthermore, the bidirectional input/output lines are provided as the input/output means for each block are oriented only in two directions such that the block connector tab networks for adjacent blocks face each other in orientation. This orientation and arrangement permits blocks to share routing resources. In addition, this arrangement permits blocks to share routing resources. In addition, this arrangement enables a 4×4 block grouping to be scalable.

Abstract: A memory device which utilizes a plurality of memory modules coupled in parallel to a master I/O module through a bus. Each memory module has independent address and command decoders to enable independent operation. Thus each memory module is activated by commands on the bus only when a memory access operation is performed within the particular memory module. Each memory module has a programmable identification register which stores a communication address of the module. The communication address for each module can be changed during operation of the memory device by a command from the bus. The memory device includes redundant memory modules to replace defective memory modules. Replacement can be carried out through commands on the bus.

Abstract: The present invention is a method and apparatus for performing a multimedia function. A data port receives the input data. A shared memory is coupled to the data port for storing the input data. A multimedia syntax is coupled to the shared memory for processing the input data based on a configuration information. The multimedia syntax corresponds to the multimedia function.

Abstract: A data processor is provided which has integrated therein at least two of a bootstrap memory, a program memory and a data memory, wherein the at least two memories are of the same construction. In an exemplary embodiment, the memories are flash EEPROM memories. The data memory is provided with registers for temporarily storing the contents of an entire row of memory such that modifications can be easily made to a single bit within the row by storing the contents of the row, erasing the row, modifying the data and storing the data back in the row.

Abstract: A processing system in accordance with the present invention is disclosed. The processing system comprises a processor and a microcode sequencer coupled to the processor. The microcode sequencer includes a plurality of modules. Each of the modules enables a specific function based upon a selection signal from the processor. A system and method in accordance with the present invention provides for many advantages over conventional systems. First of all, there is an efficient register bank and the hardware is smaller and more efficient than a DSP. Finally, since it is possible to program macro instructions for different applications, it is more flexible than DSP systems. It also is smaller, has a lower gate count and is faster to market because it is software programmable. Unlike RISC or coprocessor type systems, only a single assembler is needed to handle DSP and multimedia instructions. In addition, a large cache memory is not required while having a higher code density for a particular application.

Abstract: An enhanced memory algorithmic processor (“MAP”) architecture for multiprocessor computer systems comprises an assembly that may comprise, for example, field programmable gate arrays (“FPGAs”) functioning as the memory algorithmic processors. The MAP elements may further include an operand storage, intelligent address generation, on board function libraries, result storage and multiple input/output (“I/O”) ports. The MAP elements are intended to augment, not necessarily replace, the high performance microprocessors in the system and, in a particular embodiment of the present invention, they may be connected through the memory subsystem of the computer system resulting in it being very tightly coupled to the system as well as being globally accessible from any processor in a multiprocessor computer system.

Abstract: A data processing apparatus includes a storage format setting unit for setting a storage format in an interactive manner in order to store acquisition data, acquired from a control appliance connected thereto, a storage file forming unit for forming a storage file used to store the acquisition data based upon the storage format set by this storage format setting unit, and a storage unit for storing the acquisition data acquired from the control appliance in the storage file formed by this storage file forming unit according to the storage format set by the storage format setting unit.

Abstract: A reduced programmable controller for an extensible digital signal processing architecture supports particular instructions to facilitate common digital signal processing operations. These instructions include extract and insert instructions, which are useful in managing the storage and extraction of digital signal processing variables to and from registers, and also useful in assembling fixed-length digital signal parameters from a section of a bitstream stored in a register. These instructions further include leading value detect instructions, including a leading zero detect instruction and a leading one detect instruction which are useful in parsing unique prefix codes such as Huffman codes used in MPEG encoding of video and other variable length codes, and useful in handling of a priority encoder such as a task manager.

Abstract: A CPU is provided with an ability to modify its operation in accordance with an encryption key. When a program is compiled, the program is modified in order that execution may be performed with the CPU with its operation modified. As a result, it is unnecessary to decrypt the program into standard op codes prior to execution. The keyed program operation permits secure transfer of program data through open channels such as the Internet. A programmable instruction decoder programmable decodes encrypted instruction op codes, without decrypting them into standard op codes. Logic is used to accomplish network handshaking. The network handshaking further used to provide additional key information for continued operation the CPU.

Abstract: The invention relates to a microprocessor having a plurality of components which are selected from registers (14, 16), arithmetic logic units (30, 32), memory (36, 38), input/output circuits and other similar components where the plurality of components are interconnected in a manner which allows connection between some of the components to be varied under program control.

Abstract: A data processing apparatus and a data processing method for implementing data-tuning rapidly, in which when CPU is operating based on PROM data, it permits operation to implement while referring to data which is rewritten to RAM without stop of the operation. There is provided a CPU core for performing program operation for the purpose of implementing of data processing, a PROM for storing data which is referred at the time of data processing, a register for memorizing a data-stored-address, and a comparator for comparing an address.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Abstract: A data processor including: a CPU (1) for performing a wait operation upon input of a wait signal (10) to its wait terminal (9); a wait/wait cancel instruction setting register (11) to which the CPU (1) sets a wait instruction and a wait cancel instruction; and a wait controller (12) for outputting a wait signal to the wait terminal (9) of the CPU (1) in accordance with the setting of the register (11), wherein the inventive data processor allows a wait state to be set and canceled as programmed independently of address space constraints.

Abstract: In a camera which mounts a microcomputer with an internal flash memory, it is impossible to arbitrarily rewrite the contents of all program areas in the flash memory. In this invention, the flash memory is divided into a plurality of banks, and one bank holds a control program for altering the contents of the flash memory. Upon rewriting contents of this bank, the control program held in that bank is copied to the other bank, and the contents of that bank are rewritten under the control of the control program on the other bank.

Abstract: A digital signal processing device (e.g., DSP), employed by electronic musical instruments and the like, is designed to perform a variety of digital signal processings. The digital signal processing device contains an arithmetic unit which is configured by at least an adder and a multiplier. There are provided first and second microprograms, each of which consists of microinstructions and each of which is designed to perform a specific kind of digital signal processing. The first and second microprograms are alternatively selected in accordance with a preset sequence of processing; and consequently, data supplied to the arithmetic unit are changed in response to the microprogram selected. Thus, the arithmetic unit performs arithmetical operations, using the data selectively supplied thereto, in accordance with the microprogram selected. By changing the sequence of processing, it is possible to easily change a manner of digital computing performed by the digital signal processing device.

Abstract: A method is disclosed for integrating a field programmable gate array (FPGA) with a microprocessor to form a single, multi-chip or stacked, hybrid processor module. The method includes the identification and parallel routing of selected I/O pins of the FPGA and microprocessor. The method further includes the identification and routing of control pins of the FPGA and microprocessor to a controller, and, the establishment of an interface between the controller, the FPGA and the microprocessor in order to develop a processor module for coordinated processing of data utilizing both the FPGA and microprocessor resources.

Abstract: A data processing unit is described which comprises a central processing unit, a bus coupled with the central processing unit to access a device via address and data lines coupled with the bus. A debug unit is coupled to the bus, a protection unit is coupled with the bus and with the debug unit for protecting access on the bus. The protection unit is programmable to operate in a protecting mode in which the bus can be protected and in a debug mode in which a signal is sent to the debug unit, whereupon the debug unit generates a debug signal.

Abstract: A data protecting method wherein a resident control program which is stored as to be resident in a storage medium driving device judges on the basis of instruction from an executing device for executing a specified process, whether a control program for executing the process is incorporated or not therein, searches the control program from a set storage medium when the result of judgment is NO, reads in the searched control program, and incorporates the read-in control program therein. A storage medium driving device which stores this resident control program as to be resident, and a storage medium which is driven by this device.

Abstract: An improved PC system that includes a main CPU microprocessor, a file-based operating system, and a DSP microprocessor arranged so that the DSP can execute main CPU operations during time intervals in which the main CPU is otherwise occupied, thereby increasing the bandwidth of the system is provided. This PC system may include multiple CPUs and/or multiple DSPs.

Abstract: A programmable address arithmetic unit and method for use on microprocessors, microcontrollers, and digital signal processors is described. The addressing arithmetic unit incorporates a programmable logic array or other programmable device coupled to address registers and the instruction stream, the address unit being responsive to commands in the processor's instruction set. A first set of instructions control the initialization and configuration of the address arithmetic unit logic. A second set of instructions reference operands using one or more addressing modes that calculate the operand's effective address using the logic programmed by said first set of instructions.

Abstract: An electronic system and a processing unit supporting a flexible microcode space and Basic Input/Output System (BIOS) space. The electronic system features a first circuit board having a connector interconnected to a processing unit. The processing unit includes a second circuit board having an embedded controller and an on-substrate memory. The non-substrate memory is coupled to the embedded controller via a communication line routed through or placed on the second circuit board. In one embodiment, during a boot procedure and upon executing an instruction requesting data to be obtained from the on-substrate memory, the embedded controller obtains at least one microcode instruction from the on-substrate memory via the communication line.

Abstract: A programmable logic device having redundant sets of logic blocks which are capable of being enabled or disabled. The programmable logic device includes a plurality of sets of logic blocks, a plurality of routing resources and a programming circuit. Good logic blocks are enabled and fully operational when programmed. Nonfunctional logic blocks are disabled, powered off and invisible to the programming software. Each set of logic blocks has a corresponding routing resource. The routing resource corresponding to an enabled set of logic blocks is capable of being configured to provide input and output data paths for the enabled set of logic blocks. The routing resource corresponding to a disabled set of logic blocks is capable of being configured to bypass the disabled set of the logic blocks. The programming circuit stores the configuration data for the routing resources and is capable of providing the configuration data to a routing resource that corresponds to an enabled set of logic blocks.

Abstract: A customizable instruction-set processor (10) implements complex, time-consuming operations by reconfiguring a portion of an instruction execution unit (34) to perform a group of specific functions in hardware rather than implementing a string of operations in software routines. The instruction execution unit (34) has a non-programmable section (46) and a programmable section (48) that receive an opcode and output control signals for controlling a datapath (16). The datapath (16) has a non-programmable datapath (18) and a programmable datapath (32). The programmable section (48) and the programmable datapath (32) are programmed by the user to provide a customizable instruction-set that controls and adds functionality to the customizable instruction-set processor (10).

Abstract: A method and an apparatus for retiming in a network of multiple context processing elements are provided. A programmable delay element is configured to programmably delay signals between a number of multiple context processing elements of an array without requiring a multiple context processing element to implement the delay. The output of a first multiple context processing element is coupled to a first multiplexer and to the input of a number of serially connected delay registers. The output of each of the serially connected delay registers is coupled to the input of a second multiplexer. The output of the second multiplexer is coupled to the input of the first multiplexer, and the output of the first multiplexer is coupled to a second multiple context processing element. The first and second multiplexers are provided with at least one set of data representative of at least one configuration memory context of a multiple context processing element.

Abstract: A system and method for the streamlined execution of complex or repeating instructions. The method comprises creating a specialized instruction unit for executing a group of operations and then executing the group as they appear in an instruction stream. The system includes a programmable specialized instruction unit for executing the group of instructions as they appear in an instruction stream. The method comprises receiving a plurality of instructions, examining the plurality of instructions, identifying a subset of the plurality of instructions, creating a specialized instruction unit which is operable to execute the subset, and executing the subset in the special instruction unit upon an occurrence of the subset. Examining the plurality of instructions may occur at such times as compiling a computer program, performing an initialization procedure, or fetching or decoding instructions before execution.

Abstract: A digital processor with reconfigurable architecture includes a processor input and a processor output. A library stores a plurality of related function sequences for executing a processor operation. Memory stores data as required by the function sequences. A configurable device is connected to the library and the memory and between the processor input and the processor output. The configurable device sequentially stores the function sequences from the library in a plurality of programmable gate arrays configurable by the function sequences. The configurable device reconfigures the programmable gate arrays with another of the function sequences to complete the processor operation.

Abstract: A flash memory capable of solving a problem of a conventional flash memory in that it requires considerable time and effort to measure supply voltages generated in the flash memory during writing, erasing and verifying operations, and is difficult to acquire accurate results, because they cannot be measured by a tester and must be measured manually by putting a probe directly to voltage supply lines.

Abstract: A microcontroller having a special function register to internally select between internal memory and external memory on the fly. Two data pointers in conjunction with the special function register result in four effective quick reference locations. The internal memory consists of one memory module having its array subdivided into a data memory store and a code memory store, and having a bank of pass devices to selectively isolate the code memory store from the data memory store. The present memory can further support concurrent writing to the data memory store while reading from the code memory store. This is done through one of two memory embodiments. In a first memory embodiment two y-decoders are used; a first y-decoder adjacent the code memory store and a second y-decoder adjacent the data memory store. When a simultaneous read/write instruction is started, the outputs from the second y-decoder and an x-decoder are latched.

Abstract: A communications system utilizes an embedded Digital Signal Processor (DSP), a DSP interface and memory architecture, a micro-controller interface, a DSP operating system (OS), a data flow model, and an interface for hardware blocks. The design allows software to control much of the configuration of the architecture while using hardware to provide efficient data flow, signal processing, and memory access. In devices with embedded DSPs, memory access is often the bottleneck and is tightly coupled to the efficiency of the design. The platform architecture involves a method that allows the sharing of the DSP memory with other custom hardware blocks or the micro-controller. The DSP can operate at full millions-of-instructions-per-second (MIPS) while another function is transferring data to and from memory. This allows for an efficient use of the memory and for a partitioning of the DSP tasks between software and hardware.

Abstract: A reconfigurable circuit wherein part or all of an instruction or a result of decoding thereof and output of said register file are inputted and a circuit structure thereof can be changed by an external signal is provided. If a bug occurs when part or all of the instruction or the result of decoding thereof and the output of the register file satisfy a particular condition, the reconfigurable circuit is reconstructed by an external signal so as to output a first signal under that particular condition. An interrupt control circuit controls a processing unit so as to carry out processing based on the first signal or processing to avoid the bug when the first signal is inputted.

Abstract: A chip includes a programmable logic device and a microprocessor, wherein at least one of the associated registers of the microprocessor is distributed in the programmable logic device. The distributed register is coupled to both the microprocessor and the programmable logic device. In this manner, the microprocessor has the ability to access the register and place a value into the programmable logic device all in one clock cycle. Additionally, the logic functions in the programmable logic device are also advantageously available to the microprocessor.

Abstract: A virtual network consists of many distributed virtual computers interconnected over a communication network of individual links, such as optical fibers or electrical conductors, for example. Each distributed virtual computer has at least two ports connected over respective links to other respective distributed virtual computers on the network. Each distributed virtual computer is connected to or resident within its own host, each host typically being a conventional computer such as a personal computer or a work station, for example, although at least one of the hosts may itself be another virtual computer. Each distributed virtual computer has reconfigurable logic elements such as an FPGA or an array of FPGAs.

Abstract: According to the present invention, a method for changing a program including a plurality of instructions in a processor having a ROM for storing the program therein is provided. The method includes the steps of: replacing one of the plurality of instructions which are stored in the ROM with data having a predetermined value; and interpreting the data having the predetermined value as an instruction.

Abstract: A method and apparatus for In-System Programming which overcomes the above-described disadvantages. The method and apparatus of the ISP system interfaces with the two oscillator (instead of I/O) pins on the microcontroller. By interfacing with the two oscillator pins, the need for extra isolation circuitry to isolate other circuits from the ISP circuits is avoided in most circumstances, without incurring the expense of an expensive JTAG tester or extra dedicated pins. The amount of isolation circuitry necessary is reduced because the two oscillator pins are usually connected to passive components (registers, capacitors, or crystals) which cannot be damaged by the relatively high programming voltages and which do not produce signals that would interfere with the ISP programming signals.

Abstract: To improve the efficiency of delayed transactions in bus-to-bus bridge systems which include at least one interface to a PCI bus, a bridge system is disclosed including at least a primary interface and an interface to a secondary subsystem for interconnecting a primary PCI bus system and the secondary subsystem. The system comprises a delayed transaction mechanism for enabling a transaction source attached to the primary PCI bus system to effect delayed transactions with a target in the secondary subsystem. This system has a programmable delay transaction timer which provides a degree of flexibility in the configuration of PCI systems. This flexibility can be exploited to provide considerable efficiency gains, albeit at the expense of some deviation of the strict requirements of the PCI Specification.

Abstract: An interface between the host CPU and the programmably memory, providing an address, data and read/write control signals to create a non-volatile sector within the programmable memory. In an embodiment when the system reset is de-asserted immediately after power-on, the size of the protected EEPROM area is sensed on special strapping option pins and automatically configures the non-volatile sector. This allows the size of the protected area to be changed on the manufacturing line as needed for different applications. Once configured to protect a specific size and location in the non-volatile memory, the invention prevents the write control signal to the memory to be asserted when the address of the data access requested by the CPU is in the protected area of the memory. This has the effect of preventing modification of the protected area by a sector modification algorithm.

Abstract: An architecture for microcontroller with embedded flash memory is provided. The microcontroller allows the reprogramming of data into the embedded flash memory of the microcontroller to be performed on-board without having to dismount the entire IC package of the microcontroller from the circuit board and then use a dedicated writer to perform the write operation. The reprogramming operation can be initiated either by an external reprogramming-enable signal or an internal reprogramming-enable signal. When either of these two signals is generated, it causes an OR gate to output a high-voltage logic signal to a multiplexer to thereby cause the multiplexer to select a ROM unit for connection to the microprocessor unit. This allows the microprocessor unit to execute a reprogramming control routine stored in the ROM unit. The flash memory unit further stores a reprogramming detection/initialization routine which checks whether a flash reprogramming request signal is issued from the main-unit interface.

Abstract: An arithmetic logic unit capable of executing an instruction belonging to a user-defined instruction area at the same clock frequency as a hard-wired logic includes a memory storing data at an arbitrary address and outputting the data stored in the address when an instruction code and an operand data are applied as an address. When an instruction decoder decoding part of the instruction code for setting the memory to read mode or write mode is provided, contents of the memory can be re-written, and therefore the content of the memory can be readily changed even after delivery. The arithmetic logic unit may include, in place of the memory, a programmable logic device adapted to receive an instruction code and the operand data and capable of organizing a desired logic.

Abstract: A method and apparatus for providing a programmable logic datapath that may be used in a field programmable device. According to one aspect of the invention, a programmable logic datapath is provided that includes a plurality of logic elements to perform various (Boolean) logic operations. The programmable logic datapath further includes circuitry to selectively route and select operand bits between the plurality of logic elements (operand bits is used hereinafter to refer to input bits, logic operation result bits, etc., that may be generated within the logic datapath). In one embodiment, by providing control bits concurrently with operand bits to routing and selection (e.g., multiplexing) circuitry, the programmable logic datapath of the invention can provide dynamic programmability to perform a number of logic operations on inputs of various lengths on a cycle-by-cycle basis.

Abstract: A microcomputer with embedded flash memory is provided, which has an on-chip programming capability that allows new data to be reprogrammed by the microcomputer itself into the embedded flash memory, without having to use external reprogramming tools. Moreover, a method is provided for programming data into the embedded flash memory of the microcomputer. The microcomputer includes a microprocessor unit, an embedded flash memory unit, a register set, and a bus multiplexer. The embedded flash memory unit is partitioned into a loader block for storing a loader program and a user block for storing at least one user application program. The new data that are to be programmed into the user block of the embedded flash memory unit are first transferred to and stored in the register set. In the embedded flash memory unit, only one of the loader block and the user block can be in active operation, which is controlled by the microprocessor unit.