Abstract: Methods, systems, and devices for power regulation for memory systems are described. In one example, a memory system, such as a memory module, may include a substrate, and an input/output component coupled with the substrate and operable to communicate signals with a host system. The memory system may also include one or more memory devices coupled with the substrate and the input/output component and operable to store data for the host system. A memory device of the one or more memory devices may include a power management component in its package with one or more memory dies. The power management component may be coupled with the one or more memory dies, and feedback component, and may be operable to provide one or more supply voltages for the one or more memory dies based on one or more voltages associated with the memory system.

Abstract: Methods and apparatus relating to techniques for repeating graphics render pattern detection are described. In an embodiment, a repeating pattern in a plurality of workload blocks is detected. Information corresponding to the plurality of workload blocks is stored and analyzed to determine a Dynamic Voltage Frequency Scaling (DVFS) sampling window of a processor. Other embodiments are also disclosed and claimed.

Abstract: A device includes a display, a camera, a memory storing a software code, and a hardware processor configured to execute the software code to: configure the device to be in a first mode; receive, from the camera, camera data of an environment surrounding the device; determine that a person is present in the environment based on the camera data; determine that the person is facing the display based on the camera data; and transition the device from the first mode to a second mode, in response to determining that the person is facing the display. The display displays a first content when the device is in the first mode, and displays a second content different than the first content when the device is in the second mode. The second content is configured to provide information about the device to the person without requiring the person to touch the device.

Abstract: An information processing apparatus includes a communication unit, a determination unit, a power mode setting unit, an input process unit, and a registration unit. The communication unit receives a communication packet. The determination unit determines whether the communication packet received by the communication unit in a second power mode of first and the second power modes meets at least one of a plurality of determination conditions included in determination condition information. The second power mode is lower in electric power consumption than the first power mode. The power mode setting unit switches a power mode from the second power mode to the first power mode on the basis of a result of determination performed by the determination unit. The input process unit receives user operation. The registration unit registers the determination conditions in the determination condition information on the basis of the user operation received by the input process unit.

Abstract: The present disclosure relates to a non-volatile memory device and to a method for generating overvoltage values in such a memory device structured in a plurality of sub-arrays and including at least a decoding and sensing circuitry associated with each sub-array, a charge pump architecture for each sub-array including pump stages for increasing the value of an input voltage and obtaining an overvoltage output value, a control and JTAG interface in the memory device, and at least a registers block coupled to the charge pump architecture and driven by a logic circuit portion for receiving at least an activation signal selecting a specific charge pump architecture associated with a memory sub-array of the plurality of sub-arrays.

Abstract: Methods and apparatus for dynamically adjusting performance of partitioned memory. In one embodiment, the method includes receiving one or more configuration requests for the memory device, determining whether to grant the one or more configuration requests for the memory device, in response to the determining, implementing the one or more configuration requests within the memory device and operating the memory device in accordance with the implementing. The adjusting of the performance for the partitioned memory includes one or more of enabling/disabling refresh operations, altering a refresh rate for the partitioned memory, enabling/disabling error correcting code (ECC) circuity for the partitioned memory, and/or altering a memory cell architecture for the partitioned memory. Systems and applications that may benefit from the dynamic adjustment of performance are also disclosed.

Abstract: An information handling system includes a processor, a plurality of dual in-line memory modules (DIMMs), and a basic input/output system (BIOS). During a power-on self-test (POST), the BIOS may read serial presence detect data from each of the DIMMs, determine a total amount of installed memory. The BIOS may determine whether the total amount of the installed memory exceeds a maximum memory capacity of the processor. If so, the BIOS may remove memory capacity of the DIMMs to create a second total amount of the installed memory that is less than the maximum memory capacity of the processor, configure a memory address decode register with the second total amount of the installed memory, and complete the POST.

Abstract: An apparatus includes a first control unit configured to shift to at least a first power mode and a second power mode where power saving is greater than that in the first power mode, a detection unit configured to detect a predetermined return factor and output a first signal, a second control unit, which includes a storage unit storing information about input of the first signal, configured to output a second signal based on the stored information, and a third control unit configured to output a third signal for shifting the first control unit from the second power mode to the first power mode based on the second signal. The third control unit sets a predetermined value in the storage unit when the first control unit shifts to the second power mode.

Abstract: One embodiment provides for a wearable electronic device comprising a display device, a memory device, and one or more processors to execute instructions stored in the memory device. The instructions cause the one or more processors to receive an interaction to transition an application to a front-most state on the wearable electronic device, receive a request to initiate an activity via the application in the front-most state, detect that the wearable electronic device has transitioned to a low power mode, and enable enhanced functionality for the application in the front-most state during the low power mode while the application is in the front-most stat. Enabling enhanced functionality for the application in the front-most state includes, for example, increasing an execution priority of the application while the application is in the front most state.

Abstract: The invention is related to a non-transitory computer program product, a method and an apparatus for controlling access to a flash storage. The method, performed by a processing unit of a bridge integrate circuit (IC), includes: receiving a host write command from a host side; determining whether the flash storage needs to enter a hibernate state based on at least information regarding a length of data that has been programmed into the flash storage and/or a quantity of host write commands that have been executed after executing the host write command; and instructing the flash storage to enter the hibernate state when the length of data and/or the quantity of host write command meets a triggering condition.

Abstract: A three-dimensional (3D) ultra-low power neuromorphic accelerator is described. The 3D ultra-low power neuromorphic accelerator includes a power manager as well as multiple tiers. The 3D ultra-low power neuromorphic accelerator also includes multiple cores defined on each tier and coupled to the power manager. Each core includes at least a processing element, a non-volatile memory, and a communications module.

Abstract: Technologies for performance monitoring include a computing device having multiple processor cores. The computing device performs a training workload with a processor core by continuously polling an empty input queue. The computing device determines empty polling thresholds based on the empty polling workload. The computing device performs a packet processing workload with one or more processor cores by continuously polling input queues associated with network traffic. The computing device compares a measured number of empty polls performed by the packet processing workload against the empty polling thresholds. The computing device configures power management of one or more processor cores in response to the comparison. The computing device may determine empty polling trends and compare the measured number of empty polls and the empty polling trends to the empty polling thresholds. Other embodiments are described and claimed.

Abstract: In one embodiment, a gaming system, method, and device may have a memory having a plurality of power management rules and a processor configured to receive a power status information from another device, retrieve at least one power management rule from the memory, and configure a power state of the gaming device or its peripheral device based on the power status information and the at least one power management rule.

Abstract: A motor drive is provided, which includes a control circuit, a first transistor, a first comparison circuit, a second transistor and a load. The control circuit includes a first output terminal and a second output terminal; the first output terminal outputs a first control signal; the second output terminal outputs a second control signal whose phase is inverse to the phase of the first control signal. The gate of the first transistor receives the first control signal. The first comparison circuit compares the gate-source voltage with a reference voltage to generate a first comparison signal. When the first comparison signal shows that the first control signal is reduced to be lower than the reference voltage, the second control signal generated by the second output terminal is transmitted to the gate of the second transistor.

Abstract: A system circuit board configured to be supplied by at least one power supply unit, with an operating voltage in an operating state and a stand-by voltage in at least one stand-by state, the system circuit board includes at least one connection device for at least one extension card, wherein the connection device is configured to provide at least one first card voltage on the basis of the operating voltage; at least one switching element arranged on the system circuit board and configured to disconnect the at least one connection device from the operating voltage; and a control device arranged on the system circuit board, and configured to identify a type of a connected power supply unit and send a switching signal to the switching element depending on the identified type.

Abstract: In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.

Abstract: A method for performing dynamic throttling control with aid of configuration setting and associated apparatus such as a host device, a data storage device and a controller thereof are provided. The method includes: utilizing the host device to provide a user interface, to allow a user to select any of a plurality of throttling control configurations of the data storage device; and in response to the selection of said any of the plurality of throttling control configurations by the user, utilizing the host device to send throttling control information corresponding to said any of the plurality of throttling control configurations toward the data storage device, to perform the dynamic throttling control on the data storage device during programming the NV memory, for limiting power consumption of the data storage device during programming the NV memory, wherein the throttling control information indicates performing the dynamic throttling control is required.

Abstract: A method is implemented by a network device for orchestrating execution of a polling thread of a software-based switching program on a heterogeneous multicore processor. The method includes causing the polling thread to be executed on a first processing core in a first cluster of a plurality of clusters of processing cores, determining a value indicative of a number of active processing cycles used by the polling thread, determining whether the value is higher than a high threshold associated with the first processing core or lower than a low threshold associated with the first processing core, and if so causing the polling thread to be moved to a second processing core in a second cluster of the plurality of clusters, where the second processing core has a different processing capacity than the first processing core.

Abstract: Methods and apparatus relating to techniques for processor core energy management are described. In an embodiment, energy management logic causes a modification to energy consumption by an electrical load (such as a processor core) based at least in part on comparison of an electrical current value and an operating current threshold value. The electrical current value is detected at an electrical current sensor coupled to the electrical load. Other embodiments are also disclosed and claimed.

Abstract: A storage controller includes a host interface which real-time analyzes a command received from a host, a programmable logic unit which loads an optimal image adaptively selected from a plurality of images in response to at least one of a current operating state of the storage controller and the command, and a processor which performs an operation on a nonvolatile memory device using the programmable logic unit after the optimal image is loaded.

Abstract: A system, method, and computer program product are provided for simultaneously determining settings for a plurality of parameter variations. In use, a plurality of parameter variations associated with a device is identified, where the plurality of parameter variations are organized into a plurality of segments. Additionally, settings for each of the plurality of parameter variations are determined and consistency of the settings across the plurality of segments is ensured.

Abstract: A data processing system may include servers configured for running virtual machines and a system controller configured to perform the following steps: receiving commands to terminate a hosting session of one or more virtual machines hosted on the servers; making a determination as to how much processing capacity is required of the plurality of host servers to host the remaining virtual machines following the termination of one or more virtual machines; and if hosting the remaining virtual machines requires less than a predetermined amount of processing capacity, moving all other processes from one or more host servers to other host servers and changing the one or more host servers from an online mode in which the one or more host servers are fully powered up to an offline mode in which the one or more host servers utilize a reduced amount of electrical power.

Abstract: A system for event notification based on editing a transponder identifier is disclosed herein. The system may include a sensor system, a transponder, a transponder reader, and a controller. The system may detect an event associated with a sensor. The system may identify a transponder associated with the sensor. The system may cause the transponder to store an event identifier in a memory location of an identifier, of the transponder, to form an edited identifier. The event identifier may be associated with the event. The system may determine that the transponder responded to the query from the transponder reader. The system may store a confirmation that the event identifier was provided to the transponder reader via the transponder.

Abstract: A reduction instruction receiver receives a reduction instruction for energy from a server. An energy setter sets, when the reduction instruction receiver receives the reduction instruction, individual target energies for the respective subsystems, the individual target energies each being a target value of a consumption energy for a corresponding subsystem such that (i) a total of individual target energies that are target values of consumption energies for the respective subsystems is smaller than a total target energy that is a target value of a consumption energy of an entirety of the subsystems, and (ii) a higher correlation among consumption energies of the respective subsystems provides an increase in a total margin energy, the total margin energy being a difference between the total target energy and the sum of the individual target energies. The control-instruction transmitter transmits control-instruction information for control of the facility device based on the set individual target energies.

Abstract: A system on chip (SoC) adjusts power of a memory through a handshake. The SoC includes a memory controller and a power manager. The memory controller is configured to control a memory. The power manager is configured to manage a supply power level of the memory. The memory controller is configured to output, to the power manager, a memory access level indicating a frequency of accesses to the memory. The power manager is configured to adjust the supply power level of the memory according to the memory access level.

Abstract: In accordance with one embodiment, a fan controller operates in a standard mode when main power is provided to the power supply unit in which speed of the fan is controlled in response to a primary pulse width modulation (PWM) signal from a power controller. A loss of the main power to the power supply unit may be detected at a logic circuit, which provides a secondary PWM signal to the fan controller in response to the loss of the main power. In certain embodiments, the fan controller is operated in a power loss mode in response to the secondary PWM signal to direct the speed of the fan to a low-power consumption target speed.

Abstract: Embodiments of systems and methods for managing turbo states based upon user presence are described. In some embodiments, a method may include detecting, by an Information Handling System (IHS), a presence state of a user, and modifying a turbo configuration of a component of the IHS in response to the presence state.

Abstract: A power throttling engine includes a register configured to receive a power throttling signal. The power throttling engine further includes a decoder configured to generate a vector based on a value of the power throttling signal. The value of the power throttling signal is an amount of power throttling of a device. The power throttling engine further includes a clock gating logic configured to receive the vector and further configured to receive a clocking signal. The clock gating logic is configured to remove clock edges of the clocking signal based on the vector to generate a throttled clocking signal.

Abstract: An embedded file network server based on a seismic data stream includes a broadband power management module, a main control unit, a serial-port-to-RS232 module, a PHY bridge layer, an SD card, and a network interface. The main control unit includes serial port, an SDIO interface, an internal RAM, DMA units, and a MAC drive layer. The main control unit performs seismic data interaction with an external device through the serial port, and receives seismic data through an internal interruption, and the received seismic data stream is stored in the internal RAM. The internal RAM transfers the received seismic data stream to the SDIO interface and MAC driver layer through the DMA units. The SDIO interface stores the seismic data stream in the SD card for data backup. The MAC driver layer is coupled to the PHY bridge layer for inputting and outputting the seismic data stream.

Abstract: Technologies for batching requests in an edge infrastructure include a compute device including circuitry configured to obtain a request for an operation to be performed at an edge location. The circuitry is also configured to determine, as a function of a parameter of the obtained request, a batch that the obtained request is to be assigned to. The batch includes a one or more requests for operations to be performed at an edge location. The circuitry is also configured to assign the batch to a cloudlet at an edge location. The cloudlet includes a set of resources usable to execute the operations requested in the batch.

Abstract: A system for setting a power cap state is disclosed. The system includes a plurality of power monitor sensors generating power monitor sensor data and a plurality of thermal monitor sensors generating thermal monitor sensor data. A controller has a plurality of inputs configured to receive the power monitor sensor data and the thermal monitor sensor data, to assign a priority to one of two or more power cap states and to generate a control signal. A power limiting circuit coupled to the controller is configured to receive the control signal and to modify one or more power settings.

Abstract: A method comprises analyzing performance data of a system using one or more machine learning techniques. The system comprises a plurality of hardware components. In the method, a priority list of the plurality of hardware components is generated based on the analysis, and power from one or more power sources is distributed to one or more of the plurality of hardware components based on the priority list.

Abstract: There is provided a control device that includes a processor and an energy harvesting unit. The processor acquires an electricity consumption amount necessary for execution of a predetermined function of the processor and an amount of energy harvested by the energy harvesting unit, and determines whether or not to execute the predetermined function based on the electricity consumption amount, the amount of energy harvested that are acquired.

Abstract: An electronic apparatus includes a detection unit configured to detect a change from a state where a person is present to a state where the person is absent based on output of a distance sensor which detects an object present within a predetermined detection range, and a captured image covering a predetermined imaging range.

Abstract: Inventive aspects include a device including storage media. The device includes a PMU, and a controller communicatively coupled to the PMU. The PMU determines that an operating power of the device exceeds a threshold, and transmits a signal to the controller to trigger a power reduction operation. The controller throttles one or more operations until the operating power goes below the threshold. Some embodiments include a method for controlling performance of a storage device. The method includes measuring, by a PMU, a power consumption associated with a storage device. The method includes determining, by the PMU, whether the power consumption is greater than a threshold. In response, the method may include setting a performance throttle. The method may include determining, by the PMU, whether the power consumption is less than the threshold. In response, the method may include releasing the performance throttle.

Abstract: Systems and methods for detecting gestures using ultrasonic clicks are described. For example, some methods include playing an ultrasonic click using an audio driver, wherein the ultrasonic click is a modulated audio pulse with a duration less than one hundred periods of a modulation frequency waveform of the ultrasonic click; accessing a recording, captured using a microphone, of the ultrasonic click; applying an ultrasonic bandpass filter to the recording to obtain a filtered signal; determining a classification of a gesture based on the filtered signal; and transmitting, storing, or displaying an indication of the classification of the gesture.

Abstract: An information processing apparatus including a volatile storage unit, and is operated in any of a plurality of modes including a first power mode and a second power mode, power being supplied to the storage unit in the first power mode and the second power mode, power consumption in the first power mode being higher than power consumption in the second power mode.

Abstract: Systems and methods described herein make previously stranded power capacity (power that is provisioned for a data center according to a computing system's nameplate power consumption but is currently not useable) available to the data center. Systems described herein generate empirical power profiles that specify expected upper bounds for the power consumption levels that applications trigger. Using the upper bounds for application power-consumption levels, a computing system described herein can reliably release part of its provisioned nameplate power for other systems or data center consumers, reducing the amount of stranded power in a data center. The method described herein avoids performance penalties for most jobs by using sensor measurements made at a rapid rate explained herein to ensure that a system power cap based on running application's measured peak power consumption is reliable with reference to the power capacitance inherent in the computing system.

Abstract: A multiplexing latch circuit includes first, second, and third tristate inverters and an inverter. The first tristate inverter includes an output terminal and an input terminal coupled to a first data line, the second tristate inverter includes an output terminal and an input terminal coupled to a second data line, and the third tristate inverter includes an input terminal and an output terminal. The first inverter includes an input terminal coupled to the output terminals of each of the first, second, and third tristate inverters, an output terminal coupled to the input terminal of the third tristate inverter, and is configured to generate an output signal based on data received on one of the first data line or the second data line.

Abstract: A timing control board includes a point-to-point interface, a storage, a signal input port and a timing controller. The storage is for storing multiple sets of different point-to-point configuration parameters. The timing controller obtains a set of point-to-point configuration parameters matching a protocol type of a source drive circuit board in the storage according to the configuration parameter selection signal, and initializes settings according to the set of point-to-point configuration parameters to generate matched data signals and output the data signals to the source drive circuit board through the point-to-point interface, so as to realize the compatibility of display panels and reduce the design cost.

Abstract: Systems and methods for centralized client application management are provided. In an example embodiment, device data is received from a user device. The user device is identified according to an identification rule. A client state is received from the user device. A match between the client state and a specified state is determined. Based on the client state matching the specified state, an instruction to be performed on the user device is generated. The instruction is caused to be performed on the user device. The instruction causes a change to the client state stored on the user device.

Abstract: Disclosed are systems and methods for cloud-based monitoring and control of physical environments. A system comprises a computing cloud with at least one processor configured to execute one or more application modules and a data analytics module for analyzing diagnostic and environmental metric data. The system further comprises a building server communicatively coupled with the computing cloud, at least one gateway communicatively coupled with the building server, and at least one system device communicatively coupled with the at least one gateway. The at least one system device generates environmental metric data for further analysis and display, and the data is communicated to the computing cloud by way of the at least one gateway and the at least one building server.

Abstract: Particular embodiments described herein provide for an electronic device that can be configured to receive a plurality of thermal parameters for a device, identify one or more of the plurality of thermal parameters that affect a thermal response of the device, and create a thermal vector for the device using the one or more of the plurality of thermal parameters that affect the thermal response of the device, where the thermal vector can be used to predict a new thermal response of the device. In an example, the thermal vector includes weighted thermal parameters.

Abstract: An apparatus comprises a processing device configured to obtain first parameters characterizing an operating state of information technology (IT) resources of a data center and second parameters characterizing an operating state of cooling systems of the data center, to determine an overall operating state of the data center by aggregating the first and second parameters, to identify a power consumption profile based on the overall operating state, and to perform a joint training of first and second reinforcement learning agents based on the overall operating state and the power consumption profile. The processing device is also configured to generate first controls for the heterogeneous IT resources utilizing the first reinforcement learning agent and second controls for the cooling systems utilizing the second reinforcement learning agent, the first and second controls being configured to reduce power consumption while maintaining specified performance benchmarks for workloads executing in the data center.

Abstract: A semiconductor device includes a circuit including an input coupled to a first node; and a first signal control circuit configured to determine a voltage of the first node in a low power mode, wherein the first signal control circuit sets a voltage of the first node to a first value in an n-th occurrence of the low power mode and a second value different from the first value in an m-th occurrence of the low power mode, and wherein n and m are two different natural numbers.

Abstract: There is provided a data storage system comprising a power supply module, a plurality of serially connected storage enclosures, where a first storage enclosure of the plurality of serially connected storage enclosures is connected to the power supply module, and a power management module connected to the power supply module. A given storage enclosure includes at least one disk storage. The power management module is configured to selectively cause the power supply module to provide electric power to activate the first storage enclosure. The power management module is further configured to selectively cause the power supply module to provide electric power to activate a second storage enclosure, where the second storage enclosure is connected downstream from the first storage enclosure, and the second storage enclosure is configured to selectively receive power from the power supply module in response to the first storage enclosure being active.

Abstract: An FPGA-based graph data processing method is provided for executing graph traversals on a graph having characteristics of a small-world network by using a first processor being a CPU and a second processor that is a FPGA and is in communicative connection with the first processor, wherein the first processor sends graph data to be traversed to the second processor, and obtains result data of the graph traversals from the second processor for result output after the second processor has completed the graph traversals of the graph data by executing level traversals, and the second processor comprises a sparsity processing module and a density processing module, the sparsity processing module operates in a beginning stage and/or an ending stage of the graph traversals, and the density processing module with a higher degree of parallelism than the sparsity processing module operates in the intermediate stage of the graph traversals.

Abstract: Methods, apparatus, and processor-readable storage media for automated device power conservation using machine learning techniques are provided herein. An example computer-implemented method includes obtaining usage-related data from one or more processing devices; determining at least one usage pattern for the one or more processing devices by processing the obtained usage-related data using one or more machine learning techniques; automatically generating, based at least in part on the at least one determined usage pattern, instructions pertaining to controlling one or more power states of the one or more processing devices; and performing at least one automated action based at least in part on the generated instructions.

Abstract: Provided is a semiconductor system. The semiconductor system includes a universal flash storage (UFS) host, including a host controller interface, a UniPro and a M-PHY; a UFS device configured to exchange data with the UFS host through a UFS interface; and an application processor configured to control the UFS host. The UFS device is configured to maintain a power-on status when the application processor operates in a suspend mode.

Abstract: The present application teaches methods and apparatuses related to providing dynamic auxiliary port power management including providing a first current to a first auxiliary port and a second current to a second auxiliary port, determining a system power level in response to the first current and the second current, comparing the system power level to a system power level threshold, and providing a third current to the second auxiliary port in response to the system power level exceeding the system power level threshold, the third current having a lower amperage than the second current.