Abstract: Apparatus for diagnosing and correcting faults in a host computer having a central processing unit (CPU) and ancillary units. The apparatus is in two parts; a first part in the form of a service card to be coupled to the host computer and operable to disable the CPU and operate and/or interrogate the ancillary units, and a second part in the form of a remote support station to be coupled to the first part and operable to diagnose faults in the computer through the first part and to effect at least some corrective measures through the first part. The first and second parts are located remote from each other and connected by a telecommunication link such as through modems.

Abstract: A method to protect against system memory configuration data loss and/or corruption includes obtaining configuration data from a computer system memory module, determining if the obtained configuration data is incorrect, and repairing the configuration data of the memory module if the obtained configuration data is incorrect. A computer system providing memory configuration data protection includes a random access memory having one or more modules (each memory module having module configuration data), a nonvolatile storage element having configuration data for each of the memory modules stored thereon, and a processor module adapted to determine if the configuration data from one of the memory modules is incorrect and, if it is, use at least a portion of the configuration data stored in the nonvolatile storage element to replace at least a portion of the configuration data of the memory module having the incorrect configuration data.

Abstract: A test system for functionally testing disk drives over a wide range of power conditions. The system simulates the power conditions using a computer controlled system architecture featuring several major components. The first of these components is a computer enhanced with features allowing the computer to communicate with disk drives having either IDE or Small Computer System Interface (SCSI) formats. The computer communicates with a second component termed the programmable power supply (PPS) and a third component having simulation circuitry termed universal power simulator, or UPS. The computer uses a combination of hardware and software to create simulated power conditions which are used to test the disk drives for correct operation and to glean out defective drives. The UPS is responsive to control signals from the host computer and the PPS and sends simulated power signals to the disk drives under test.

Abstract: In a microcontroller employing a buffer descriptor ring direct memory access (DMA) unit, transmission of a packet can be split between multiple buffers. If an error occurs during the transmission of one of the buffers, the buffer descriptor ring DMA unit includes a provision that allows the software to reset the DMA channel to the first buffer containing the failed packet and to restart the transmission of the failed packet, rather than proceeding to the next packet.

Abstract: In a publish/subscribe data processing broker network having a plurality of broker data processing apparatuses, each of which has an input for receiving published messages directly from a publisher application and/or receiving subscription data directly from a subscriber application, and each of which having a means for receiving a published message on a first topic and assigning a broker-specific sequence number to the received message; a first broker apparatus has: a software unit for determining a failure of a neighboring broker apparatus which has provided published messages on the first topic to the first broker apparatus; and a software unit for sending historic resubscriptions with respect to the first topic to each antecedent broker apparatus of the failed neighboring broker apparatus by using the broker-specific sequence number corresponding to each antecedent broker apparatus.

Abstract: Apparatus for monitoring and testing a transaction system, and controlled by enterprise automation equipment. The testing apparatus is programmed with various MIB structures to provide probe points and signals to the transaction system. Responses are received by the test apparatus via check points connected to the transaction system. The test apparatus applies test signals to the probe points in a manner similar to signals applied by users of the transaction system. The responses received from the transaction system are again similar to the responses received by the user in the normal utilization of the transaction system.

Abstract: A method of managing defective data sites on a hard disk drive through a shared defect table. The method writes both skip type entries and vector type entries to the defect table. Skip type entries represent defective data sites that are to be skipped during operation of the disk drive, and vector type entries represent defective data sites which have been reassigned to spare data sites and alternate locations on the disk. Both skip type entries and vector type entries are in a common format within the defect table, where the top two data bits of each entry distinguish skip type entries from vector type entries. The method also manages a separate cross-reference table for vector type entries, where the location of the reassigned defective data site is associated with the location of a spare data site which contains the data from the reassigned site. The shared defect table provides an efficient way for distinguishing skipped and vectored defective data sites during subsequent disk operation.

Abstract: A system and method of implementing column redundancy in a memory system in which a single set of redundant columns is provided in one of a plurality of blocks of columns which is the fastest to receive decoded select signals or which is physically located closest to decode circuitry. In normal operation, the decode circuitry selects a single column and block as determined by the input address signal. In redundancy mode, the input address is compared to a pre-programmed repair column and block address corresponding to the a previously determined defective column and a match signal is generated. The match signal functions to enable the block having the redundant columns and disable the sense amplifiers of all other blocks. In addition, the match signal disables all of the columns in the selected redundancy block other than a single redundant column. As a result, all redundant columns have approximately the same access time as the fastest block of columns in the memory system.

Abstract: An error information reporting system of the present invention is applicable to an error monitoring system including a CPU (Central Processing Unit) and data output terminals. When a critical error occurs in a device being monitored, all data necessary for analysis and remedy are immediately sent to all expected destinations.

Abstract: The invention provides a computerized method and apparatus which enables a user, even one who has little or no predictive maintenance skills, to establish a predictive maintenance database that defines information needed to monitor equipment in accordance with a predictive maintenance plan. The type of equipment components to be monitored and associated physical characteristics of the components are input to a computer as an equipment configuration, which may include one or more interconnected components. The computer includes a knowledge base that defines relationships between monitoring practices, component types, and physical characteristic information for component types. A predictive maintenance database is constructed for the components using the inference engine operating on the knowledge base, the selected component type, and the selected physical characteristic information. Multiple measurement technologies may be specified for each component.

Abstract: An apparatus and a method detect and automatically correct an illegal address in a peripheral connect interface bus addressing scheme. The value of a current bit is read. The value of a bit immediately left adjacent of the current bit is read. A value of 0 is outputted as the current bit in the event the value of the current bit is 1 and the value of the left adjacent bit is 0. In one specific embodiment, the apparatus employs a multiplexer and a single-bit register with a feedback as a one bit detection and correction circuit.

Abstract: A monitoring system generates alerts indicating predefined conditions exist in a computer system. Alerts are generated by comparing alert definitions to a host state representing the state of the hardware and software components of a computer system. to determine if conditions defined in the alert definitions exist in the host state; and generating alerts accordingly. The host state is a static tree structure including elements in a fixed hierarchical relationship, the elements being given value by associated tokens, the elements and associated tokens representing the hardware and software components of the computer system. The alert definitions generate alerts according to the values of at least one token, at least one alert or a combination of various tokens and/or alerts. The host state is created by providing a static tree structure representing a general computer system.

Abstract: The present invention pertains to a system and method for tracking object references in an object-oriented computing system including a number of independent computing nodes interconnected by a communications link. The reference counting mechanism tracks references to an object through the use of a messaging protocol. A server node keeps a foreign reference count for each of its objects. The foreign reference count indicates the number of remote nodes having a reference to one of the servers objects. A server node increments the foreign reference count for each object reference that it exports prior to sending it to an intended client node. A client node will send a message to the server node when it has already received the exported object reference and in response to this message, the server node decrements the appropriate foreign reference count.

Abstract: A standalone virtual device driver that is not a mouse driver replacement or a mouse minidriver examines mouse data packets received from the mouse hardware for data packets that are obviously or likely to be faulty. When such a data packet is detected, the virtual device driver also removes the suspected faulty data by returning a null mouse packet to the mouse driver in its place. The virtual device driver may also initiate resynchronization procedures or reset the mouse hardware if necessary.

Abstract: A disk controlling apparatus creates sense data indicating the contents of an error and writes it into an intermediate buffer provided within the disk controlling apparatus together with the record normally read when a key portion or a data portion constituting a record is not normally read. The disk controlling apparatus searches the intermediate buffer for desired record, reads and informs an error while taking the sense data into consideration for each record. The disk controlling apparatus stores a write address in a memory at the time of writing data, and when data are normally written the write address is eliminated from the memory, while holding the address when data are not normally written. At the time of reading data, if the address which agrees with the read address is stored in the memory, the disk controlling apparatus reports an error to a host apparatus.

Abstract: A method and system for accurately indicating test results from testing routines of a self-check operation during initialization or reset of the system utilize test result bits in a secure status register that must be sequentially reset to indicate a successful completion of the self-check operation. The system is a microcontroller that can be incorporated into various consumer products requiring digital processing. Each test result bit represents a distinct component of the system that is tested during the self-check operation. The test result bits in the status register can only be reset one at a time, by activating a demultiplexer which resets a particular test result bit in response to a successful testing of a component. However, the demultiplexer can only be activated by modifying a control bit in an access register that is protected by a double password scheme. To modify the control bit, the CPU must provide two valid passwords.

Abstract: A tractable architecture level coverage measure uses information about the coverage measures obtained by the data path blocks, control logic blocks and cache to obtain an overall measure of coverage. This technique is applicable to a variety of different designs using different fabrication processes. Moreover, it allows the use of extended length test vectors, for example, such as those using commercial software applications. Since the coverage measure does not rely on the traditional stuck at model, it is applicable to extended length test vectors that may be used with high performance systems.

Abstract: A multi-processor system and methodology optimize overhead costs associated with manufacturing large integrated circuit devices having multiple data processors and processing elements thereon by effectively disabling processing elements that are not functional. Disabling the processing elements is performed through segmented power distribution on an integrated circuit first-level package or by providing inhibit signals in pre-selected logic states based on the functionality of the multi-processing system. The functionality of the multiprocessing system is determined during an initial testing procedure, including wafer-level testing.

Abstract: A device for replacing defective storage locations with working storage locations comprises receiving means for receiving an incoming address for accessing a storage location, comparing means for comparing the incoming address with all of the addresses of known defective storage locations, and directing means for directing accesses to an alternative location when the incoming address matches one of the addresses of known defective storage locations. There is one alternative storage location and one comparing means for each known defective storage location. In this invention only a portion of the incoming address is used in the comparing means. In addition, each of the comparing means may use a different portion of the address for accessing a storage location.

Abstract: A multiprocessor system includes a plurality of processors. A debugger interface includes interface circuitry to interface the plurality of processors to a debugger. The debugger interface includes means for receiving a debugger command from the debugger. Debugger command directing means determines from the debugger command for which of at least one of the plurality of processors the debugger command is intended, directs the debugger command, via the interface circuitry to the at least one intended processor. A processor command is received from one of the plurality of processors, and processor command directing means directs the processor command, received from the one processor, via the interface circuitry to the debugger. The system is especially suited for debugging software that is executing on the plurality of processors of the multiprocessor system.

Abstract: An apparatus for tracking processing of commands between command sources and sinks includes a command directory. The command directory receives a command from at least one command source, receives signals from command sinks, generates status information corresponding to the command based on the command and the received signals, and stores the status information. The status information indicates to which command sink the command is to be routed, whether the command sink has accepted the command, and whether the command sink has completed processing the command. The command directory includes a command buffer having a plurality of directory entries. The command buffer stores a command and associated status information in a directory entry. The command buffer also includes free buffer logic which monitors the status information in each directory entry. Based on this monitoring, the free buffer logic determines whether a directory entry has been disabled or whether command tracking errors exist.

Abstract: A method, apparatus, and computer program product for testing a computer system having a set of computer components and a testing program stored in memory provides both a test header file associated with a selected component, and a component file listing the set of components of the computer system. The test header file and component header file are compared to determine if the selected computer component is one of the set of components of the computer system. If it is determined that the selected component is one of the set of components of the computer system, then the testing program is executed.

Abstract: A multi-client test harness for testing first and second computer systems by executing a first test case on the first and second computer systems. The multi-client test harness includes a scheduler module. The scheduler module initiates execution of the first test case on the first computer system and the second computer system responsive to attest initiation event. The scheduler module synchronizes the execution of the first test case on the first and second computer systems such that the first test case executes on the first computer system at substantially the same time that the first test case executes on the second computer system.

Abstract: An apparatus and method are provided for the development, testing and verification of a logic design of a programmable logic device in a real-time user environment to simplify the development of the programmable logic device and associated systems. The apparatus comprises an emulation programmable logic device based on the same family and package of the target programmable logic device. The adapter further comprises a plurality of individually programmable switches for selectively coupling the emulation device to the target device or to a logic device substituting for the target device. The apparatus further comprises a controller, which configures the switches based on control signals received from a host computer system, such that a stimulus applied to the input pins of the target or substitute device are also applied concurrently to the corresponding input pins of the emulation device.

Abstract: A method and apparatus for a dual power supply on a universal serial bus system using an overcurrent detect circuit. Dual power supplies in the universal serial bus system allows for greater flexibility of operation and is based on two separate power systems. The first power system is achieved using the power line on the bus connecting to the universal serial bus controller. The second power system is a separate power supply to power the downstream ports. Moreover, the universal serial bus system has an overcurrent and thermal error detect circuit based on the power system in order to achieve an efficient and cost effective method and apparatus in which to notify the universal serial bus controller of any error in the power system.

Abstract: A dual-port RAM-type ring-address FIFO including a data input register with a set of transparent latches is tested by causing the FIFO to execute a test method comprised of a set of interwoven steps. Upon execution, the steps of the method cause the FIFO to manifest all possible memory, address and functional faults. This test method manifests faults by causing the FIFO to alter the state of various flags it normally sets and by altering the logic state of the data normally produced by the FIFO.

Abstract: A model-based process for translating test programs from a first computer language to a second computer language includes the steps of extracting test strategy and replaceable item callouts from an existing test program in the first language, converting the extracted test strategy into an asymmetric dependency model, converting the dependency model into a model-based test strategy, extracting code segments from the existing test program, translating the extracted code segments into the second language, and merging the model-based test strategy and the translated code segments into a new test program in the second language.